• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A low current amplifier circuit which stably operates at a low current and has a reduced tendency to cause static breakdown includes first and second field-effect transistors. The first field-effect transistor has a gate with a small width for passing a small current when a bias voltage is applied to the gate to compensate for variations in threshold voltage. The second field-effect transistor has a gate with a larger width than that of the first field-effect transistor and a source connected to a drain of the first field-effect transistor. The second field-effect transistor reduces a current flowing through the first field-effect transistor due to static electricity.
    公开号:US20010009390A1
    申请号:US09/769,540
    申请日:2001-01-25
    公开日:2001-07-26
    发明作者:Keiji Kusachi
    申请人:NEC Corp；
    IPC主号:H03F3-1935
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The present invention relates to an amplifier circuit which operates at a low current. [0002]
    [0003] 2. Description of the Related Art [0003]
    [0004] An LO (Local Oscillator) buffer amplifier is one of amplifier circuits for local oscillator peripheral circuits used in a frequency converter in a receiving section of a cellular phone. In recent years, since low power consumption is highly required in cellular phones, the LO buffer amplifier need operate at a low current of approximately 1 to 2 mA. [0004]
    [0005] FIG. 1 is an equivalent circuit diagram of an amplifier circuit of a first prior art with a pseudo enhancement mode HJ (Hetero Junction)-FET. The pseudo enhancement mode HJ-FET refers to a hetero-junction field-effect transistor with a threshold voltage Vth of approximately −0.1 V. [0005]
    [0006] The amplifier circuit of the first prior art comprises input/output circuit [0006] 15 for amplifying an input signal at a radio frequency and providing an output signal, power supply circuit 25 for supplying input/output circuit 15 with power, active bias circuit 35 for supplying input/output circuit 15 with a bias voltage, and capacitor 154 for removing direct-current components in the output signal. Input/output circuit 15 and active bias circuit 35 are arranged within an IC such as an MMIC (Monolithic Microwave Integrated Circuit) with a pseudo enhancement mode HJ-FET, and power supply circuit 25 and capacitor 154 are provided outside the IC.
    [0007] Input/output circuit [0007] 15 includes capacitor 151 for removing direct-current components in the input signal, resistor 152 for providing a load to the bias voltage supplied from active bias circuit 35, and field-effect transistor 153 for amplifying the input signal. Capacitor 151 is connected between an input terminal and a gate of field-effect transistor 153. Resistor 152 is connected between an input from active bias circuit 35 and the gate of field-effect transistor 153. A source of field-effect transistor 153 is grounded. Field-effect transistor 153 has a gate width of 200 μm, and if the bias voltage is, for example 0.2 V, a current of approximately 6 mA flows.
    [0008] A drain of field-effect transistor [0008] 153 is connected to one terminal of capacitor 154, and the other terminal of capacitor 154 serves as the output from the amplifier circuit.
    [0009] Power supply circuit [0009] 25 includes voltage source 251 for supplying a direct-current voltage, capacitor 252 for removing noise in the power supply, and load inductor 253 for providing a load to output from voltage source 251. Capacitor 252 is connected between an output of voltage source 251 and a ground potential. Load inductor 253 has one terminal connected to the output of voltage source 251 and the other terminal connected to the drain of transistor 153.
    [0010] Active bias circuit [0010] 35 includes field-effect transistor 351 for controlling the bias voltage supplied to input/output circuit 15, and resistors 352, 353, and 354. Resistor 352 has one terminal connected to the drain of field-effect transistor 153 and the other terminal which is connected to a drain of field-effect transistor 351 and to one terminal of resistor 353 and supplies the bias voltage to input/output circuit 15. The other terminal of resistor 353 is connected to a gate of field-effect transistor 351 and to one terminal of resistor 354. A source of field-effect transistor 351 and the other terminal of resistor 354 are grounded.
    [0011] In the amplifier circuit of the first prior art, input/output circuit [0011] 15 supplied the power from power supply circuit 25 biases an input signal with the bias voltage provided by active bias circuit 35, and amplifies and provides the signal.
    [0012] FIG. 2 is an equivalent circuit diagram showing an amplifier circuit of a second prior art. [0012]
    [0013] The amplifier circuit of the second prior art has field-effect transistor [0013] 161 with a gate width of 50 μm instead of field-effect transistor 153 in the first prior art, and the remaining configuration is the same as that of the first prior art.
    [0014] Since the gate width is as thin as 50 μm in the second prior art, it is possible to suppress a current to approximately 0.2 mA even when a bias voltage of 0.2 V is applied. [0014]
    [0015] FIG. 3 is an equivalent circuit diagram showing an amplifier circuit of a third prior art. [0015]
    [0016] In the amplifier circuit of the third prior art, load inductor [0016] 253 in power supply circuit 25 of the second prior art is eliminated, and load inductor 171 is included as an IC internal circuit between the connection of constant-voltage source 251 and capacitor 154 and the connection of field-effect transistor 161 and resistor 352. The remaining configuration is the same as that of the amplifier circuit of the second prior art.
    [0017] In the amplifier circuit of the third prior art, since load inductor [0017] 171 reduces static electricity from the outside applied between the drain and the source, a current is suppressed to approximately 2 mA, and breakdown due to static electricity is also unlikely to occur.
    [0018] FIG. 4 is an equivalent circuit diagram showing an amplifier circuit of a fourth prior art. [0018]
    [0019] The amplifier circuit of the fourth prior art is of a self-bias type, and includes resistor [0019] 181 and bypass capacitor 182 in parallel between a source of field-effect transistor 153 and a ground potential in the configuration of the amplifier circuit of the first prior art. The remaining configuration is the same as that of the amplifier circuit of the first prior art.
    [0020] Since the amplifier circuit of the fourth prior art is of the self-bias type and cancels a bias voltage at a gate of the transistor with a bias voltage at the source, it can operates at a low current. [0020]
    [0021] The amplifier circuits shown as the first to fourth prior arts suffer from the following problems. [0021]
    [0022] Theoretically, the amplifier circuit of the first prior art can be operated at a low current with a bias voltage of 0 V, but actually, the bias voltage cannot be set at 0V to compensate for variations in the threshold voltage Vth of fired-effect transistor [0022] 153. Specifically, in the amplifier circuit of the first prior art, the threshold voltage Vth of the pseudo enhancement mode HJ-FET has variations ranging from −0.2 V to 0 V as shown in FIG. 5, and the bias voltage need be set at 0.2 V or higher to compensate for the variations. Since a bias voltage of 0.2 V causes a current of approximately 6 mA to pass through field-effect transistor 153, it is impossible to realize a low current of 1 to 2 mA required for an amplifier circuit in a cellular phone.
    [0023] The amplifier circuit of the second prior art has its gate as thin as of 50 μm and can operate at a low current, but breakdown readily occurs due to static electricity between the drain and the source. [0023]
    [0024] While the amplifier circuit of the third prior art can operate at a low current and the static breakdown is unlikely to occur, the IC chip size is large since load inductor [0024] 171 which is a spiral inductor occupies a large area within the MMIC. In addition, the load inductor disposed outside the IC in the other prior arts is included within the IC, thereby reducing the choice of inductance value.
    [0025] In the fourth prior art, the capacitance of bypass capacitor [0025] 182 cannot be reduced sufficiently since the impedance is large. Thus, at a high frequency, a short circuit is insufficient and negative resistance tends to be arisen, resulting in unstable operations of field-effect transistor 153. Also, a highly dielectric film is required for forming bypass capacitor 182, and complicated manufacturing steps and higher cost are involved. SUMMARY OF THE INVENTION
    [0026] It is an object of the present invention to provide a low current amplifier circuit which stably operates at a low current and has a reduced tendency to cause static breakdown. [0026]
    [0027] The low current amplifier circuit according to the present invention comprises a power supply circuit, a bias circuit, and first and second field-effect transistors. [0027]
    [0028] The power supply circuit provides power supply voltage. The bias circuit biases an input signal. The first field-effect transistor has a small gate width to pass a small current when a bias voltage is applied to its gate to compensate for variations in threshold voltage. The first field-effect transistor has its grounded source and its gate to which an input signal biased with the bias voltage is applied. The second field-effect transistor has a larger gate width than that of the first field-effect transistor, its source connected to a drain of the first field-effect transistor, and its drain supplied with the power supply voltage. [0028]
    [0029] In the low current amplifier circuit of the present invention, a current from static electricity flows through the second field-effect transistor connected in a cascade to the first field-effect transistor, and a current flowing between the drain and the source of the first field-effect transistor is reduced. Thus, the first field-effect transistor having a small gate width for realizing a low current can be protected against the static electricity by the second field-effect transistor having a larger gate width. [0029]
    [0030] The gate of the first field-effect transistor has a width for allowing the transistor to operate at a current of 2 mA or lower when the bias voltage is applied to the gate, and preferably, the width is 50 μm or less. [0030]
    [0031] The gate of the second field-effect transistor has a width for not readily causing static breakdown of the transistor even when a voltage from static electricity is applied between the drain and the source, and preferably, the width is 200 μm or more. [0031]
    [0032] The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention. [0032] BRIEF DESCRIPTION OF THE DRAWINGS
    [0033] FIG. 1 is an equivalent circuit diagram showing an amplifier circuit of a first prior art with a pseudo enhancement mode HJ-FET; [0033]
    [0034] FIG. 2 is an equivalent circuit diagram showing an amplifier circuit of a second prior art; [0034]
    [0035] FIG. 3 is an equivalent circuit diagram showing an amplifier circuit of a third prior art; [0035]
    [0036] FIG. 4 is an equivalent circuit diagram showing an amplifier circuit of a fourth prior art; [0036]
    [0037] FIG. 5 is a graph showing transfer characteristics of the amplifier circuit shown in FIG. 1; [0037]
    [0038] FIG. 6 is an equivalent circuit diagram showing an amplifier circuit of an embodiment of the present invention configured with a pseudo enhancement mode HJ-FET; and [0038]
    [0039] FIG. 7 is an equivalent circuit diagram showing an amplifier circuit of another embodiment of the present invention. [0039] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0040] Referring now to FIG. 6, there is shown an amplifier circuit according to an embodiment of the present invention configured with a pseudo enhancement mode HJ-FET which comprises input/output circuit [0040] 10, power supply circuit 20, active bias circuit 30, and capacitor 108. Input/output circuit 10 amplifies an input signal at a radio frequency and provides it. Power supply circuit 20 supplies input/output circuit 15 with power. Active bias circuit 30 supplies input/output circuit 15 with a bias voltage. Capacitor 108 removes direct-current components from the output. Input/output circuit 10 and active bias circuit 30 are configured as an internal circuit of an IC such as an MMIC, while power supply circuit 20 and capacitor 108 are provided outside the IC.
    [0041] Input/output circuit [0041] 10 includes capacitor 101, resistor 102, field-effect transistor 103 and 104, resistors 105 and 106, and capacitor 107.
    [0042] Capacitor [0042] 101 is connected between an input terminal and a gate of field-effect transistor 103, and removes direct-current components from an input signal. Resistor 102 is connected between an output of active bias circuit 30 and the gate of field-effect transistor 103, and gives a load to the bias voltage supplied from active bias circuit 30. Field-effect transistor 103 has its source grounded, its drain connected to the source of field-effect transistor 104. Field-effect transistors 103 and 104 amplify an input signal. Resistor 105 is connected between the gate and the drain of field-effect transistor 104, and resistor 106 and capacitor 107 are connected in parallel between the gate of field-effect transistor 104 and a ground potential. Resistors 105 and 106 divide the voltage supplied from power supply circuit 20 and apply a bias voltage to the gate of field-effect transistor 104. Capacitor 107 provides a bypass between the gate of field-effect transistor 104 and the ground potential at a radio frequency.
    [0043] The gate width of field-effect transistor [0043] 103 is 50 μm, and the gate width of field-effect transistor 104 is 200 μm.
    [0044] Capacitor [0044] 108 has its one terminal connected to the drain of field-effect transistor 104 and its other terminal connected to the output terminal of the amplifier circuit.
    [0045] Power supply circuit [0045] 20 includes voltage source 201 for supplying a direct-current voltage, capacitor 202 for removing noise in the power supply, and load inductor 203 for giving a load to output from voltage source 201. Capacitor 202 is connected between an output of voltage source 201 and a ground potential. Load inductor 203 has its one terminal connected to the output of voltage source 201 and its other terminal connected to the drain of field-effect transistor 104.
    [0046] Active bias circuit [0046] 30 includes field-effect transistor 301 for controlling the bias voltage supplied to input/output circuit 10, and resistors 302, 303, and 304. Resistor 302 has its one terminal connected to the drain of field-effect transistor 104 and its other terminal connected to a drain of field-effect transistor 301. Resistor 303 is connected between a gate and the drain of field-effect transistor 301. Resistor 304 is connected between the gate of field-effect transistor 301 and a ground potential. A source of field-effect transistor 301 is grounded.
    [0047] The input signal is biased with the bias voltage supplied from active bias circuit [0047] 30 and amplified by field-effect transistors 103 and 104 to output. At this point, since the gate width of field-effect transistor 103 is 50 μm, it can operate at a current of 1 to 2 mA.
    [0048] Since the field-effect transistor with its gate grounded has a small input impedance, field-effect transistor [0048] 104 is mainly responsible for amplification, and field-effect transistor 103 mainly serves as a current source.
    [0049] For operations against static electricity, a current flows through field-effect transistor [0049] 104 with a gate width of 200 μm, thereby reducing a current flowing between the drain and the source of field-effect transistor 103 with a gate width of 50 μm.
    [0050] Since the current from the static electricity flowing between the drain and the source of field-effect transistor [0050] 103 is reduced, field-effect transistor 103 having a small gate width is unlikely to be broken due to the static electricity. Therefore, lower power consumption can be achieved in cellular phones and amplifier circuits less prone to static breakdown can be realized.
    [0051] Referring to FIG. 7, there is shown an amplifier circuit of another embodiment of the present invention. The amplifier circuit has a configuration in which second capacitor [0051] 107 and third resistor 106 are eliminated from the amplifier circuit shown in FIG. 6, and the remaining configuration is the same as that of the amplifier circuit shown in FIG. 6.
    [0052] In the amplifier circuit shown in FIG. 7, similarly to the amplifier circuit shown in FIG. 6, an input signal is biased with a bias voltage supplied from active bias circuit [0052] 30 and amplified by field-effect transistors 103 and 104 to output. Since field-effect transistor 103 has a gate width of 50 μm, it can also operate at a current of 1 to 2 mA similarly to the amplifier circuit shown in FIG. 6.
    [0053] For operations against static electricity, a current flows through field-effect transistor [0053] 104 and a current flowing between a drain and a source of field-effect transistor 103 is reduced similarly to the amplifier circuit shown in FIG. 6. Therefore, it is possible to make an amplifier circuit less prone to static breakdown and operating at a low current.
    [0054] The amplifier circuit shown in FIG. 7, however, differs from the amplifier circuit shown in FIG. 6 in that field-effect transistor [0054] 103 is mainly responsible for amplification and field-effect transistor 104 mainly serves as a current source.
    [0055] While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims. [0055]
    权利要求:
    Claims (7)
    [1" id="US-20010009390-A1-CLM-00001] 1. A low current amplifier circuit comprising:
    a power supply circuit for providing power supply voltage;
    a bias circuit for biasing an input signal;
    a first field-effect transistor having a gate with a small width for allowing a small current pass therethrough when a bias voltage is applied to said gate to compensate for variations in threshold voltage, and its source grounded, said gate receiving an input signal biased with said bias voltage; and
    a second field-effect transistor having its gate with a larger width than that of said first field-effect transistor, its source connected to a drain of said first field-effect transistor, and its drain supplied with said power supply voltage.
    [2" id="US-20010009390-A1-CLM-00002] 2. The low current amplifier circuit according to
    claim 1 , wherein said gate of said first field-effect transistor has a width for allowing said first field-effect transistor to operate at a current of 2 mA or less when said bias voltage is applied to said gate, and
    said gate of said second field-effect transistor has a width for not readily causing static breakdown in said second field-effect transistor even when a voltage from static electricity is applied between said drain and said source.
    [3" id="US-20010009390-A1-CLM-00003] 3. The low current amplifier circuit according to
    claim 2 , wherein said gate width of said first field-effect transistor is 50 μm or less.
    [4" id="US-20010009390-A1-CLM-00004] 4. The low current amplifier circuit according to
    claim 2 , wherein said gate width of said second field-effect transistor is 200 μm or more.
    [5" id="US-20010009390-A1-CLM-00005] 5. The low current amplifier circuit according to
    claim 1 , further comprising a first resistor connected between said drain and said gate of said second field-effect transistor.
    [6" id="US-20010009390-A1-CLM-00006] 6. The low current amplifier circuit according to
    claim 5 , further comprising a second resistor and a capacitor connected in parallel between said gate of said second field-effect transistor and a ground potential.
    [7" id="US-20010009390-A1-CLM-00007] 7. The low current amplifier circuit according to
    claim 1 , further comprising:
    a first capacitor connected between said gate of said first field-effect transistor and an input terminal; and
    a second capacitor connected between said drain of said second field-effect transistor and an output terminal.
    类似技术:
    公开号 | 公开日 | 专利标题
    JP4206589B2|2009-01-14|Distributed amplifier
    US5952860A|1999-09-14|Amplifier using a single polarity power supply
    US7619482B1|2009-11-17|Compact low voltage low noise amplifier
    US6472941B2|2002-10-29|Distributed amplifier with terminating circuit capable of improving gain flatness at low frequencies
    US7274258B2|2007-09-25|Dynamic bias circuit for a radio-frequency amplifier
    US7358817B2|2008-04-15|Linearized bias circuit with adaptation
    US7728672B2|2010-06-01|RF amplifier
    JPH09260957A|1997-10-03|Semiconductor amplifier circuit
    US4890069A|1989-12-26|Gallium arsenide power monolithic microwave integrated circuit
    US10320350B1|2019-06-11|System and method for bypassing a low noise amplifier
    US6542036B2|2003-04-01|Low current amplifier circuit with protection against static electricity
    JP6689450B2|2020-04-28|Current reuse field effect transistor amplifier
    JP2008103889A|2008-05-01|Low-noise amplifier
    US10116273B2|2018-10-30|Current reuse field effect transistor amplifier
    JP3657079B2|2005-06-08|Integrated circuit device having enhancement type transistor circuit bias circuit
    KR101363174B1|2014-02-13|Power amplifier having depletion mode high electron mobility transistor
    US20030214358A1|2003-11-20|Multistage amplifier circuit capable of boosting output power
    JPH08265065A|1996-10-11|Amplifier circuit
    JP2013034090A|2013-02-14|Amplifier
    US10944363B2|2021-03-09|Power amplifier
    US6452370B1|2002-09-17|Low noise biasing technique
    JP5126676B2|2013-01-23|Amplifier
    CN112152575A|2020-12-29|Low-noise amplifier circuit with high input dynamic range
    JP3068000B2|2000-07-24|Front end circuit
    JP3176793B2|2001-06-18|Amplifier circuit
    同族专利:
    公开号 | 公开日
    JP3515725B2|2004-04-05|
    JP2001211033A|2001-08-03|
    US6542036B2|2003-04-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2003001661A1|2001-06-26|2003-01-03|Koninklijke Philips Electronics N.V.|Self-biased cascode rf power amplifier in sub-micron|JPH02105468A|1988-10-13|1990-04-18|Nec Corp|Field effect transistor circuit|
    JPH04105358A|1990-08-24|1992-04-07|Nec Corp|Semiconductor device|
    JP2882309B2|1995-04-28|1999-04-12|日本電気株式会社|Input protection circuit and method of manufacturing semiconductor integrated circuit device|
    EP1081573B1|1999-08-31|2003-04-09|STMicroelectronics S.r.l.|High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers|
    US6407640B1|2000-09-22|2002-06-18|Qualcomm, Incorporated|Two-stage LNA with good linearity|US6888411B2|2003-06-06|2005-05-03|Broadcom Corporation|Radio frequency variable gain amplifier with linearity insensitive to gain|
    US6888410B1|2003-10-10|2005-05-03|Broadcom Corp.|Power amplifier having low gate oxide stress|
    JP5743850B2|2011-10-28|2015-07-01|株式会社東芝|Integrated circuit|
    法律状态:
    2001-01-25| AS| Assignment|Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KUSACHI, KEIJI;REEL/FRAME:011482/0392 Effective date: 20010117 |
    2002-11-20| AS| Assignment|Owner name: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013505/0932 Effective date: 20020919 |
    2006-04-04| AS| Assignment|Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.;REEL/FRAME:017422/0528 Effective date: 20060315 |
    2006-09-08| FPAY| Fee payment|Year of fee payment: 4 |
    2010-09-01| FPAY| Fee payment|Year of fee payment: 8 |
    2010-11-18| AS| Assignment|Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025375/0918 Effective date: 20100401 |
    2014-11-07| REMI| Maintenance fee reminder mailed|
    2015-04-01| LAPS| Lapse for failure to pay maintenance fees|
    2015-04-27| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2015-05-19| FP| Lapsed due to failure to pay maintenance fee|Effective date: 20150401 |
    优先权:
    申请号 | 申请日 | 专利标题
    JP2000017187A|JP3515725B2|2000-01-26|2000-01-26|Low current amplifier circuit|
    JP2000-017187||2000-01-26||
    [返回顶部]