美国专利US20010009245A1 Etching methods, methods of removing portions of material, and methods of forming silicon nitride sp

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专利摘要:
In one aspect, the invention includes a method of removing at least a portion of a material from a substrate, comprising: a) first etching the material in a reaction chamber; b) second etching the material in the reaction chamber; and c) cleaning a component of the material from at least one sidewall of the reaction chamber between the first etching and the second etching. In another aspect, the invention includes a method of patterning a material over a semiconductive substrate, comprising: a) forming a layer of first material against a second material and over a semiconductive substrate, the semiconductive substrate comprising a surface having a center and an edge; b) first etching the first material in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the first material relative to the second material; c) second etching the first material in the reaction chamber, the second etching comprising a second center-to-edge uniformity across the surface of the wafer and comprising a second selectivity for the first material relative to the second material, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity; and d) cleaning a component of the first material from at least one sidewall of the reaction chamber between the first etching and the second etching.
公开号:US20010009245A1
申请号:US09/797,355
申请日:2001-02-28
公开日:2001-07-26
发明作者:Tuman Allen
申请人:Allen Tuman Earl；
IPC主号:H01L21-31116

专利说明:
[0001] The invention pertains to etching methods, such as, for example, methods of forming silicon nitride spacers. [0001] BACKGROUND OF THE INVENTION
[0002] A commonly utilized method for removing at least some of a material is plasma etching. Such method can be used, for example, in semiconductor processing. An enormous diversity of materials can be removed by appropriately adjusting etchant components and etching parameters. Among the materials that can be removed are polycrystalline silicon, silicon nitride and silicon oxides. Etchants that can be utilized for removing polycrystalline silicon include HCl, HBr, HI, and Cl[0002] ₂, alone or in combination with each other and/or one or more of He, Ar, Xe, N₂, and O₂. A suitable etchant that can be utilized for removing a silicon oxide, such as silicon dioxide, is a plasma comprising CF₄/CHF₃, or CF₄/CH₂F₂. Additionally, a suitable etchant for removing silicon oxide is a plasma comprising a large amount of CF₃, and a minor amount of CH₂F₃. A suitable etchant for removing silicon nitride is a plasma comprising CF₄/HBr.
[0003] An example prior art reaction vessel [0003] 10 is illustrated in FIG. 1. Reaction vessel 10 comprises a plurality of sidewalls 12 surrounding an internal reaction chamber 14. Also, reaction vessel 10 comprises a radio frequency (RF) generating coil 16 surrounding a portion of reaction chamber 14 and connected to a first RF source 18. RF coil 16 is configured to generate a plasma within reaction chamber 14.
[0004] A substrate [0004] 20 is received within internal chamber 14 and connected to a second RF source 22. Second RF source 22 is configured to generate an RF bias at substrate 20. Additionally, reaction vessel 10 can comprise coolant coils (not shown) configured to cool a backside of substrate 20 and thereby maintain substrate 20 at a desired temperature during an etching process. It is to be understood that vessel 10 is an exemplary etching vessel. Other constructions are possible. For instance, reaction vessel 10 utilizes a cylindrical inductively driven source geometry, but planar or other inductively driven source geometries can be used. Also, reaction vessel 10 is shown utilizing two separate RF sources, 18 and 20, but other constructions can be used wherein a single RF source can be utilized and the RF power from such source split to form a first RF power at coil 16 and an RP bias at substrate 20.
[0005] Substrate [0005] 20 can comprise, for example, a monocrystalline silicon wafer. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
[0006] In operation, plasma gases (not shown) are flowed into internal chamber [0006] 14 and converted into a plasma by energy input from reaction coil 16. An RF bias is generated at substrate 20, and such RF bias draws plasma components to a surface of substrate 20 to etch a material at such surface.
[0007] During etching of a component from substrate [0007] 20, the materials produced by chemical reaction to the substrate with etch gases are released into the internal chamber. Such materials are referred to herein as etch reaction products, or as etchant debris. A method of determining when an etch has penetrated a material is to monitor the concentration of the evolved reaction products and/or etchant gases as the etch proceeds. Monitoring of the etchant debris can be accomplished by, for example, spectroscopic methods, including, for example, ultraviolet-visible spectroscopy and mass spectrometry. Preferably, the monitoring will be performed by an automated system, with software configured to detect when a concentration of a monitored material decreases within the etchant debris.
[0008] In the shown embodiment, a monitoring device [0008] 28 is provided to observe etchant debris within reaction chamber 14 through a window 26. Monitoring device 28 can comprise, for example, a spectrometer. The spectrometer can be configured to, for example, display a signal corresponding to a concentration of a particular component in the etchant debris, and/or to send such signal to an automated mechanism which performs a function in response to particular signal characteristics. An example automated system is a system comprising an algorithm to analyze the signal and determine from the analysis when an etch penetrates a particular material. The automated system can be configured to terminate the etching process in response to a determination that the etch has penetrated the particular material.
[0009] An etch will frequently be conducted in two distinct etching steps, particularly if the etching is to remove a thickness of material that is greater than or equal to 200 Angstroms. First, a highly physical (non-selective) etch is utilized to etch through the majority of a material. Second, a chemical-type etch (highly selective) is utilized to etch through a remainder of the material. A less selective (physical-type) etch generally has better center-to-edge uniformity than a more selective (chemical-type) etch. Center-to-edge uniformity can be understood by reference to FIG. 2 wherein a semiconductive wafer [0009] 40 is illustrated. Wafer 40 comprises an edge region 42 and a center region 44. Generally, an etch process will etch material from both edge region 42 and center region 44, as well as from regions intermediate edge region 42 and center region 44. Etching frequently progresses at a different rate at edge region 42 than at center region 44. Thus, as an etch progresses further into a material of semiconductive wafer 40, a disparity between etchant depth at center region 44 and edge region 42 becomes more pronounced. Center-to-edge uniformity is a measure of a degree of disparity between an etch rate at edge region 42 versus an etch rate at center region 44.
[0010] Physical-type etch processes generally have a high degree of center-to-edge uniformity, and therefore etch edge region [0010] 42 at about the same rate as center region 44. In contrast, chemical-type edges typically have a lower degree of center-to-edge uniformity, and accordingly etch edge region 42 at a significantly different rate than center region 44.
[0011] A reason for utilizing a physical-type etch initially in an etching process is to maintain a high degree of center-to-edge uniformity as the bulk of a material is etched. The etching process is then changed to a more chemical-type etch as a final portion of the material is removed to obtain a high degree of selectivity for the material relative to other materials that can be exposed during latter stages of an etch. [0011]
[0012] A chemical-type etch and a physical-type etch can utilize the same etchants but vary in power settings and pressures, or can utilize different etchants at either the same or different power settings and pressures. If the physical-type etch and chemical-type etch comprise the same etchants, the physical-type etch generally comprises a higher bias power at a substrate, and a lower pressure within a reactor than the chemical-type etch. For example, both chemical-type etching and physical-type etching of a silicon nitride material can utilize an etchant comprising CF[0012] ₄/HBr. However, the physical-type etching will utilize an RF power to primary RF coil 16 of from about 250 to about 800 watts, a bias power to substrate 20 of from about 75 to about 400 watts, and a pressure within internal chamber 14 of from about 5 to about 15 mTorr. In contrast, a chemical-type etch will utilize a power to primary RF coil 16 (FIG. 1) of from about 300 to about 900 watts, a bias power to substrate 20 of less than about 20 watts, and a pressure within internal chamber 14 of from about 40 to about 70 mTorr.
[0013] A difficulty in etching methods can occur during monitoring of etchant debris. For instance, a nitride spacer etch is described with reference to FIGS. [0013] 3-5, with a semiconductor wafer fragment 50 illustrated before an etch (FIG. 4) and after the etch (FIG. 5), and a graph of nitrogen-containing components in debris from the etch shown in FIG. 3. In the before-etch-construction of FIG. 4, wafer fragment 50 comprises a substrate 52 having a transistor gate construction 54 formed thereover. Substrate 52 can comprise, for example, monocrystalline silicon lightly doped with a P-type dopant. Transistor gate structure 54 comprises a silicon dioxide layer 56, a polycrystalline silicon layer 58, a metal-silicide layer 60, and an insulative cap 62. Metal-silicide layer 60 can comprise, for example, titanium-silicide or tungsten-silicide, and insulative cap 62 can comprise, for example, silicon dioxide or silicon nitride. In the shown construction, silicon dioxide layer 56 extends beyond lateral peripheries of gate construction 54 and over an upper surface of substrate 52. A silicon nitride layer 64 is formed over silicon dioxide layer 56, as well as over gate structure 54. In other constructions (not shown) an extent of silicon dioxide layer 56 can be limited to within the lateral peripheries of gate construction 54, and silicon nitride layer 64 can contact substrate 52 in regions beyond the lateral peripheries of gate construction 54.
[0014] Referring to FIG. 5, an etch is conducted to pattern silicon nitride layer [0014] 64 into sidewall spacers 66. The etching has selectively stopped at oxide layer 56. Preferably, insulative cap 62 comprises silicon dioxide so that the etch of nitride layer 64 also selectively stops at cap 62.
[0015] The etch of silicon nitride layer [0015] 64 comprises two distinct etch steps, an initial physical-type etch, and a subsequent chemical-type etch. The FIG. 3 graph of nitrogen composition in etchant debris illustrates the intensity of a 386 nanometer signal obtained as a function of time. The 386 nanometer signal is associated with a C—N excitation. The physical-type etch forms a first peak region 70 of nitrogen-containing material in the etch debris, and the chemical-type etch forms a second peak region 72 of nitrogen-containing material in the etch debris. A trough region 74 occurs between peak regions 70 and 72, and corresponds to a period of time wherein etching conditions within the reaction chamber are switched from physical-type etching conditions to chemical-type etching conditions.
[0016] A difficulty occurs in monitoring peak region [0016] 72 to ascertain the precise time at which nitride layer 64 (FIGS. 4 and 5) has been etched through to oxide layer 56 (FIGS. 4 and 5). Careful observation of peak region 72 reveals a break at a location labeled 76. Such break corresponds to a significant drop in nitrogen-containing species within an etch debris, and corresponds to the time at which the shown etch has penetrated silicon nitride layer 64. Although the break at location 76 can be discerned by a person viewing peak region 72, it is difficult to create software algorithms that can accurately detect break 76 on the overall peak-shape of peak region 72. Specifically, peak region 72 comprises a sloped trailing edge before the drop in nitrogen species occurring at location 76. Such sloped trailing edge effectively creates a sloping baseline upon which location 76 is to be identified. It is difficult to create software algorithms that can reproducibly discern a change on a sloping baseline. Accordingly, it is desirable to develop methods for substantially removing the sloping trailing edge of peak region 72. SUMMARY OF THE INVENTION
[0017] In one aspect, the invention encompasses a method of removing at least a portion of a material from a substrate. The material is subjected to a first etching and a second etching in a reaction chamber. A component of the material is removed from at least one sidewall of the reaction chamber between the first etching and the second etching. [0017]
[0018] In another aspect, the invention encompasses a method of patterning a material over a semiconductive substrate. A layer of first material is formed against a second material and over a semiconductive substrate. The semiconductive substrate comprises a surface having a center and an edge. The first material is subjected to first etching in a reaction chamber. The first etching comprises a first center-to-edge uniformity across the surface of the wafer and comprises a first selectivity for the first material relative to the second material. The first material is subjected to second etching in the reaction chamber. The second etching comprises a second center-to-edge uniformity across the surface of the wafer and comprises a second selectivity for the first material relative to the second material. The second center-to-edge uniformity is less than the first center-to-edge uniformity, and the second selectivity is greater than the first selectivity. A component of the first material is cleaned from at least one sidewall of the reaction chamber between the first etching and the second etching. [0018] BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0019]
[0020] FIG. 1 is a schematic, cross-sectional side-view of a prior art plasma-etching chamber. [0020]
[0021] FIG. 2 is a schematic top view of a prior art wafer fragment. [0021]
[0022] FIG. 3 is a graph of intensity vs. time of a 386 nanometer signal in a prior art etching process. [0022]
[0023] FIG. 4 is a fragmentary, schematic, cross-sectional side-view of a semiconductor wafer fragment at a preliminary processing step of a prior processing method. [0023]
[0024] FIG. 5 is a view of the FIG. 4 wafer fragment shown at a prior art processing step subsequent to that of FIG. 4. [0024]
[0025] FIG. 6 is a graph of intensity vs. time of a 386 nanometer signal in an etching process conducted in accordance with a method of the present invention. [0025] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). [0026]
[0027] It is observed that the sloped trailing edge of prior art peak region [0027] 72 (FIG. 3) indicates that there is a diminishing amount of nitrogen containing species within a prior art etching chamber, even before the drop in nitrogen species occurring at location 76. It is also observed that such diminishing amount of nitrogen-containing species can be due to nitrogen-containing components being inadvertently displaced from sidewalls of a reaction chamber and into an etch debris during the etch of silicon nitride layer 64 (FIG. 4). One or more of several mechanisms could occur to deposit nitrogen-containing components on sidewalls of a reaction chamber. The nitrogen-containing components can be deposited on the sidewalls, for example, during either or both of a physical-type etch and a chemical-type etch of a silicon nitride material.
[0028] In accordance with the present invention, a sidewall of the reaction chamber is cleaned prior to an etching of a material within the chamber to reduce or eliminate inadvertent release of components from the sidewalls during the etching of the material. In a preferred embodiment of the invention, a sidewall of a reaction chamber is cleaned after a physical-type etch of a material within the chamber, and before a chemical-type etch of the material within the same chamber. [0028]
[0029] A sidewall of a reaction chamber can be cleaned by a number of methods. For instance, the sidewall can be subjected to a plasma containing one or more strong oxidants. Suitable plasmas can include, for example, SF[0029] ₆, Cl₂or NF₃in combination with oxygen atoms. More specifically, suitable plasmas can include, for example, SF₆/O₂, Cl₂/O₂, or NF₃/O₃. Suitable etch conditions can comprise, for example, 500 watts of power to a primary RF coil (such as RF coil 16 of the prior art reactor construction of FIG. 1) and from about 20 to about 60 mTorr of pressure within a reaction chamber. Preferably, a substrate will remain in the reaction chamber during cleaning of the sidewalls, but no bias power will be applied to the substrate. As no bias power is applied to the substrate, the oxidizing plasma within the chamber is substantially kept from etching materials on the substrate. In other words, the oxidizing plasma substantially selectively removes materials from sidewalls of the reaction chamber and not from the substrate. In the context of this document, the term “substantially selectively” means that the oxidizing plasma removes materials from the sidewalls of the reaction chamber at a rate that is at least 2 times greater than a rate at which materials are removed from the substrate, and preferably at least 10 times greater. As the debris film on a chamber wall is typically very thin (frequently less than 20 Angstroms), the oxidizing plasma treatment of the chamber sidewalls is for a brief enough time period that typically less than 5 Angstroms of material is removed from a wafer in the chamber during the oxidizing plasma treatment.
[0030] It is found that cleaning of the sidewalls of a reaction chamber between a physical-type etch and a chemical-type etch can alleviate the monitoring problems discussed above in the “background” section of this disclosure. A graph of nitrogen-component concentration versus time for a silicon nitride etch process conducted in accordance with the present invention is shown in FIG. 6. More specifically, FIG. 6 is a graph of signal intensity at 386 nanometers for a silicon nitride spacer etch, such as the etch described above with reference to FIGS. 4 and 5. Accordingly, the graph of FIG. 6 corresponds to similar processing as that described with reference to the prior art graph of FIG. 3, with a difference that the processing of FIG. 6 incorporates a sidewall cleaning step between a physical-type etch and a chemical-type etch. [0030]
[0031] The FIG. 6 the graph comprises three distinct peak regions, [0031] 90, 92 and 94. Peak region 90 corresponds to nitrogen-comprising components released during a physical-type etch of silicon nitride, and peak region 92 corresponds to nitrogen-components released during a chemical-type etch of the silicon nitride. Accordingly, peak regions 90 and 92 correspond to similar etches as peak regions 70 and 72 of the prior art graph shown in FIG. 3.
[0032] A difference between the graph of FIG. 6 and that of FIG. 3 is that peak region [0032] 92 of the chemical-type etch after a cleaning step of the present invention has a much flatter upper surface than does peak region 72 of the prior art chemical-type etch. Accordingly, peak region 92 provides a relatively flat baseline against which a decrease in nitrogen component concentration of etchant debris can be ascertained. For instance, peak region 92 contains an easily identified location 96 wherein a nitrogen-component concentration in an etch debris is decreasing. A comparison of peak regions 92 and 72 indicates that a decrease in nitrogen component concentration of etchant debris is significantly easier to detect with peak region 92 than with prior art peak region 72. Such easier detection can aid automated detection mechanisms. For instance, location 96 can be readily recognized even by conventional software algorithms as a distinct drop in intensity relative to the flat baseline at the top of peak region 92. Even in processes wherein automated detection mechanisms are not utilized, peak region 92 can have significant advantages relative to peak region 72. For instance, in manual operations (wherein a human operator is detecting a decrease in an etch debris component concentration) the operator can more readily detect the concentration change relative to peak region 92 than relative to prior art peak region 72.
[0033] The third peak region of the graph of FIG. 6 (peak region [0033] 94) corresponds to nitrogen-components released from the sidewalls of a reaction chamber during a cleaning step of the present invention. In the shown preferred embodiment, such cleaning step has occurred between a physical-type etch (indicated by peak region 90) and a chemical-type etch (indicated by peak region 92).
[0034] A comparison of the graph of a process of the present invention in FIG. 6 with the graph of a prior art process in FIG. 3 indicates that the present invention release of nitrogen-components by sidewall cleaning, and removal of such components from reaction chamber prior to the chemical-type etch, can alleviate complications that were occurring in prior art etch monitoring processes. [0034]
[0035] Although the process described above is described primarily with reference to a method of etching silicon nitride, it is to be understood that the invention has application to many other etch processes. For instance, the invention can be utilized during etching of silicon oxides or other materials. In such etching, a monitored component can be either oxygen or silicon. Additionally, the invention can be utilized during etching of materials that can consist essentially of silicon, such as, for example, polycrystalline silicon, amorphous silicon or monocrystalline silicon. The silicon can be removed from reaction chamber sidewalls by the strongly oxidizing plasmas described above. [0035]
[0036] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0036]

权利要求:
Claims (38)
[1" id="US-20010009245-A1-CLM-00001] 1. An etching method, comprising:
providing a substrate in a reaction chamber;
while the substrate is within the reaction chamber, providing a plasma within the reaction chamber, the plasma substantially selectively etching material from the sidewall relative to the substrate; and
applying no bias power to the substrate during the etching.
[2" id="US-20010009245-A1-CLM-00002] 2. An etching method, comprising:
providing a substrate in a reaction chamber;
providing first etching conditions within the reaction chamber to remove a first portion of the substrate;
providing second etching conditions within the reaction chamber remove a second portion of the substrate; and
cleaning a component from at least one sidewall of the reaction chamber between the first etching and the second etching.
[3" id="US-20010009245-A1-CLM-00003] 3. The method of
claim 2 wherein the substrate remains in the reaction chamber during the cleaning.
[4" id="US-20010009245-A1-CLM-00004] 4. The method of
claim 2 wherein the first portion and the second portion comprise a common material.
[5" id="US-20010009245-A1-CLM-00005] 5. A method of removing at least a portion of a material from a substrate, comprising:
providing a substrate in a reaction chamber, the substrate having a material thereover;
first etching the material while the substrate is in the reaction chamber;
second etching the material while the substrate is in the reaction chamber; and
cleaning a component from at least one sidewall of the reaction chamber between the first etching and the second etching, the component comprising a species that is present in the material.
[6" id="US-20010009245-A1-CLM-00006] 6. The method of
claim 5 wherein the material comprises silicon nitride and the species comprised by the component is nitrogen.
[7" id="US-20010009245-A1-CLM-00007] 7. The method of
claim 5 wherein the material comprises silicon oxide and the species comprised by the component is silicon.
[8" id="US-20010009245-A1-CLM-00008] 8. The method of
claim 5 wherein the material consists essentially of silicon and the species comprised by the component is silicon.
[9" id="US-20010009245-A1-CLM-00009] 9. The method of
claim 5 wherein the substrate remains in the reaction chamber during the cleaning.
[10" id="US-20010009245-A1-CLM-00010] 10. The method of
claim 5 wherein the first etching comprises a different pressure than the second etching.
[11" id="US-20010009245-A1-CLM-00011] 11. The method of
claim 5 wherein the substrate is provided with a different bias power during the first etching than during the second etching.
[12" id="US-20010009245-A1-CLM-00012] 12. The method of
claim 5 wherein the first etching utilizes a first plasma and the second etching utilizes a second plasma, the first and second plasmas having different chemical compositions from one another.
[13" id="US-20010009245-A1-CLM-00013] 13. The method of
claim 5 wherein the first and second etchings pattern the material on the substrate.
[14" id="US-20010009245-A1-CLM-00014] 14. The method of
claim 5 wherein the cleaning comprises exposing the sidewall to a plasma comprising SF₆and oxygen atoms.
[15" id="US-20010009245-A1-CLM-00015] 15. The method of
claim 5 wherein the cleaning comprises:
exposing the sidewall to a plasma comprising SF₆and oxygen atoms;
maintaining a pressure within the reaction chamber at from about 20 mtorr to about 60 mTorr; and
maintaining the substrate at a bias power of 0.
[16" id="US-20010009245-A1-CLM-00016] 16. The method of
claim 5 wherein the cleaning comprises exposing the sidewall to a plasma comprising chlorine atoms and oxygen atoms.
[17" id="US-20010009245-A1-CLM-00017] 17. The method of
claim 5 wherein the cleaning comprises:
exposing the sidewall to a plasma comprising chlorine atoms and oxygen atoms;
maintaining a pressure within the reaction chamber at from about 20 mTorr to about 60 mTorr; and
maintaining the substrate at a bias power of 0.
[18" id="US-20010009245-A1-CLM-00018] 18. The method of
claim 5 wherein the cleaning comprises exposing the sidewall to a plasma comprising NF₃and oxygen atoms.
[19" id="US-20010009245-A1-CLM-00019] 19. The method of
claim 5 wherein the cleaning comprises:
exposing the sidewall to a plasma comprising NF₃and oxygen atoms;
maintaining a pressure within the reaction chamber at from about 20 mTorr to about 60 mTorr; and
maintaining the substrate at a bias power of 0.
[20" id="US-20010009245-A1-CLM-00020] 20. A method of patterning a material over a semiconductive substrate, comprising:
forming a layer of first material against a second material and over a semiconductive substrate, the semiconductive substrate comprising a surface having a center and an edge;
first etching the first material in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the first material relative to the second material;
second etching the first material in the reaction chamber, the second etching comprising a second center-to-edge uniformity across the surface of the wafer and comprising a second selectivity for the first material relative to the second material, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity; and
cleaning a component of the first material from at least one sidewall of the reaction chamber between the first etching and the second etching.
[21" id="US-20010009245-A1-CLM-00021] 21. The method of
claim 20 wherein the semiconductive substrate comprises monocrystalline silicon and the second material is monocrystalline silicon of the semiconductive substrate.
[22" id="US-20010009245-A1-CLM-00022] 22. The method of
claim 20 wherein the semiconductive substrate comprises monocrystalline silicon and the second material is not monocrystalline silicon.
[23" id="US-20010009245-A1-CLM-00023] 23. The method of
claim 20 wherein the second etching creates a debris, the method further comprising monitoring the debris for the component to determine when the second etching has penetrated the first material.
[24" id="US-20010009245-A1-CLM-00024] 24. The method of
claim 23 wherein the monitoring and determining are accomplished entirely by an automated mechanism, the automated mechanism comprising software configured to recognize a drop in a component concentration in the debris.
[25" id="US-20010009245-A1-CLM-00025] 25. The method of
claim 20 wherein the first material is over the second material, wherein the second material does not comprise the component, and wherein the second etching creates a debris, the method further comprising monitoring the debris for the component to determine when the second etching has penetrated the first material to reach the second material.
[26" id="US-20010009245-A1-CLM-00026] 26. A method of forming silicon nitride spacers, comprising:
forming a transistor gate assembly over a semiconductive substrate, the semiconductive substrate comprising a surface having a center and an edge;
forming a silicon dioxide layer proximate the transistor gate assembly;
forming a silicon nitride layer over the transistor gate assembly and over the silicon dioxide layer;
first etching the silicon nitride in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the silicon nitride relative to the silicon oxide;
second etching the silicon nitride in the reaction chamber, the second etching comprising a second center-to-edge uniformity across the surface of the wafer and comprising a second selectivity for the silicon nitride relative to the silicon oxide, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity, the first and second etchings patterning the silicon nitride into spacers proximate the transistor gate; and
cleaning a component of the silicon nitride from at least one sidewall of the reaction chamber between the first etching and the second etching.
[27" id="US-20010009245-A1-CLM-00027] 27. The method of
claim 26 wherein the component comprises nitrogen.
[28" id="US-20010009245-A1-CLM-00028] 28. The method of
claim 26 wherein the substrate remains in the reaction chamber during the cleaning.
[29" id="US-20010009245-A1-CLM-00029] 29. The method of
claim 26 wherein the first etching comprises a different pressure than the second etching.
[30" id="US-20010009245-A1-CLM-00030] 30. The method of
claim 26 wherein the substrate is provided with a different bias power during the first etching than during the second etching.
[31" id="US-20010009245-A1-CLM-00031] 31. The method of
claim 26 wherein the cleaning comprises exposing the sidewall to a plasma comprising SF₆and oxygen atoms.
[32" id="US-20010009245-A1-CLM-00032] 32. The method of
claim 26 wherein the cleaning comprises:
exposing the sidewall to a plasma comprising SF₆and oxygen atoms;
maintaining a pressure within the reaction chamber at from about 20 mTorr to about 60 mTorr; and
maintaining the substrate at a bias power of 0.
[33" id="US-20010009245-A1-CLM-00033] 33. The method of
claim 26 wherein the cleaning comprises exposing the sidewall to a plasma comprising chlorine atoms and oxygen atoms.
[34" id="US-20010009245-A1-CLM-00034] 34. The method of
claim 26 wherein the cleaning comprises:
exposing the sidewall to a plasma comprising chlorine atoms and oxygen atoms;
maintaining a pressure within the reaction chamber at from about 20 mTorr to about 60 mTorr; and
maintaining the substrate at a bias power of 0.
[35" id="US-20010009245-A1-CLM-00035] 35. The method of
claim 26 wherein the cleaning comprises exposing the sidewall to a plasma comprising NF₃and oxygen atoms.
[36" id="US-20010009245-A1-CLM-00036] 36. The method of
claim 26 wherein the cleaning comprises:
exposing the sidewall to a plasma comprising NF₃and oxygen atoms;
maintaining a pressure within the reaction chamber at from about 20 mTorr to about 60 mTorr; and
maintaining the substrate at a bias power of 0.
[37" id="US-20010009245-A1-CLM-00037] 37. The method of
claim 26 wherein the second etching creates a debris, the method further comprising monitoring the debris for the component to determine when the second etching has penetrated the silicon nitride.
[38" id="US-20010009245-A1-CLM-00038] 38. The method of
claim 37 wherein the monitoring and determining are accomplished entirely by an automated mechanism, the automated mechanism comprising software configured to recognize a drop in a component concentration in the debris.

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同族专利:

公开号 | 公开日

US6533953B2|2003-03-18|

US20030052089A1|2003-03-20|

US6479393B1|2002-11-12|

US6967170B2|2005-11-22|

US6235213B1|2001-05-22|

US20030047537A1|2003-03-13|

US6478978B1|2002-11-12|

US6878300B2|2005-04-12|

US6800561B2|2004-10-05|

US20030036286A1|2003-02-20|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

WO2003038889A2|2001-10-31|2003-05-08|Lam Research Corporation|Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring|

US6756313B2|2002-05-02|2004-06-29|Jinhan Choi|Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber|

US20070010096A1|2005-07-08|2007-01-11|Kyoung-Choul Shin|Method for fabricating semiconductor device|

CN108346572A|2018-02-09|2018-07-31|信利（惠州）智能显示有限公司|The surface treatment method of silicon oxide film and silicon nitride film|

US10446447B2|2017-03-23|2019-10-15|United Microelectronics Corp.|Method for fabricating a curve on sidewalls of a fin-shaped structure|US3767021A|1969-08-20|1973-10-23|Olivetti & Co Spa|Cam actuated shift device with continuously operated intermediate lever for type-bar typewriter|

US4397724A|1981-08-24|1983-08-09|Bell Telephone Laboratories, Incorporated|Apparatus and method for plasma-assisted etching of wafers|

US4513021A|1982-02-01|1985-04-23|Texas Instruments Incorporated|Plasma reactor with reduced chamber wall deposition|

US4436584A|1983-03-21|1984-03-13|Sperry Corporation|Anisotropic plasma etching of semiconductors|

US4528066A|1984-07-06|1985-07-09|Ibm Corporation|Selective anisotropic reactive ion etching process for polysilicide composite structures|

US5026666A|1989-12-28|1991-06-25|At&T Bell Laboratories|Method of making integrated circuits having a planarized dielectric|

US5155336A|1990-01-19|1992-10-13|Applied Materials, Inc.|Rapid thermal heating apparatus and method|

US5302240A|1991-01-22|1994-04-12|Kabushiki Kaisha Toshiba|Method of manufacturing semiconductor device|

FR2674524B1|1991-03-25|1993-05-21|Adir|NOVEL HETEROCYCLIC ALKYL AMIDES, THEIR PREPARATION PROCESS AND THE PHARMACEUTICAL COMPOSITIONS CONTAINING THEM.|

US5242538A|1992-01-29|1993-09-07|Applied Materials, Inc.|Reactive ion etch process including hydrogen radicals|

JP3215151B2|1992-03-04|2001-10-02|株式会社東芝|Dry etching method|

GB9205320D0|1992-03-11|1992-04-22|Ici Plc|Anti-tumour compounds|

US5445712A|1992-03-25|1995-08-29|Sony Corporation|Dry etching method|

US5716494A|1992-06-22|1998-02-10|Matsushita Electric Industrial Co., Ltd.|Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate|

DE69320963T2|1992-06-22|1999-05-12|Lam Res Corp|PLASMA CLEANING METHOD FOR REMOVING RESIDUES IN A PLASMA TREATMENT CHAMBER|

KR100276093B1|1992-10-19|2000-12-15|히가시 데쓰로|Plasma etching system|

US5565056A|1993-04-23|1996-10-15|Aluminum Company Of America|Plural extruder method for making a composite building panel|

EP0709877A4|1993-05-20|1997-11-26|Hitachi Ltd|Plasma processing method|

JP2674488B2|1993-12-01|1997-11-12|日本電気株式会社|Dry etching chamber cleaning method|

US5505816A|1993-12-16|1996-04-09|International Business Machines Corporation|Etching of silicon dioxide selectively to silicon nitride and polysilicon|

US5565036A|1994-01-19|1996-10-15|Tel America, Inc.|Apparatus and method for igniting plasma in a process module|

US5431778A|1994-02-03|1995-07-11|Motorola, Inc.|Dry etch method using non-halocarbon source gases|

AT251798T|1994-04-28|2003-10-15|Applied Materials Inc|METHOD FOR OPERATING A HIGH PLASMA DENSITY CVD REACTOR WITH COMBINED INDUCTIVE AND CAPACITIVE COUPLING|

JP3597885B2|1994-06-06|2004-12-08|テキサスインスツルメンツインコーポレイテツド|Semiconductor device|

KR0137841B1|1994-06-07|1998-04-27|문정환|Method for removing a etching waste material|

US5514247A|1994-07-08|1996-05-07|Applied Materials, Inc.|Process for plasma etching of vias|

US5950092A|1995-06-02|1999-09-07|Micron Technology, Inc.|Use of a plasma source to form a layer during the formation of a semiconductor device|

US5679211A|1995-09-18|1997-10-21|Taiwan Semiconductor Manufacturing Company, Ltd.|Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue|

US5830279A|1995-09-29|1998-11-03|Harris Corporation|Device and method for improving corrosion resistance and etch tool integrity in dry metal etching|

US5644153A|1995-10-31|1997-07-01|Micron Technology, Inc.|Method for etching nitride features in integrated circuit construction|

US5788869A|1995-11-02|1998-08-04|Digital Equipment Corporation|Methodology for in situ etch stop detection and control of plasma etching process and device design to minimize process chamber contamination|

EP0777258A3|1995-11-29|1997-09-17|Applied Materials Inc|Self-cleaning plasma processing reactor|

US5756400A|1995-12-08|1998-05-26|Applied Materials, Inc.|Method and apparatus for cleaning by-products from plasma chamber surfaces|

US5647953A|1995-12-22|1997-07-15|Lam Research Corporation|Plasma cleaning method for removing residues in a plasma process chamber|

US5679215A|1996-01-02|1997-10-21|Lam Research Corporation|Method of in situ cleaning a vacuum plasma processing chamber|

US6200412B1|1996-02-16|2001-03-13|Novellus Systems, Inc.|Chemical vapor deposition system including dedicated cleaning gas injection|

TW473857B|1996-04-26|2002-01-21|Hitachi Ltd|Method of manufacturing semiconductor device|

US5814563A|1996-04-29|1998-09-29|Applied Materials, Inc.|Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas|

US5843847A|1996-04-29|1998-12-01|Applied Materials, Inc.|Method for etching dielectric layers with high selectivity and low microloading|

US5626775A|1996-05-13|1997-05-06|Air Products And Chemicals, Inc.|Plasma etch with trifluoroacetic acid and derivatives|

US5865938A|1996-06-25|1999-02-02|Xerox Corporation|Wafer chuck for inducing an electrical bias across wafer heterojunctions|

US5843226A|1996-07-16|1998-12-01|Applied Materials, Inc.|Etch process for single crystal silicon|

US5798303A|1996-09-05|1998-08-25|Micron Technology, Inc.|Etching method for use in fabrication of semiconductor devices|

US5935340A|1996-11-13|1999-08-10|Applied Materials, Inc.|Method and apparatus for gettering fluorine from chamber material surfaces|

US5933759A|1996-12-31|1999-08-03|Intel Corporation|Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications|

US5843239A|1997-03-03|1998-12-01|Applied Materials, Inc.|Two-step process for cleaning a substrate processing chamber|

US5780338A|1997-04-11|1998-07-14|Vanguard International Semiconductor Corporation|Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits|

US6103070A|1997-05-14|2000-08-15|Applied Materials, Inc.|Powered shield source for high density plasma|

US6127278A|1997-06-02|2000-10-03|Applied Materials, Inc.|Etch process for forming high aspect ratio trenched in silicon|

US5868853A|1997-06-18|1999-02-09|Taiwan Semiconductor Manufacturing Co. Ltd.|Integrated film etching/chamber cleaning process|

US5965463A|1997-07-03|1999-10-12|Applied Materials, Inc.|Silane etching process|

US5872061A|1997-10-27|1999-02-16|Taiwan Semiconductor Manufacturing Company, Ltd.|Plasma etch method for forming residue free fluorine containing plasma etched layers|

TW351837B|1997-10-29|1999-02-01|United Semiconductor Corp|Method for improving etching process|

US6136211A|1997-11-12|2000-10-24|Applied Materials, Inc.|Self-cleaning etch process|

US6093655A|1998-02-12|2000-07-25|Micron Technology, Inc.|Plasma etching methods|

US6235213B1|1998-05-18|2001-05-22|Micron Technology, Inc.|Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers|

US6010967A|1998-05-22|2000-01-04|Micron Technology, Inc.|Plasma etching methods|

US6277759B1|1998-08-27|2001-08-21|Micron Technology, Inc.|Plasma etching methods|US6093655A|1998-02-12|2000-07-25|Micron Technology, Inc.|Plasma etching methods|

US6235213B1|1998-05-18|2001-05-22|Micron Technology, Inc.|Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers|

US6277759B1|1998-08-27|2001-08-21|Micron Technology, Inc.|Plasma etching methods|

US6599842B2|1999-11-29|2003-07-29|Applied Materials, Inc.|Method for rounding corners and removing damaged outer surfaces of a trench|

US6762129B2|2000-04-19|2004-07-13|Matsushita Electric Industrial Co., Ltd.|Dry etching method, fabrication method for semiconductor device, and dry etching apparatus|

US6566270B1|2000-09-15|2003-05-20|Applied Materials Inc.|Integration of silicon etch and chamber cleaning processes|

WO2002075801A2|2000-11-07|2002-09-26|Tokyo Electron Limited|Method of fabricating oxides with low defect densities|

JP2002299316A|2001-03-29|2002-10-11|Toshiba Corp|Plasma processing method|

TW529099B|2002-01-21|2003-04-21|Macronix Int Co Ltd|Method for performing via etching in the same etching chamber|

EP1509929A4|2002-05-23|2007-03-21|Columbian Chem|Conducting polymer-grafted carbon material for fuel cell applications|

KR100457844B1|2002-08-27|2004-11-18|삼성전자주식회사|Method Of Etching Semiconductor Device|

JP4749683B2|2004-06-08|2011-08-17|東京エレクトロン株式会社|Etching method|

US20050269294A1|2004-06-08|2005-12-08|Tokyo Electron Limited|Etching method|

US7629026B2|2004-09-03|2009-12-08|Eastman Kodak Company|Thermally controlled fluidic self-assembly|

US20070243714A1|2006-04-18|2007-10-18|Applied Materials, Inc.|Method of controlling silicon-containing polymer build up during etching by using a periodic cleaning step|

US7488685B2|2006-04-25|2009-02-10|Micron Technology, Inc.|Process for improving critical dimension uniformity of integrated circuit arrays|

US20080124937A1|2006-08-16|2008-05-29|Songlin Xu|Selective etching method and apparatus|

US20080102642A1|2006-10-31|2008-05-01|United Microelectronics Corp.|Method of seasoning idle silicon nitride etcher and method of activating|

JP2009188257A|2008-02-07|2009-08-20|Tokyo Electron Ltd|Plasma etching method, plasma etching apparatus, and storage medium|

CN103996621B|2014-04-25|2017-08-29|京东方科技集团股份有限公司|Dry etching method|

US10094586B2|2015-04-20|2018-10-09|Green Power Labs Inc.|Predictive building control system and method for optimizing energy use and thermal comfort for a building or network of buildings|

US10381235B2|2016-05-29|2019-08-13|Tokyo Electron Limited|Method of selective silicon nitride etching|

JP2019004029A|2017-06-14|2019-01-10|キヤノン株式会社|Semiconductor device manufacturing method|

法律状态:
2003-08-26| CC| Certificate of correction|

2006-08-28| FPAY| Fee payment|Year of fee payment: 4 |

2010-08-18| FPAY| Fee payment|Year of fee payment: 8 |

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2015-03-18| LAPS| Lapse for failure to pay maintenance fees|

2015-04-13| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |

2015-05-05| FP| Lapsed due to failure to pay maintenance fee|Effective date: 20150318 |

优先权:

申请号 | 申请日 | 专利标题

US09/080,656|US6235213B1|1998-05-18|1998-05-18|Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers|

US09/797,355|US6533953B2|1998-05-18|2001-02-28|Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers|US09/797,355| US6533953B2|1998-05-18|2001-02-28|Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers|

US10/262,727| US6878300B2|1998-05-18|2002-10-01|Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers|

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