• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.
    公开号:US20010008808A1
    申请号:US09/779,924
    申请日:2001-02-08
    公开日:2001-07-19
    发明作者:Fernando Gonzalez
    申请人:Fernando Gonzalez；
    IPC主号:H01L27-10844
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The present invention relates to semiconductor fabrication techniques, and more particularly to techniques for fabricating dynamic random access memories (DRAM). [0002]
    [0003] 2. Description of the Background [0003]
    [0004] A DRAM array is comprised of individual memory cells arranged in columns and rows on a lightly-doped silicon substrate. Each cell has a field-effect access transistor and a storage capacitor. The capacitor, which is directly connected to the transistor's source or storage node, may be charged and discharged through the transistor's channel. Transistor gates and gate interconnects within an array row are formed from a ribbon of conductive material which runs the length of the row. That conductive ribbon is known as a rowline. Between consecutive transistor gate within a row, the rowline traverses a field oxide region. In active areas of the array (locations where the rowline functions as a gate), the rowline is insulated from the substrate by a layer of gate oxide. When voltage is applied to each rowline through a driver transistor, all the transistors in the row are turned on. The access node of each transistor is connected to a columnar bit line. To determine the capacitor charge value (which may be equated with either a “1” or a “0” binary value), a column sense amp at the end of the bit line compares the capacitor charge to a reference voltage. [0004]
    [0005] The speed of a dynamic random access memory is dependent on a number of factors. One of the primary factors is access speed, i.e., the speed at which a rowline can turn on the transistors of the cells along a row. Rowline access speed is inversely proportional to the rowline's resistance multiplied by its capacitance, i.e., an RC time constant. In other words, an increase in either the resistance of the capacitance of the rowline will degrade access speed. The reduction of rowline resistance is easily achieved. In fact, current DRAM designs typically utilize rowlines constructed from conductively-doped polycrystalline silicon (hereinafter “Polysilicon”) that has been silicided with a refractory metal such as titanium, platinum, palladium, cobalt, or tungsten. The resistance of a silicided, conductively-doped polysilicon is generally within the range of 5-25 ohms per square, whereas the resistance of titanium silicided conductively-doped polysilicon, for example, is approximately 2 ohms per square. [0005]
    [0006] The reduction of rowline capacitance, however, is more problematic. Rowline capacitance is roughly equal to the summation of the polysilicon gate-to-substrate capacitances, because the field oxide regions are relatively thick and capacitances of the word line over those regions is relatively minimal. Using most current production techniques, all transistors within a DRAM array (whether they be cell access transistors or transistors within the periphery) utilize a single thickness of gate oxide. To reduce rowline capacitance using such fabrication techniques, it would be necessary to increase the gate oxide layer thickness. Because capacitance is inversely proportional to dielectric layer thickness, a doubling of dielectric layer thickness should approximately halve rowline capacitance. However, the drive current at maximum voltage for the peripheral, rowline driver transistors is decreased by the increase in dielectric layer thickness. Because of reduction in drive current will result in a reduction in rowline access speed, the gain in speed achieved through the reduction in rowline capacitance will be offset by the reduction in speed caused by decreased drive current. [0006]
    [0007] A solution to the aforementioned problem is set forth in U.S. Pat. No. 5,057,499 entitled Process For Creating Two Thicknesses of Gate Oxide Within A Dynamic Random Access Memory. The invention disclosed therein achieves a net increase in rowline access speed by providing a process for creating DRAM memories having dual layers of gate oxide of different thicknesses. Peripheral driver transistors are constructed on top of a thin layer of gate oxide to optimize their performance whereas cell access transistors are constructed on top of a thicker layer of gate oxide to minimize rowline capacitance. [0007]
    [0008] The process of U.S. Pat. No. 5,057,499 begins by thermally growing a first layer of gate oxide on a silicon substrate. The first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. During the growth of the second gate oxide layer, the thickness of the remaining fist oxide layer portions increases, but at a rate considerably slower than that at which new oxide initially forms on bare substrate regions. The resultant gate oxide layer, which then comprises regions of two different thicknesses, is used as a pad oxide layer during a conventional local oxidation of silicon (LOCOS) operation; nitride is deposited on the resultant gate oxide layer, masked, and etched to create regions devoid of nitride where field oxide regions will be grown. The field oxide regions are then thermally grown, and DRAM fabrication proceeds in a conventional manner. [0008]
    [0009] While the invention of U.S. Pat. No. 5,057,449 provides a fabrication technique which enables gate oxide layers of different thicknesses to be fabricated, the need still exists to create fabrication techniques that enable gate oxide layers of different thicknesses to be fabricated using fewer process steps and or fewer masks. [0009] SUMMARY OF THE INVENTION
    [0010] The present invention is directed to a fabrication technique in which dual gate oxide thicknesses are provided but with less steps and one less mask than is currently required. Beginning with a substrate on which a local oxidation of silicon process has been performed, i.e., a substrate as shown in FIG. 3, the process comprises the steps of stripping a pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques. [0010]
    [0011] Starting with a bare substrate, the process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques. [0011]
    [0012] According to one embodiment of the present invention, the step of striping the pad oxide and growing a sacrificial oxide layer can be eliminated if the pad oxide layer has the desired characteristics. [0012]
    [0013] One advantage of the present invention is that the mask used as an implant mask to protect the area which will form the memory array is also used as an etch mask for etching the sacrificial oxide. That eliminates the need to create a separate etch mask and saves time by eliminating the steps associated with applying a separate etch mask. The diode characteristics are improved by the process of the present invention because the array area is protected during the implantation step for the peripheral devices. Static refresh times are improved. The process of the present invention also enables the thickness of the gate oxide to be tailored for the desired function thereby improving such characteristics as the subthreshold voltage and gate induced drain leakage. Those and other advantages and benefits will become apparent from the Description Of A Preferred Embodiment hereinbelow. [0013] BRIEF DESCRIPTION OF THE DRAWINGS
    [0014] For the present invention to be clearly understood and readily practiced, the present invention will be described in conjunction with the following figures wherein: [0014]
    [0015] FIG. 1 illustrates a substrate with a first gate oxide layer grown on a surface thereof and a layer of silicon nitride deposited on top of the gate oxide layer; [0015]
    [0016] FIG. 2 illustrates the substrate of FIG. 1 after the silicon nitride layer has been patterned with a photoresist mask to define oxide regions which will become future active areas; [0016]
    [0017] FIG. 3 illustrates the substrate of FIG. 2 after an oxide layer has been thermally grown on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer and after the remnants of the silicon nitride layer have been removed; [0017]
    [0018] FIG. 4 illustrates the substrate of FIG. 3 after the pad oxide has been stripped to expose the substrate in the regions which will become future active areas; [0018]
    [0019] FIG. 5 illustrates the substrate of FIG. 4 after a thick sacrificial oxide layer has been grown; [0019]
    [0020] FIG. 6 illustrates the substrate of FIG. 5 after a photoresist has been patterned to define local integrated field implant areas; [0020]
    [0021] FIG. 7 illustrates the substrate of FIG. 6 masked to protect the array; [0021]
    [0022] FIG. 8 illustrates the substrate of FIG. 7 after the exposed thick oxide has been stripped, the photoresist removed, and a thin gate oxide layer grown; [0022]
    [0023] FIG. 9 illustrates the substrate of FIG. 8 after the gate oxide layers has been masked and etched to form gate regions; [0023]
    [0024] FIGS. 10 and 11 illustrate the substrate at two different stages of completion; and [0024]
    [0025] FIG. 12 illustrates a completed device. [0025] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0026] The present invention is directed to a process for creating two thicknesses of gate oxide within a dynamic random access memory. A thick gate oxide is provided within the array to minimize the rowline capacitance. A thin layer of gate oxide is provided for the peripheral devices to provide for increased speed. The process begins, as shown in FIG. 1, with a first silicon dioxide layer [0026] 12 being thermally grown on the upper surface of a silicon substrate 10 to a thickness of approximately 200-250 angstroms. A layer of silicon nitride 14 is deposited on top of the silicon dioxide layer 12.
    [0027] The silicon nitride [0027] 14 is covered with a photoresist, which is patterned according to an appropriate mask. Thereafter, those portions of the silicon nitride 14 defined by the mask are removed so that the silicon nitride layer 14 is patterned as shown FIG. 2. Those portions of the oxide layer 12 not masked by the silicon nitride 14 are stripped so that portions of the silicon substrate 10 are exposed. Thereafter, a silicon dioxide layer 16 (FIG. 3) is grown on the exposed surfaces of the substrate 10. The remaining portions of silicon nitride 14 are selectively stripped so as not to etch the oxide layer 16 thereby leaving the oxide layer 16 with the configuration illustrated in FIG. 3. The oxide layer 16 is made up of pad oxide regions 18 which cover gate regions 19. The pad oxide regions 18, which were masked by portions of the silicon nitride 14, are approximately 200-250 angstroms thick. The pad oxide regions 18 are part of the original oxide layer 12. The pad oxide regions 18 are connected by field oxide regions 20 which may have a thickness of 4,000-6,000 angstroms. The process steps which produce the oxide layer 16 having the configuration as shown in FIG. 3 is sometimes referred to as a local oxidation of silicon (LOCOS) operation.
    [0028] In FIG. 4, the oxide layer [0028] 16 is subjected to a stripping operation which completely removes the pad oxide regions 18 and reduces the field oxide in regions 20 by approximately the same small amount. The substrate 10 is subjected to conditions which allow an oxide layer to be regrown as shown in FIG. 5 by the reference number 22. The regrown oxide layer 22 is approximately 350 angstroms thick in gate regions 19. The oxide layer 22 is sometimes referred to as the sacrificial oxide layer. It should be noted, as an alternative to the strip and regrow shown in FIG. 4, if the pad oxide 18 is in sufficiently good condition, and sufficiently close to the final dimension of the thick gate, the process could continue directly from FIG. 3 to the steps illustrated in FIG. 5 skipping the strip and regrow step of FIG. 4.
    [0029] In FIG. 6, the sacrificial oxide layer [0029] 22 is covered with photoresist which is patterned according to a field implant mask. The purpose of the field implant mask is to protect the storage node areas 23 from the dopant. Another purpose of the mask is to protect the area 25 where the peripheral devices will be fabricated. In the case of a CMOS process, the periphery p-channel devices would also be protected. The field implant is a high energy (approximately 150 to 200 KeV) implant with a dose of 1 to 5×1012 atoms/cm2 of boron. The high energy implant is for isolation purposes. The high energy implant is followed by a low energy (approximately 25 KeV) implant with a dose of 1 to 2×1012 atoms/cm2 of boron or boron fluoride (BF2). The low energy implant increases the threshold voltage of the future array devices. The implants take place in the area 24. The implant areas in the substrate resulting from the implants are shown only in FIG. 12 for purposes of clarity. After the implant steps, the photoresist illustrated in FIG. 6 is stripped.
    [0030] In FIG. 7, a new layer of photoresist [0030] 26 is provided on top of sacrificial oxide layer 22 and patterned according to a mask. The mask is a noncritical mask with respect to alignment. The purpose of the mask is to protect the thick gate oxide in the implant area 24 while at the same time exposing implant area 28. After implantation, the sacrificial oxide 22 exposed by the photoresist layer 26 is etched such that the sacrificial oxide in implant area 28 is completely removed exposing the underlying silicon substrate 10. Thereafter, the photoresist layer 26 is stripped and a thin oxide layer is grown. Growing the thin oxide layer results, as shown in FIG. 8, in a thin gate oxide layer in implant area 28 of approximately 100 angstroms. As a result of growing the 100 angstroms thick oxide layer, the gate oxide in implant area 24 also grows. If the 250 angstrom pad oxide was used, after the strip and regrow step occurring between FIGS. 7 and 8, the oxide in implant area 24 may be approximately 325 angstroms thick. Alternative, if the pad oxide was stripped and regrown, then the 350 angstrom oxide layer in implant area 24 may increase in thickness to approximately 410 angstroms. The oxide layer 22 appearing in FIG. 8 thus has a thick gate oxide portion in implant area 24, a thin gate oxide portion in implant area 28, and thick field oxide portions 20 therebetween.
    [0031] It is seen that the photoresist layer [0031] 26 of FIG. 7 acts as both an implant mask and an etch mask. That saves a process step inasmuch as there is no need for a separate implant mask and a separate etch mask.
    [0032] Fabrication of the device may continue as shown in FIG. 9 using any known conventional techniques. For example, a layer of polysilicon [0032] 34 may be deposited and etched followed by an oxide layer 36 which is grown and etched. During that subsequent processing, the oxide layer 22 may be over-etched resulting in the gate regions 30 illustrated in FIG. 9. The thicker gate oxide allows for a greater amount of over etching while still maintaining a desirable defect density.
    [0033] A portion of the memory device is shown at two different stages of completion in FIGS. 10 and 11. A portion of the completed memory device [0033] 38 is illustrated in FIG. 12 in which metallic conductors 40 are in electrical contact with the active components comprising device 38.
    [0034] The process steps of the present invention result in a memory device in which static refresh is improved. Additionally, the subthreshold voltage of the access transistor is also improved. Finally, gate induced drain leakage (GIDL) is reduced thereby improving overall performance. [0034]
    [0035] As previously mentioned, the process disclosed herein utilizes a photoresist mask as both an implant mask and an etch mask thereby eliminating a number of steps and eliminating the need for a separate mask. That improves the efficiency of the process. Also, the process itself, as described above, results in a device which has improved characteristics. [0035]
    [0036] While the present invention has been described in connection with preferred embodiments thereof, those of ordinary skill in the art will recognize that many modifications and variations may be practiced which do not part from the spirit and scope of the present invention. All such modifications and variations are intended to be covered by the foregoing description and the following claims. [0036]
    权利要求:
    Claims (10)
    [1" id="US-20010008808-A1-CLM-00001] 1. A process for creating two thicknesses of gate oxide within a memory device constructed on a substrate on which a local oxidation of silicon process has been performed, comprising the steps of:
    stripping a pad oxide and growing a sacrificial oxide layer;
    masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed;
    stripping the sacrificial oxide not protected by the photoresist;
    stripping the photoresist; and
    growing a gate oxide layer which is thinner than the sacrificial oxide layer.
    [2" id="US-20010008808-A1-CLM-00002] 2. The process of
    claim 1 additionally comprising the step of masking and etching the sacrificial oxide layer and gate oxide layer to form gate regions of different thicknesses.
    [3" id="US-20010008808-A1-CLM-00003] 3. The process of
    claim 1 additionally comprising the steps of masking the sacrificial oxide layer with a photoresist to define local integrated field implant areas, performing a field implant in the area where the memory array will be formed, and stripping the photoresist before the step of masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed.
    [4" id="US-20010008808-A1-CLM-00004] 4. The process of
    claim 3 additionally comprising the step of performing an enhancement implant before the step of stripping the sacrificial oxide not protected by the photoresist.
    [5" id="US-20010008808-A1-CLM-00005] 5. A process for creating two thicknesses of gate oxide within a memory device constructed on a substrate on which a local oxidation of silicon process has been performed, comprising the steps of:
    masking a pad oxide with a photoresist to protect the area where the memory array will be formed;
    stripping the pad oxide not protected by the photoresist;
    stripping the photoresist; and
    growing a gate oxide layer which is thinner than the pad oxide layer.
    [6" id="US-20010008808-A1-CLM-00006] 6. The process of
    claim 6 additionally comprising the step of masking and etching the pad oxide and gate oxide layer to form gate regions of different thicknesses.
    [7" id="US-20010008808-A1-CLM-00007] 7. A process for creating two thicknesses of gate oxide within a memory device, comprising the steps of:
    growing a first oxide layer on the upper surface of a substrate;
    depositing a silicon nitride layer on top of the first oxide layer;
    patterning the silicon nitride layer with a photoresist mask to define field oxide areas;
    stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer;
    removing the remnants of the silicon nitride layer;
    stripping the pad oxide layer and growing a sacrificial oxide layer;
    masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed;
    stripping the sacrificial oxide not protected by the photoresist;
    stripping the photoresist; and
    growing a gate oxide layer which is thinner than the sacrificial oxide layer.
    [8" id="US-20010008808-A1-CLM-00008] 8. A process for creating two thicknesses of gate oxide within a memory device constructed on a substrate, comprising the steps of:
    growing a first oxide layer on the upper surface of a substrate;
    depositing a silicon nitride layer on top of the first oxide layer;
    patterning the silicon nitride layer with a photoresist mask to define field oxide areas;
    stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer;
    removing the remnants of the silicon nitride layer;
    masking the pad oxide layer with a photoresist to protect the area where the memory array will be formed;
    stripping the pad oxide not protected by the photoresist;
    stripping the photoresist; and
    growing a gate oxide layer which is thinner than the pad oxide layer.
    [9" id="US-20010008808-A1-CLM-00009] 9. The process of
    claim 8 additionally comprising the steps of masking the pad oxide layer with a photoresist to define local integrated field implant areas, performing a field implant in the area where the memory array will be formed, and stripping the photoresist before the step of masking the pad oxide layer with a photoresist to protect the area where the memory array will be formed.
    [10" id="US-20010008808-A1-CLM-00010] 10. The process of
    claim 9 additionally comprising the step of performing an enhancement implant before the step of stripping the pad oxide not protected by the photoresist.
    类似技术:
    公开号 | 公开日 | 专利标题
    US5863819A|1999-01-26|Method of fabricating a DRAM access transistor with dual gate oxide technique
    US5057449A|1991-10-15|Process for creating two thicknesses of gate oxide within a dynamic random access memory
    KR100338413B1|2002-05-27|Method for providing dual work function doping and protective insulating cap
    US5492851A|1996-02-20|Method for fabricating attached capacitor cells in a semiconductor device having a thin film transistor
    US6483152B1|2002-11-19|Semiconductor device
    US6025227A|2000-02-15|Capacitor over bit line structure using a straight bit line shape
    US5296399A|1994-03-22|Method for manufacturing a narrowed sidewall spacer in a peripheral circuit of a ULSI semiconductor memory device
    US4878100A|1989-10-31|Triple-implanted drain in transistor made by oxide sidewall-spacer method
    US6040221A|2000-03-21|Semiconductor processing methods of forming a buried contact, a conductive line, an electrical connection to a buried contact area, and a field effect transistor gate
    US5447881A|1995-09-05|Method for the fabrication of capacitor in semiconductor device
    US5516719A|1996-05-14|Method for the fabrication of a capacitor in a semiconductor device
    US5234853A|1993-08-10|Method of producing a high voltage MOS transistor
    EP0028654B1|1986-01-15|Semiconductive memory device and fabricating method therefor
    US5700708A|1997-12-23|Process for fabricating storage capacitor for DRAM memory cell
    US4388121A|1983-06-14|Reduced field implant for dynamic memory cell array
    JPH05102415A|1993-04-23|Manufacture of ultrahigh-density integrated semiconductor memory device
    JPH09181277A|1997-07-11|Manufacture of semiconductor memory device
    US6252268B1|2001-06-26|Method of forming transistors in a peripheral circuit of a semiconductor memory device
    JPH07161835A|1995-06-23|Manufacture of semiconductor memory device
    US5140392A|1992-08-18|High voltage mos transistor and production method thereof, and semiconductor device having high voltage mos transistor and production method thereof
    US6432787B1|2002-08-13|Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact
    US5332682A|1994-07-26|Local encroachment reduction
    US20030205745A1|2003-11-06|DRAM cell having independent and asymmetric source/drain and method of forming the same
    JPH07288313A|1995-10-31|Capacitor preparation of a semiconductor memory device
    US5689120A|1997-11-18|MOS field effect transistor in a dynamic random access memory device and method for fabricating the same
    同族专利:
    公开号 | 公开日
    US5863819A|1999-01-26|
    US6548340B2|2003-04-15|
    US6204106B1|2001-03-20|
    US6686246B2|2004-02-03|
    US20020119619A1|2002-08-29|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20040202786A1|2001-05-22|2004-10-14|Novellus Systems, Inc.|Method of forming low-resistivity tungsten interconnects|
    US20050031786A1|2001-05-22|2005-02-10|Novellus Systems, Inc.|Method for reducing tungsten film roughness and improving step coverage|
    US20050130441A1|2003-11-05|2005-06-16|Geon-Ook Park|Semiconductor devices and methods of manufacturing the same|
    US20060094238A1|2003-01-21|2006-05-04|Novellus Systems, Inc.|Deposition of tungsten nitride|
    US7157798B1|2003-05-09|2007-01-02|Novellus Systems, Inc.|Selective refractory metal and nitride capping|
    US20080045010A1|2003-08-26|2008-02-21|Novellus Systems, Inc.|Reducing silicon attack and improving resistivity of tungsten nitride film|
    US20080124926A1|2001-05-22|2008-05-29|Novellus Systems, Inc.|Methods for growing low-resistivity tungsten film|
    US20090114832A1|2007-08-30|2009-05-07|Kelvin Lynn|Semiconductive materials and associated uses thereof|
    US20090149022A1|2007-12-05|2009-06-11|Novellus Systems, Inc.|Method for improving uniformity and adhesion of low resistivity tungsten film|
    US20090163025A1|2007-12-21|2009-06-25|Novellus Systems, Inc.|Methods for forming all tungsten contacts and lines|
    US7655567B1|2007-07-24|2010-02-02|Novellus Systems, Inc.|Methods for improving uniformity and resistivity of thin tungsten films|
    US20100055904A1|2008-08-29|2010-03-04|Novellus Systems Inc.|Method for reducing tungsten roughness and improving reflectivity|
    US20100159694A1|2008-06-12|2010-06-24|Novellus Systems Inc.|Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics|
    US20100267235A1|2009-04-16|2010-10-21|Feng Chen|Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects|
    US20110059608A1|2009-09-09|2011-03-10|Novellus Systems, Inc.|Method for improving adhesion of low resistivity tungsten/tungsten nitride layers|
    US7955972B2|2001-05-22|2011-06-07|Novellus Systems, Inc.|Methods for growing low-resistivity tungsten for high aspect ratio and small features|
    US8062977B1|2008-01-31|2011-11-22|Novellus Systems, Inc.|Ternary tungsten-containing resistive thin films|
    US8709948B2|2010-03-12|2014-04-29|Novellus Systems, Inc.|Tungsten barrier and seed for copper filled TSV|
    US8853080B2|2012-09-09|2014-10-07|Novellus Systems, Inc.|Method for depositing tungsten film with low roughness and low resistivity|
    US8975184B2|2012-07-27|2015-03-10|Novellus Systems, Inc.|Methods of improving tungsten contact resistance in small critical dimension features|
    US9034760B2|2012-06-29|2015-05-19|Novellus Systems, Inc.|Methods of forming tensile tungsten films and compressive tungsten films|
    US9076843B2|2001-05-22|2015-07-07|Novellus Systems, Inc.|Method for producing ultra-thin tungsten layers with improved step coverage|
    US9153486B2|2013-04-12|2015-10-06|Lam Research Corporation|CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications|
    US9159571B2|2009-04-16|2015-10-13|Lam Research Corporation|Tungsten deposition process using germanium-containing reducing agent|
    US9240347B2|2012-03-27|2016-01-19|Novellus Systems, Inc.|Tungsten feature fill|
    US9589808B2|2013-12-19|2017-03-07|Lam Research Corporation|Method for depositing extremely low resistivity tungsten|
    US9613818B2|2015-05-27|2017-04-04|Lam Research Corporation|Deposition of low fluorine tungsten by sequential CVD process|
    US9754824B2|2015-05-27|2017-09-05|Lam Research Corporation|Tungsten films having low fluorine content|
    US9953984B2|2015-02-11|2018-04-24|Lam Research Corporation|Tungsten for wordline applications|
    US9978605B2|2015-05-27|2018-05-22|Lam Research Corporation|Method of forming low resistivity fluorine free tungsten film without nucleation|
    US9997405B2|2014-09-30|2018-06-12|Lam Research Corporation|Feature fill with nucleation inhibition|
    US10256142B2|2009-08-04|2019-04-09|Novellus Systems, Inc.|Tungsten feature fill with nucleation inhibition|JPS56120166A|1980-02-27|1981-09-21|Hitachi Ltd|Semiconductor ic device and manufacture thereof|
    JPS57130463A|1981-02-06|1982-08-12|Toshiba Corp|Semiconductor memory|
    DE3463805D1|1984-02-23|1987-06-25|Rodoverken Handel|Method of erecting large cylindrical storage tanks with a plurality of vertical plate bodies arranged inside one another|
    US4675982A|1985-10-31|1987-06-30|International Business Machines Corporation|Method of making self-aligned recessed oxide isolation regions|
    KR100212098B1|1987-09-19|1999-08-02|가나이 쓰도무|Semiconductor integrated circuit device and manufacturing method thereof, wiring board of semiconductor integrated circuit device and manufacturing method thereof|
    US4957787A|1987-10-19|1990-09-18|Ppg Industries, Inc.|Artificial flower|
    US4957878A|1988-05-02|1990-09-18|Micron Technology, Inc.|Reduced mask manufacture of semiconductor memory devices|
    US4951175A|1988-05-18|1990-08-21|Kabushiki Kaisha Toshiba|Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof|
    JP2633650B2|1988-09-30|1997-07-23|株式会社東芝|Semiconductor memory device and method of manufacturing the same|
    US5248628A|1989-09-08|1993-09-28|Kabushiki Kaisha Toshiba|Method of fabricating a semiconductor memory device|
    US5079177A|1989-09-19|1992-01-07|National Semiconductor Corporation|Process for fabricating high performance bicmos circuits|
    US5021848A|1990-03-13|1991-06-04|Chiu Te Long|Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof|
    US5057449A|1990-03-26|1991-10-15|Micron Technology, Inc.|Process for creating two thicknesses of gate oxide within a dynamic random access memory|
    US5225362A|1992-06-01|1993-07-06|National Semiconductor Corporation|Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer|
    US5672539A|1994-01-14|1997-09-30|Micron Technology, Inc.|Method for forming an improved field isolation structure using ozone enhanced oxidation and tapering|
    US5404037A|1994-03-17|1995-04-04|National Semiconductor Corporation|EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region|
    US5837574A|1995-05-10|1998-11-17|National Semiconductor Corporation|Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range|US7664263B2|1998-03-24|2010-02-16|Moskowitz Scott A|Method for combining transfer functions with predetermined key creation|
    TW412842B|1997-10-18|2000-11-21|United Microelectronics Corp|Method of making dual gate oxide|
    US6468855B2|1998-08-14|2002-10-22|Monolithic System Technology, Inc.|Reduced topography DRAM cell fabricated using a modified logic process and method for operating same|
    US6383861B1|1999-02-18|2002-05-07|Micron Technology, Inc.|Method of fabricating a dual gate dielectric|
    WO2001013421A1|1999-08-18|2001-02-22|Infineon Technologies North America Corp.|Method of simultaneously growing oxide layers with different ticknesses on a semiconductor body using selective implantations of oxygen and nitrogen|
    US6171911B1|1999-09-13|2001-01-09|Taiwan Semiconductor Manufacturing Company|Method for forming dual gate oxides on integrated circuits with advanced logic devices|
    US6248618B1|1999-10-12|2001-06-19|Chartered Semiconductor Manufacturing Ltd.|Method of fabrication of dual gate oxides for CMOS devices|
    US6583011B1|2000-01-11|2003-06-24|Chartered Semiconductor Manufacturing Ltd.|Method for forming damascene dual gate for improved oxide uniformity and control|
    US20070048882A1|2000-03-17|2007-03-01|Applied Materials, Inc.|Method to reduce plasma-induced charging damage|
    US6534414B1|2000-06-14|2003-03-18|Integrated Device Technology, Inc.|Dual-mask etch of dual-poly gate in CMOS processing|
    US6417037B1|2000-07-18|2002-07-09|Chartered Semiconductor Manufacturing Ltd.|Method of dual gate process|
    KR100421048B1|2001-09-07|2004-03-04|삼성전자주식회사|Semiconductor device having local interconnection layer & fabricating method thereof|
    US6831020B2|2001-11-05|2004-12-14|Matsushita Electric Industrial Co., Ltd.|Method for fabricating semiconductor device|
    US6579766B1|2002-02-15|2003-06-17|Infineon Technologies Ag|Dual gate oxide process without critical resist and without N2 implant|
    US6798013B2|2002-08-28|2004-09-28|Fernando Gonzalez|Vertically integrated flash memory cell and method of fabricating a vertically integrated flash memory cell|
    US6818514B2|2003-02-26|2004-11-16|Silterra Malaysia Sdn. Bhd.|Semiconductor device with dual gate oxides|
    JP4524735B2|2003-06-20|2010-08-18|ルネサスエレクトロニクス株式会社|Semiconductor memory device|
    US7323379B2|2005-02-03|2008-01-29|Mosys, Inc.|Fabrication process for increased capacitance in an embedded DRAM memory|
    US7491650B2|2005-07-27|2009-02-17|Micron Technology, Inc.|Etch compositions and methods of processing a substrate|
    US20070164366A1|2006-01-13|2007-07-19|Texas Instruments Incorporated|Mitigation of gate oxide thinning in dual gate CMOS process technology|
    JP4872395B2|2006-03-15|2012-02-08|ヤマハ株式会社|Silicon oxide film forming method, capacitor element manufacturing method, and semiconductor device manufacturing method|
    US20090069547A1|2007-05-01|2009-03-12|Massachusetts Institute Of Technology|Stabilization of mammalian membrane proteins by short surfactant peptides|
    法律状态:
    2003-08-12| CC| Certificate of correction|
    2006-09-22| FPAY| Fee payment|Year of fee payment: 4 |
    2010-01-04| AS| Assignment|Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Effective date: 20091223 Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Effective date: 20091223 |
    2010-09-16| FPAY| Fee payment|Year of fee payment: 8 |
    2014-11-21| REMI| Maintenance fee reminder mailed|
    2015-04-15| LAPS| Lapse for failure to pay maintenance fees|
    2015-05-11| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2015-06-02| FP| Expired due to failure to pay maintenance fee|Effective date: 20150415 |
    优先权:
    申请号 | 申请日 | 专利标题
    US08/548,011|US5863819A|1995-10-25|1995-10-25|Method of fabricating a DRAM access transistor with dual gate oxide technique|
    US09/191,235|US6204106B1|1995-10-25|1998-11-13|Method of fabricating a DRAM access transistor with dual gate oxide technique|
    US09/779,924|US6548340B2|1995-10-25|2001-02-08|Method of fabricating a DRAM transistor with a dual gate oxide technique|US09/779,924| US6548340B2|1995-10-25|2001-02-08|Method of fabricating a DRAM transistor with a dual gate oxide technique|
    US10/008,558| US6686246B2|1995-10-25|2001-11-13|Method of fabricating a DRAM transistor with a dual gate oxide technique|
    [返回顶部]