美国专利US20010008790A1 Semiconductor device and alignment method

专利PDF首页>>美国专利

专利附录

专利说明

权利要求

类似技术

同族专利

引用文献

法律状态

优先权

专利摘要:
A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
公开号:US20010008790A1
申请号:US09/769,710
申请日:2001-01-25
公开日:2001-07-19
发明作者:Gong Chen；Robert Colclasure
申请人:Gong Chen；Colclasure Robert D.；
IPC主号:G03F9-7084

专利说明:
[0001] The present invention relates in general to semiconductors, and more particularly to aligning a semiconductor die on a semiconductor wafer. [0001]
[0002] Semiconductor devices typically are fabricated as an array of dice formed on a semiconductor wafer. The devices are built up in successive layers of material formed into predetermined patterns. Patterns typically are produced by coating the wafer with a photoresist and activating a light path directed through a reticle functioning as a photomask. An alignment tool is used to align the wafer and reticle by locating an alignment mark on the reticle and one formed on the wafer during a previous processing step. Such alignment marks occupy regions of the wafer surface and can add significantly to the size of a semiconductor die. To minimize the increase in die size, many systems place alignment marks in inactive regions of the die such as scribe grids where there is no active circuitry. [0002]
[0003] Modern alignment tools electronically align a photomask to a wafer by locating alignment marks with optical sensors. The wafer and photomask positions are determined from the alignment marks and are adjusted by controlling the position of a wafer stage with a stepper motor and a feedback signal. Prior art alignment tools use multiple sets of alignment marks to improve sensing and alignment resolution. The multiple sets of alignment marks improve alignment but occupy a large die area that increases the cost of a semiconductor device. [0003]
[0004] Hence, there is a need for a semiconductor device aligned with a system that can reduce the die area and resulting manufacturing cost of the semiconductor device. [0004] BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 schematically illustrates a stepper alignment tool for aligning a reticle to a semiconductor wafer in accordance with the present invention; [0005]
[0006] FIG. 2 illustrates a prior art semiconductor wafer showing a set of prior art alignment marks; and [0006]
[0007] FIG. 3 illustrates a semiconductor wafer showing a set of alignment marks in accordance with the present invention. [0007] DETAILED DESCRIPTION OF THE DRAWINGS
[0008] In the figures, elements having the same reference number have similar functionality. [0008]
[0009] FIG. 1 schematically illustrates a stepper alignment tool [0009] 10 that exposes a photoresist coated surface 100 of a semiconductor wafer 101 for exposing a predetermined pattern on a region 103 of wafer 101. The predetermined pattern defines the configuration of a layer of material used to form electrical structures in region 103. Tool 10 senses the position of wafer 101 and the position of a reticle 111 and automatically adjusts their positions to align region 103 to reticle 111.
[0010] A light source [0010] 105 is activated to produce a light path 107 comprising optical waves at a deep ultraviolet or other specified wavelength. Light path 107 is directed through a focusing system, shown in the figure as a lens 109, to a reticle 111 containing clear and opaque regions formed in the predetermined pattern. Hence, reticle 111 functions as a photomask to screen out portions of light path 107 to transmit the predetermined pattern as a light path 13. In one embodiment, reticle 111 contains the predetermined pattern of one semiconductor die. In an alternate embodiment, reticle 111 can include shapes to form the predetermined pattern of a cluster of semiconductor dice in region 103. In order to accurately resolve small geometric features, the feature sizes of reticle 111 typically are four or five times the sizes to be printed on wafer 101.
[0011] Reticle [0011] 111 includes regions 121 and 123 containing shapes that function as alignment marks to align the predetermined pattern with patterns formed on wafer 101 during previous processing steps. A portion of light path 113 is transmitted through an optical sensor 125 to detect the position of the alignment marks in regions 121 and 123. Optical sensor 125 is configured to distinguish alignment marks from other patterns on reticle 111 by their respective shapes and orientations, as is known in the art. Optical sensor 125 produces a sense signal on node 141 indicative of the position of reticle 111. This sense signal is applied to a reticle position input of an alignment control circuit 151.
[0012] A lens [0012] 129 focuses light path 113 to produce a light path 114 focused in a region 103 of wafer 101 to expose a photoresist coating in the predetermined pattern. An optical sensor 131 operates in a similar fashion to optical sensor 125 but uses reflected light 147 from region 103 of surface 100 to detect the position of alignment marks in region 103. A representative sense signal is provided on a node 145 and applied to a wafer position input of alignment control circuit 151.
[0013] Alignment control circuit [0013] 151 receives information regarding the position of reticle 111 in the node 141 sense signal from sensor 125. Information regarding the position of region 103 of wafer 101 is received from sensor 131 in the node 145 sense signal. Alignment control circuit 151 processes these sense signals and provides a feedback signal on node 153 to drive a motor 155 that adjusts the position of a stage 157, and therefore of wafer 101. The adjustment continues until the alignment marks in region 103 are aligned with the alignment marks of reticle 111. In many alignment tools, the reticle and wafer stage are driven with separate motors to align to a stationary reference mark within the tool.
[0014] Region [0014] 103 defines a semiconductor die on which the predetermined pattern is formed in a single exposure by activating light source 105. Motor 155 has a stepping control input 159 for modifying the position of stage 157 in sequential steps to expose other regions of wafer 101 with similar patterns. Each of these regions is similarly aligned prior to activating light source 105. Hence each region includes its own alignment marks. When region 103 and the other regions each contain one semiconductor die, each of the dice on wafer 101 includes separate alignment marks. Alternatively, region 103 can include a cluster of semiconductor dice. Such a cluster is exposed at one time, and includes a single set of alignment keys for printing the predetermined pattern on all of the dice of the cluster. When all of the regions of surface 100 are printed, wafer 101 is removed for further processing.
[0015] FIG. 2 illustrates a portion of a semiconductor wafer [0015] 201 that uses prior art alignment marks. Wafer 201 includes a semiconductor die 203, illustrated by a dashed box, used in a semiconductor device such as an integrated circuit. Semiconductor die 203 includes an active region 205 containing electrical components for providing a circuit function, a first alignment region 207 that includes alignment marks 209, and a second alignment region 211 including alignment marks 213. Alignment marks 209 and 213 are detected in alignment tool 10 in order to align wafer 201, and are the same as those used on a Micrascan MSII model stepper alignment tool manufactured by the Silicon Valley Group.
[0016] A scribe grid [0016] 215 separates semiconductor die 203 from adjacent semiconductor dice on wafer 201. At the completion of wafer processing and testing, scribe grid 215 is scribed or sawed to singulate the dice of wafer 201 for subsequent packaging. To reduce the wafer area occupied by alignment regions 207 and 211, alignment regions 207 and 211 are included in scribe grid 215. Hence, when scribe grid 215 is sawed to singulate the dice of wafer 201, all or a portion of alignment regions 207 and 211 typically are sawed as well.
[0017] In accordance with the operation of alignment tool [0017] 10, the positions of alignment marks 209 and 213 are detected by optical sensor 131, and a representative sense signal is provided on node 145 of FIG. 1. Similar alignment marks on a reticle of the layer being aligned are detected by optical sensor 125 to produce a sense signal at node 141 to indicate the position of alignment marks on the reticle. The sense signals on nodes 141 and 145 are processed by alignment control circuit 151 to produce a control signal that causes motor 155 to adjust stage 157 in a direction that brings alignment marks 209 and 213 into alignment with corresponding alignment marks on the reticle.
[0018] Each alignment mark [0018] 209 comprises a pair of shapes angled at approximately forty-five degrees with respect to the sides of semiconductor die 203 and ninety degrees to each other. Similarly, each alignment mark 213 comprises a pair of shapes angled at approximately forty-five degrees with respect to the sides of semiconductor die 203 and ninety degrees from each other. However, alignment marks 209 have a different orientation from alignment marks 213, as shown in FIG. 2. That is, alignment marks 209 taper toward each other in one direction from active region 205, while alignment marks 213 taper toward each other in the opposite direction, so that alignment marks 209 and 213 are mirror images of each other. Optical sensor 131 distinguishes between alignment marks 209 and 213 by their different orientations. For accurate alignment, alignment marks with both orientations, i.e., tapering in opposite directions, are used.
[0019] Most processing steps such as etching or diffusion steps are performed in a batch mode. That is, the step is performed not only on a semiconductor die but also on the other semiconductor dice on the wafer. The cost of performing these processing steps is relatively constant for each wafer, so the cost for each semiconductor die is shared among all of the dice on a wafer. Hence, smaller semiconductor dice allow more dice to be formed on a wafer to share the fixed manufacturing cost, thereby reducing the manufacturing cost of each die. [0019]
[0020] The overall size of semiconductor die [0020] 203 is shown as the area inside of the dashed line in FIG. 2. This area includes the area of active region 205, alignment regions 207 and 211, and the portion of scribe grid 215 shown lying within the dashed line. The remainder portion of scribe grid 215, i.e., the portion outside of the dashed line, is attributed to the area of an adjacent die. Alignment regions 207 and 211 and scribe grid 215 are inactive regions of semiconductor die 203 in the sense that these regions are necessary to manufacture semiconductor die 203 but otherwise do not perform an active circuit function of a semiconductor device.
[0021] Scribe grid [0021] 215 has a typical width of at least one-hundred micrometers, which is added to the width of active region 205 to set the effective width of semiconductor die 203. Similarly, the heights of alignment regions 207 and 211 are one hundred ten micrometers each, or a total of two hundred twenty micrometers. Hence, two hundred twenty micrometers are added to the height of active region 205 to set the height of semiconductor die 203.
[0022] FIG. 3 illustrates a portion of semiconductor wafer [0022] 101 including region 103, which contains a single semiconductor die designated herein as semiconductor die 103 because no other die is formed in region 103. Semiconductor die 103 operates as an integrated circuit or other semiconductor device. Semiconductor die 103 includes an active region 161 containing electrical components for providing a circuit function. Active region 161 is surrounded by a scribe grid 191 that includes first and second alignment regions 163 and 169.
[0023] Note that first alignment region [0023] 163 includes alignment marks 165 and 167 which overlap to occupy the same area but are used to align different dice. Alignment marks 165 are used to align semiconductor die 103, while alignment marks 167 are used to align an adjacent semiconductor die 181 during a different exposure in alignment tool 10. Similarly, second alignment region 169 includes overlapping alignment marks 171 and 173. Alignment marks 171 are also used to align semiconductor die 103, but alignment marks 173 are used to align an adjacent semiconductor die 183 during a different exposure. Hence, alignment regions 163 and 169 include alignment marks which overlap in the same area but are used to align different semiconductor dice.
[0024] Alignment marks [0024] 165 have sizes and orientations in relation to active region 161 similar to prior art alignment marks 209, and alignment marks 171 have similar sizes and orientations as prior art alignment marks 213 as shown in FIG. 2. Similarly, alignment marks 173 are similar to alignment marks 209 and alignment marks 167 are similar to alignment marks 213. Alignment tool 10 can distinguish between alignment marks 165 and 167 because they have a mirror image orientation to each other. Alignment marks 171 and 173 can be distinguished because they have a mirror image orientation to each other as previously described. Hence, alignment marks for different dice which are printed in different exposures are overlapped to share the same alignment region of wafer 101.
[0025] The alignment scheme of the present invention can also be applied to multiple layers formed on semiconductor die [0025] 103 with different exposures. That is, where semiconductor die 103 has a first layer aligned with a first alignment mark disposed in alignment region 163, a second layer of die 103 can be aligned with a second alignment mark disposed in alignment region 163 during a later stage in the process. Die area can be reduced by disposing the second alignment mark to overlap the first alignment mark to reuse the same space of region 163.
[0026] Alignment tool [0026] 10 detects alignment marks 165 and 171 when aligning semiconductor die 103. Alignment marks 167 are detected when aligning semiconductor die 181 and alignment marks 173 are detected when aligning semiconductor die 183. In other words, when aligning semiconductor die 103, alignment tool 10 selects alignment marks 165 and 171 but rejects alignment marks 167 and 173. The die size and cost are reduced because the overlapping alignment marks eliminate the need for an extra alignment region as in the prior art. As a result, the present invention reduces the height of semiconductor die 103 by the height of one alignment region, or at least one hundred ten micrometers as compared to prior art alignment schemes. The reduced height proportionally reduces the effective die area, which allows more dice to be formed on wafer 101 to share the wafer manufacturing cost. The height of each die is reduced by a fixed amount, so the cost benefit is more significant for dice having smaller active regions.
[0027] In summary, the present invention provides a technique for reducing the die area and cost of a semiconductor device. A wafer includes a semiconductor die having a first alignment mark disposed in a region for aligning the die on the semiconductor wafer. A second die has a second alignment mark for aligning the second die. The second alignment mark is disposed to overlap the first alignment mark. The overlapping alignment marks allow the area occupied by the first and second alignment marks to be shared between adjacent dice, thereby reducing the cost of each die. Moreover, the advantages of the present invention can be obtained without modifying the existing manufacturing process or requiring additional processing steps or equipment. [0027]

权利要求:
Claims (17)
[1" id="US-20010008790-A1-CLM-00001] 1. A semiconductor wafer, comprising:
a first die having a first alignment mark disposed in a first region of the semiconductor wafer for aligning the first die; and
a second die having a second alignment mark disposed in the first region for aligning the second die, where the second alignment mark overlaps the first alignment mark.
[2" id="US-20010008790-A1-CLM-00002] 2. The semiconductor wafer of
claim 1 , further including a scribe grid disposed between the first die and the second die, where the first region is formed in the scribe grid.
[3" id="US-20010008790-A1-CLM-00003] 3. The semiconductor wafer of
claim 2 , wherein the first alignment mark is for forming a predetermined pattern in a material of the first die, and the second alignment mark is for forming the predetermined pattern in a material of the second die.
[4" id="US-20010008790-A1-CLM-00004] 4. The semiconductor wafer of
claim 3 , wherein the first alignment mark has a first orientation with respect to the first die and the second alignment mark has a second orientation with respect to the second die which is different from the first orientation.
[5" id="US-20010008790-A1-CLM-00005] 5. The semiconductor wafer of
claim 3 , wherein the second alignment mark is formed as a mirror image of the first alignment mark.
[6" id="US-20010008790-A1-CLM-00006] 6. The semiconductor wafer of
claim 3 , wherein the first and second alignment marks are for aligning the first and second die in a stepper alignment tool.
[7" id="US-20010008790-A1-CLM-00007] 7. The semiconductor wafer of
claim 1 , wherein the first die includes a first layer aligned to the first alignment mark and a second layer aligned to a third alignment mark of the first die, and the third alignment mark overlaps the first alignment mark.
[8" id="US-20010008790-A1-CLM-00008] 8. A method of manufacturing semiconductor devices, comprising the steps of:
aligning a first semiconductor device on a semiconductor wafer with a first alignment mark of the first semiconductor device; and
aligning a second semiconductor device on the semiconductor wafer with a second alignment mark of the second semiconductor device, where the second alignment mark overlaps the first alignment mark.
[9" id="US-20010008790-A1-CLM-00009] 9. The method of
claim 8 , further comprising the steps of:
forming a scribe grid on the semiconductor wafer between the first and second semiconductor devices; and
forming the first alignment mark in a region of the scribe grid.
[10" id="US-20010008790-A1-CLM-00010] 10. The method of
claim 9 , further comprising the step of disposing the second alignment mark in the region of the scribe grid.
[11" id="US-20010008790-A1-CLM-00011] 11. The method of
claim 9 , wherein the step of forming the first alignment mark includes the step of forming the first alignment mark to have a first orientation on the semiconductor wafer.
[12" id="US-20010008790-A1-CLM-00012] 12. The method of
claim 11 , wherein the step of forming the second alignment mark includes the step of forming the second alignment mark to have a second orientation on the semiconductor wafer that is different from the first orientation.
[13" id="US-20010008790-A1-CLM-00013] 13. The method of
claim 12 , wherein the step of forming the second alignment mark includes the step of forming the second alignment mark as a mirror image of the first alignment mark.
[14" id="US-20010008790-A1-CLM-00014] 14. The method of
claim 8 , further comprising the steps of:
coating the semiconductor wafer with a photoresist;
aligning the first semiconductor device in a stepper alignment tool; and
activating a light path in the stepper alignment tool to expose the photoresist in a predetermined pattern to produce the first semiconductor device.
[15" id="US-20010008790-A1-CLM-00015] 15. A semiconductor device comprising a first die formed on a semiconductor wafer, where the first die includes a first alignment mark for aligning the first die, and the semiconductor wafer includes a second die having a second alignment mark overlapping the first alignment mark for aligning the second die.
[16" id="US-20010008790-A1-CLM-00016] 16. The semiconductor device of
claim 15 , wherein the semiconductor wafer further includes a scribe grid disposed between the first die and the second die, and the first alignment mark shares a first region of the scribe grid with the second alignment mark.
[17" id="US-20010008790-A1-CLM-00017] 17. The semiconductor device of
claim 16 , wherein the first alignment mark is disposed in the first region with a first orientation, and the second alignment mark is disposed in the first region to have a second orientation.

类似技术:

公开号 | 公开日 | 专利标题

US6228743B1|2001-05-08|Alignment method for semiconductor device

US7187429B2|2007-03-06|Alignment method, exposure apparatus and device fabrication method

US6218200B1|2001-04-17|Multi-layer registration control for photolithography processes

US6114072A|2000-09-05|Reticle having interlocking dicing regions containing monitor marks and exposure method and apparatus utilizing same

EP1039511A1|2000-09-27|Projection exposure method and projection aligner

EP1843209A2|2007-10-10|Exposure apparatus and device manufacturing method

US4657379A|1987-04-14|Photomask and exposure apparatus using the same

JPH11168053A|1999-06-22|Electron beam exposure method and semiconductor wafer

US4798470A|1989-01-17|Pattern printing method and apparatus

EP0031680B1|1984-04-18|Focusing apparatus

JPH08250406A|1996-09-27|Exposure of semiconductor wafer

JP3210145B2|2001-09-17|Scanning exposure apparatus and method for manufacturing a device using the apparatus

US5753926A|1998-05-19|Scan type exposure apparatus and method having a reference plate with marks for image detection

JP3261948B2|2002-03-04|X-ray exposure mask and method for manufacturing semiconductor device using the same

US7144690B2|2006-12-05|Photolithographic methods of using a single reticle to form overlapping patterns

KR100444263B1|2004-08-11|Exposure apparatus and device manufacturing method

JP3245556B2|2002-01-15|Mix and match exposure method

US10895809B2|2021-01-19|Method for the alignment of photolithographic masks and corresponding process for manufacturing integrated circuits in a wafer of semiconductor material

JPH1174190A|1999-03-16|X-ray aligner

US6468704B1|2002-10-22|Method for improved photomask alignment after epitaxial process through 90° orientation change

US6784974B1|2004-08-31|Exposure method and exposure apparatus

KR19980031092A|1998-07-25|Wafer Exposure Method

KR20050051502A|2005-06-01|Focusing and leveling unit for exposure equipment and exposure method using the same

JPH1079331A|1998-03-24|Exposing method and wafer applicable thereto

JP2005116965A|2005-04-28|Exposure system and its control method

同族专利:

公开号 | 公开日

US6228743B1|2001-05-08|

TW421822B|2001-02-11|

US6509247B2|2003-01-21|

KR19990088024A|1999-12-27|

KR100576675B1|2006-05-04|

EP0955566A3|2001-09-05|

JPH11345866A|1999-12-14|

EP0955566A2|1999-11-10|

JP4336416B2|2009-09-30|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US20060278956A1|2003-03-13|2006-12-14|Pdf Solutions, Inc.|Semiconductor wafer with non-rectangular shaped dice|

US20090262319A1|2008-03-10|2009-10-22|Hiroyasu Matsuura|Maskless exposure method|

CN102063015A|2009-11-16|2011-05-18|台湾积体电路制造股份有限公司|Semiconductor wafer and pattern alignment method|

US8455162B2|2011-06-28|2013-06-04|International Business Machines Corporation|Alignment marks for multi-exposure lithography|

US20140139445A1|2011-11-27|2014-05-22|Jiadong Chen|Touch sensing device and a method of fabricating the same|JPS5424829B2|1975-07-21|1979-08-23|||

JPS6135693B2|1980-12-29|1986-08-14|Fujitsu Ltd||

US4620785A|1982-12-01|1986-11-04|Canon Kabushiki Kaisha|Sheet-like member having alignment marks and an alignment apparatus for the same|

US4623257A|1984-12-28|1986-11-18|At&T Bell Laboratories|Alignment marks for fine-line device fabrication|

US4849313A|1988-04-28|1989-07-18|Vlsi Technology, Inc.|Method for making a reticle mask|

EP0543361B1|1991-11-20|2002-02-27|Canon Kabushiki Kaisha|Method of manufacturing a semiconductor device|

US5998295A|1996-04-10|1999-12-07|Altera Corporation|Method of forming a rough region on a substrate|

JP3634505B2|1996-05-29|2005-03-30|株式会社ルネサステクノロジ|Alignment mark placement method|

US5943587A|1997-06-25|1999-08-24|International Business Machines Corporation|Method for making offset alignment marks|

KR100315911B1|1997-10-10|2002-09-25|삼성전자 주식회사|Liquid crystal display panel, method for fabricating the same and method for aligning the same|

US5952135A|1997-11-19|1999-09-14|Vlsi Technology|Method for alignment using multiple wavelengths of light|

US6228743B1|1998-05-04|2001-05-08|Motorola, Inc.|Alignment method for semiconductor device|US6228743B1|1998-05-04|2001-05-08|Motorola, Inc.|Alignment method for semiconductor device|

KR100268426B1|1998-05-07|2000-11-01|윤종용|Manufacturing Method of Semiconductor Device|

JP3065309B1|1999-03-11|2000-07-17|沖電気工業株式会社|Method for manufacturing semiconductor device|

WO2001009927A1|1999-07-28|2001-02-08|Infineon Technologies North America Corp.|Semiconductor structures and manufacturing methods|

US7067931B1|2000-12-14|2006-06-27|Koninklijke Philips Electronics N.V.|Self-compensating mark design for stepper alignment|

US6709793B1|2002-10-31|2004-03-23|Motorola, Inc.|Method of manufacturing reticles using subresolution test patterns|

TWI302348B|2002-11-08|2008-10-21|Nanya Technology Corp||

US6864956B1|2003-03-19|2005-03-08|Silterra Malaysia Sdn. Bhd.|Dual phase grating alignment marks|

KR100519789B1|2003-03-20|2005-10-10|삼성전자주식회사|An align method of a semiconductor substrate|

US6908830B2|2003-06-23|2005-06-21|International Business Machines Corporation|Method for printing marks on the edges of wafers|

JP2006140338A|2004-11-12|2006-06-01|Matsushita Electric Ind Co Ltd|Semiconductor device|

US7408461B2|2005-01-11|2008-08-05|Controlled Capture Systems, Llc|Metal detection system and method|

KR100620430B1|2005-04-29|2006-09-06|삼성전자주식회사|Alignment key structure of a semiconductor device and method of forming the same|

US7687925B2|2005-09-07|2010-03-30|Infineon Technologies Ag|Alignment marks for polarized light lithography and method for use thereof|

US20080265445A1|2007-04-30|2008-10-30|International Business Machines Corporation|Marks for the Alignment of Wafer-Level Underfilled Silicon Chips and Method to Produce Same|

US8139219B2|2008-04-02|2012-03-20|Suss Microtec Lithography, Gmbh|Apparatus and method for semiconductor wafer alignment|

US7897481B2|2008-12-05|2011-03-01|Taiwan Semiconductor Manufacturing Company, Ltd.|High throughput die-to-wafer bonding using pre-alignment|

US20120049186A1|2010-08-31|2012-03-01|Li Calvin K|Semiconductor structures|

US20120140193A1|2010-12-03|2012-06-07|Nanya Technology Corporation|Dynamic wafer alignment method in exposure scanner system|

KR20120100243A|2011-03-03|2012-09-12|삼성전자주식회사|Meothods of disposing alignment keys and meothods of forming semiconductor chips using the same|

US9323882B2|2014-03-28|2016-04-26|Globalfoundries Inc.|Metrology pattern layout and method of use thereof|

US10134624B2|2015-03-26|2018-11-20|Doug Carson & Associates, Inc.|Substrate alignment detection using circumferentially extending timing pattern|

US9953806B1|2015-03-26|2018-04-24|Doug Carson & Associates, Inc.|Substrate alignment detection using circumferentially extending timing pattern|

WO2016154539A1|2015-03-26|2016-09-29|Doug Carson & Associates, Inc.|Substrate alignment through detection of rotating tming pattern|

US9659873B2|2015-08-26|2017-05-23|United Microelectronics Corp.|Semiconductor structure with aligning mark and method of forming the same|

US9754895B1|2016-03-07|2017-09-05|Micron Technology, Inc.|Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses|

WO2017177300A1|2016-04-15|2017-10-19|Teledyne Dalsa, Inc.|Alignment of multiple image dice in package|

法律状态:
2003-01-02| STCF| Information on status: patent grant|Free format text: PATENTED CASE |

2004-05-07| AS| Assignment|Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 |

2006-06-22| FPAY| Fee payment|Year of fee payment: 4 |

2007-02-02| AS| Assignment|Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |

2010-05-13| AS| Assignment|Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 |

2010-06-22| FPAY| Fee payment|Year of fee payment: 8 |

2013-06-18| AS| Assignment|Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424 Effective date: 20130521 |

2013-11-06| AS| Assignment|Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |

2014-07-21| FPAY| Fee payment|Year of fee payment: 12 |

2015-12-21| AS| Assignment|Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553 Effective date: 20151207 |

2016-01-12| AS| Assignment|Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517 Effective date: 20151207 |

2016-01-13| AS| Assignment|Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |

2016-06-16| AS| Assignment|Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |

2016-09-21| AS| Assignment|Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |

2016-11-07| AS| Assignment|Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |

2016-11-08| AS| Assignment|Owner name: NXP USA, INC., TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:040652/0241 Effective date: 20161107 Owner name: NXP USA, INC., TEXAS Free format text: MERGER;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:040652/0241 Effective date: 20161107 |

2017-01-05| AS| Assignment|Owner name: NXP USA, INC., TEXAS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:041260/0850 Effective date: 20161107 |

2017-02-01| AS| Assignment|Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |

2019-02-20| AS| Assignment|Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |

2019-09-10| AS| Assignment|Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |

2019-12-10| AS| Assignment|Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421 Effective date: 20151207 |

2020-01-17| AS| Assignment|Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |

2020-02-17| AS| Assignment|Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |

优先权:

申请号 | 申请日 | 专利标题

US09/072,052|US6228743B1|1998-05-04|1998-05-04|Alignment method for semiconductor device|

US09/769,710|US6509247B2|1998-05-04|2001-01-25|Semiconductor device and alignment method|US09/769,710| US6509247B2|1998-05-04|2001-01-25|Semiconductor device and alignment method|

[返回顶部]