• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.
    公开号:US20010007788A1
    申请号:US09/761,943
    申请日:2001-01-17
    公开日:2001-07-12
    发明作者:Ting-Chang Chang；Yi-Shien Mor；Po-Tsun Liu
    申请人:United Microelectronics Corp；
    IPC主号:H01L21-7682
    专利说明:
    [0001] This application claims the priority benefit of Taiwan application serial no. 90100427, filed 2001/1/9. [0001] BACKGROUND OF THE INVENTION
    [0002] 1. Field of Invention [0002]
    [0003] The present invention relates to a metal-oxide-semiconductor structure and corresponding method of manufacture. More particularly, the present invention relates to an air gap semiconductor structure and corresponding method of manufacture. [0003]
    [0004] 2. Description of Related Art [0004]
    [0005] Following the rapid reduction of semiconductor line width, the accompanied increase in resistor-capacitor (RC) time delay has greatly reduced the operating speed of integrated circuits. To reduce RC time delay, methods that can lower resistance is frequently adopted. The most common trend now is to replace conventional aluminum wires by copper wires. [0005]
    [0006] A second way of reducing RC time delay is to reduce capacitance between conductive wires in a multi-layer design. Conventional silicon dioxide is no longer versatile enough for this purpose because silicon dioxide has a relatively high dielectric constant. In general, low dielectric constant organic or inorganic material is used to form inter-metal dielectric layer. However, a medium having the lowest dielectric constant is air (a dielectric constant of 1). Therefore, air is ideal dielectric medium for lowering the capacitance of a capacitor. [0006]
    [0007] Although air is the best dielectric material for lowering capacitance, overall mechanical strength of the device is reduced correspondingly. A weakened structure can have serious effect in various aspects of subsequent integrated circuit fabrication. [0007]
    [0008] A device having air as a dielectric medium generally has air gaps between metallic lines. Air gaps will destabilize the semiconductor device and lead to structural deformation. Moreover, the air gaps are normally distributed all over the substrate. Although capacitor has low capacitance when air is used as a dielectric medium layer, poor heat conductivity of air often leads to a rapid accumulation of heat and a rise in temperature during operation. [0008] SUMMARY OF THE INVENTION
    [0009] Accordingly, one object of the present invention is to provide an air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro- porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. Finally, a dielectric layer is formed over the substrate and the metal lines and between the second spacers. [0009]
    [0010] In this invention, air gaps are only formed on the sidewalls of the metal lines. Other sections of the substrate are covered by conventional dielectric material. With this arrangement, not only can RC delay be lowered to increase operating speed of integrated circuits, mechanical strength of the integrated circuit can also be maintained. [0010]
    [0011] In addition, the micro-porous structure layer increases the diffusion efficiency of by-products generated during the dissociation of the sacrificial polymer film, especially in the region between neighboring metal lines where height/separation ratio is high. [0011]
    [0012] Furthermore, since only spacer-like air gaps are formed on the sidewalls of the metal lines, heat generated during device operation can easily be channeled away through surrounding conductive layer. Hence, heat dissipation problem can be ignored. [0012]
    [0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. [0013] BRIEF DESCRIPTION OF THE DRAWINGS
    [0014] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0014]
    [0015] FIGS. 1 through 6 are schematic cross-sectional views showing the progression of steps for manufacturing an air gap semiconductor device according to one preferred embodiment of this invention. [0015] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0016] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. [0016]
    [0017] FIGS. 1 through 6 are schematic cross-sectional views showing the progression of steps for manufacturing an air gap semiconductor device according to one preferred embodiment of this invention. [0017]
    [0018] As shown in FIG. 1, a substrate [0018] 100 having metal lines 102 thereon is provided. The substrate 100 can be a semiconductor layer having multi-layered interconnects, for example. A sacrificial polymer film 104 is formed over the metal lines and the substrate 100. The sacrificial polymer film 104 is a low temperature dissociation polymer layer formed, for example, by spin-coating. The sacrificial film 104 can be a material layer having a dissociation temperature between 300° C. to 430° C., for example, polynorbornene.
    [0019] As shown in FIG. 2, a portion of the sacrificial film [0019] 104 is etched back to form first spacers 104 a on the sidewalls of the metal lines 102.
    [0020] As shown in FIG. 3, a micro-porous structure layer [0020] 106 is formed over the substrate 100 and the metal lines 102 and between the spacers 104 a. The micro-porous structure layer 106 can be formed, for example, by spin-coating. Materials that may form the micro-porous structure layer 106 include inorganic porous silicon dioxide and organic porous material, for example, Sol-gel, Xerogel, porous polyimide and porous metheyl silsesquioxane (MSQ).
    [0021] As shown in FIG. 4, a portion of the micro-porous structure layer [0021] 106 is removed by etching back to form second spacers 106 a on the sidewalls of the first spacers 104 a.
    [0022] As shown in FIG. 5, the substrate [0022] 100 is put inside a furnace and heated to between about 400° C. to 450° C. The sacrificial spacers 104 a dissociate into small molecular weight by-products (not shown). By diffusion, the by-products penetrate through the second spacers 106 a into outer regions. Ultimately, the space originally occupied by the first spacers 104 a is turned into air gaps 108.
    [0023] As shown in FIG. 6, a dielectric layer [0023] 110 is formed over the substrate 100 and the metal lines 102 and between the second spacers 106 a. The dielectric layer 110 can be a silicon dioxide layer formed, for example, by plasma-enhanced chemical vapor deposition (PECVD) or spin-on-glass (SOG).
    [0024] By forming porous second spacers [0024] 106 a over the first spacers 104 a before the dielectric layer 110, by-products of the dissociation can easily escape from the space originally occupied by the first spacers 104 a. This is particularly important for diffusing by-products away from a region having a high aspect ratio such as the space between neighboring metal lines.
    [0025] In summary, the advantages of the invention includes: [0025]
    [0026] 1. Air gaps are only formed on the sidewalls of the metal lines. Other sections of the substrate are covered by conventional dielectric material. With this arrangement, not only can RC delay be lowered to increase operating speed of integrated circuits, mechanical strength of the integrated circuit can also be maintained. [0026]
    [0027] 2. The micro-porous structure layer increases the diffusion efficiency of by-products generated during the dissociation of the sacrificial polymer film, especially in the region between neighboring metal lines where height/separation ratio is high. [0027]
    [0028] 3. Since only spacer-like air gaps are formed on the sidewalls of the metal lines, heat generated during device operation can easily be channeled away through surrounding conductive layer. Hence, heat dissipation problem can be ignored. [0028]
    [0029] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0029]
    权利要求:
    Claims (19)
    [1" id="US-20010007788-A1-CLM-00001] 1. A method of manufacturing an air gap semiconductor device, comprising the steps of:
    providing a substrate having a plurality of metal lines thereon;
    forming a sacrificial polymer film over the substrate and the metal lines;
    removing a portion of the sacrificial polymer film to form a first spacers on each sidewall of the metal lines;
    forming a micro-porous structure layer over the substrate and the metal lines and between the first spacers;
    removing a portion of the micro-porous structure layer to form a second spacers on each sidewalls of the first spacers;
    removing the first spacers; and
    forming a dielectric layer over the substrate and the metal lines and between the second spacers.
    [2" id="US-20010007788-A1-CLM-00002] 2. The method of
    claim 1 , wherein the step of forming the sacrificial polymer film includes depositing a polymer compound that has a dissociation temperature between about 300° C. to 430° C.
    [3" id="US-20010007788-A1-CLM-00003] 3. The method of
    claim 2 , wherein the polymer compound includes polynorbornene.
    [4" id="US-20010007788-A1-CLM-00004] 4. The method of
    claim 1 , wherein the step of forming the micro-porous structure layer includes depositing porous inorganic silicon dioxide.
    [5" id="US-20010007788-A1-CLM-00005] 5. The method of
    claim 1 , wherein the step of forming the micro-porous structure layer includes depositing porous organic material.
    [6" id="US-20010007788-A1-CLM-00006] 6. The method of
    claim 5 , wherein the porous organic material includes polyimide.
    [7" id="US-20010007788-A1-CLM-00007] 7. The method of
    claim 1 , wherein the step of forming the sacrificial polymer film includes spin-coating.
    [8" id="US-20010007788-A1-CLM-00008] 8. The method of
    claim 1 , wherein the step of removing a portion of the sacrificial layer includes etching.
    [9" id="US-20010007788-A1-CLM-00009] 9. The method of
    claim 1 , wherein the step of forming the micro-porous structure layer includes spin-coating.
    [10" id="US-20010007788-A1-CLM-00010] 10. The method of
    claim 1 , wherein the step of removing a portion of the micro-porous structure layer includes etching.
    [11" id="US-20010007788-A1-CLM-00011] 11. The method of
    claim 1 , wherein the step of removing the first spacers includes the sub-steps of:
    dissociating the first spacers into by-products by heating; and
    removing the by-products through outward diffusion through the second spacers.
    [12" id="US-20010007788-A1-CLM-00012] 12. The method of
    claim 11 , wherein the step of removing the first spacers includes heating to a temperature between 400° C. to 450° C.
    [13" id="US-20010007788-A1-CLM-00013] 13. The method of
    claim 1 , wherein the step of forming the dielectric layer includes depositing silicon dioxide.
    [14" id="US-20010007788-A1-CLM-00014] 14. An air gap semiconductor device, comprising:
    a substrate having a plurality of metal lines thereon;
    a micro-porous structure layer on each sidewall of the metal lines and an air gap at the junction between the micro-porous structure layer and the metal line; and
    a dielectric layer over the substrate, the metal lines and the sidewalls of the micro-porous structure layers.
    [15" id="US-20010007788-A1-CLM-00015] 15. The device of
    claim 14 , wherein material constituting the micro-porous structure layer includes porous inorganic silicon dioxide.
    [16" id="US-20010007788-A1-CLM-00016] 16. The device of
    claim 14 , wherein material constituting the micro-porous structure layer includes porous organic compound.
    [17" id="US-20010007788-A1-CLM-00017] 17. The device of
    claim 16 , wherein the porous organic compound includes polyimide.
    [18" id="US-20010007788-A1-CLM-00018] 18. The device of
    claim 14 , wherein the dielectric layer includes a silicon dioxide layer formed by plasma-enhanced chemical vapor deposition.
    [19" id="US-20010007788-A1-CLM-00019] 19. The device of
    claim 14 , wherein the dielectric layer includes a silicon dioxide layer formed by spin-on-glass method.
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    法律状态:
    2001-01-17| AS| Assignment|Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, TING-CHANG;MOR, YI-SHIEN;LIU, PO-TSUN;REEL/FRAME:011481/0307 Effective date: 20010110 |
    2003-10-02| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2007-03-22| FPAY| Fee payment|Year of fee payment: 4 |
    2011-03-20| FPAY| Fee payment|Year of fee payment: 8 |
    2015-03-25| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    TW90100427A||2001-01-09||
    TW90100427||2001-01-09||
    TW090100427A|TW476135B|2001-01-09|2001-01-09|Manufacture of semiconductor with air gap|US10/100,895| US6498070B2|2001-01-09|2002-03-18|Air gap semiconductor structure and method of manufacture|
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