• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An add/drop cross connection apparatus of an SDH system, comprises an aggregate unit matching device for providing matching with the aggregate units, a higher order path connection circuit for subjecting received higher order path data to cross connection by space switching, a lower order path connection circuit for subjecting received lower order path data to cross connection by space switching, and a selector for selectively delivering the data supplied from the aggregate units, higher order tributary device, and lower order tributary device, wherein the selector delivers the data to the higher order path connection circuit or lower order path connection circuit according as the data is the higher or lower order path data.
    公开号:US20010007564A1
    申请号:US09/756,866
    申请日:2001-01-10
    公开日:2001-07-12
    发明作者:Jai Park
    申请人:Samsung Electronics Co Ltd；
    IPC主号:H04J3-08
    专利说明:
    [0001] This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §119 from an application entitled [0001] Add/Drop Cross Connection Apparatus For Synchronous Digital Hierarchy earlier filed in the Korean Industrial Property Office on Jan. 10, 2000, and there duly assigned Ser. No. 2000-897 by that Office. BACKGROUND OF THE INVENTION
    [0002] 1. Field of the Invention [0002]
    [0003] The present invention relates to a synchronous digital hierarchy system (SDH System), and more particularly to an add/drop cross connection apparatus for an SDH system. [0003]
    [0004] 2. Description of the Related Art [0004]
    [0005] Cross-connects are electronic multiport switches for digital traffic and are known in the United States as digital cross-connect switches (DCSs) and as DXCs elsewhere. They are classified as DCS p/q or DXC p/q, where p is the hierarchical order of a port bit rate and q is the hierarchical order of the traffic component that is switched within that port bit rate. [0005]
    [0006] DXC/DCS can occur in two main types. Higher order cross-connects, generally used to route bulk traffic in blocks of nominally 155 MBPS for network provisioning or restoration, and are designated as DXC 4/4. Lower order cross-connects (DXC 4/1, or 1/1) are used for time switching leased lines, consolidation, and service restoration. [0006]
    [0007] In an add/drop cross connection apparatus of an exemplary SDH system, the data supplied from a west or east aggregate unit is divided into lower and the higher order path data. The lower order path data (or lower order virtual container (VC)) may be TU11 (Tributary Unit 11) or TU12 data processed by a TU pointer while the higher order path data (or higher order virtual container) may be AU3 (Administrative Unit 3) or AU4 data and has an AU pointer. [0007]
    [0008] The lower order path data supplied from the west or east aggregate unit is matched to the system clock through a multiplex section adaptation circuit and supplied to a higher order path overhead monitor circuit. The higher order path overhead monitor circuits respectively monitors the higher order path overheads of the data respectively supplied from the multiplex section adaptation circuits, which are then delivered to the higher order path connection circuit. The higher order path connection circuit performs the cross connection to the lower order path data by space switching and supplying the lower order path data to the lower order path data processor, which performs the cross connection to the data, aligns the data, and detects and monitors various path overheads. The data processed by the lower order path data processor is delivered to a lower order tributary device. [0008]
    [0009] Meanwhile, the higher order path data supplied from the west or east aggregate unit and supplied to the higher order path overhead monitor circuit is matched to the system clock through the multiplex section adaptation circuit. The higher order path overhead monitor circuit respectively monitors the higher order path overheads of the data respectively supplied from the multiplex section adaptation circuits and delivers the higher order path data to the higher order path connection circuit. The higher order path connection circuit performs the cross connection to the higher order path data by space switching and supplies the higher order path data to a higher order tributary device, which may be a known device such as DS3 (Digital Signal Level 3 of 44.736 MBPS), OC-1 (Optical Carrier supporting a Synchronous Transport Signal, Level 1 of 51.840 MBPS), STM-1 (Synchronous Transport Module, Level 1 of 155.520 MBPS) or STM-4 (Synchronous Transport Module, Level 4 of 622.080 MBPS) equipment. The SDH system is based upon the fundamental STM-1 rate, which is three times the fundamental SONET (Synchronous Optical NETwork) rate. The typical transmission media is defined to be an optical fiber, but the Broadband ISDN specification does define a User-Network Interface (UNI) STM-1 operating over coaxial cables. [0009]
    [0010] In addition, the lower order path data supplied from the lower order tributary device is subjected through the lower order path data processor to the cross connection by time switching and delivered to the higher order path connection circuit. The higher order path connection circuit subjects the input data to cross connection by space switching and then supplies the data via a higher order unequipped generator to the west or east aggregate units. Meanwhile, the higher order path data supplied from the higher order tributary device is subjected through the higher order path connection circuit to cross connection by space switching and delivered through the higher order unequipped generator to the west or east aggregate units. [0010]
    [0011] Hence, such add/drop cross connection apparatus is so complicated as to have one connecting path connecting it to the lower order tributary device and to separately have a second connecting path connecting it to the higher order tributary device. [0011]
    [0012] Incorporated by reference herein are: U.S. Pat. No. 6,094,440 to Toshiki Sugawara et al. entitled [0012] Multiplex Type Transmitting Apparatus; U.S. Pat. No. 5,914,952 to Doo Seop Eom et al. entitled Tributary Unit Signal Cross-Connection Apparatus; U.S. Pat. No. 5,799,001 to Dong Choon Lee et al. entitled Composite Network Protective/Recovering Device For Synchronous Digital Hierarchy DXC; U.S. Pat. No. 5,777,998 to Giovanni Traverso et al. entitled Method And Circuit Arrangement For The Realization Of The Higher Path Adaptation/Mapping Function In Synchronous Digital Hierarchy/Optical Network Equipment; U.S. Pat. No. 5,574,717 to Masahito Tomizawa et al. entitled Line Terminating Equipment In SDH Networks, Using Forward Error Correcting Codes; and U.S. Pat. No. 5,555,248 to Eiji Sugawara entitled Tandem Connection Maintenance System. SUMMARY OF THE INVENTION
    [0013] It is an object of the present invention to provide an add/drop cross connection apparatus of an SDH system that is simplified by combining the path connecting the lower order tributary device and the path connecting the higher order tributary device. [0013]
    [0014] According to an aspect of the present invention, an add/drop cross connection apparatus of an SDH system, comprises an aggregate unit matching device for providing matching with the aggregate units, a higher order path connection circuit for subjecting received higher order path data to cross connection by space switching, a lower order path connection circuit for subjecting received lower order path data to cross connection by space switching, and a selector for selectively delivering the data supplied from the aggregate units, higher order tributary device, and lower order tributary device, wherein the selector delivers the data to the higher order path connection circuit or lower order path connection circuit according to whether the data is the higher or lower order path data. [0014]
    [0015] The present invention will now be described more specifically with reference to the drawings attached only by way of example. [0015] BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS
    [0016] A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein: [0016]
    [0017] FIG. 1 is a block diagram for illustrating the structure of a complicated add/drop cross connection apparatus of an SDH system; and [0017]
    [0018] FIGS. [0018] 2 to 6 are block diagrams for illustrating the add/drop cross connection apparatus of an SDH system according to the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
    [0019] Throughout descriptions in connection with the drawings, same reference numerals are used to represent same functional parts for conveniences sake. In addition, there are omitted detailed descriptions of the conventional parts not required to comprehend the technical concept of the present invention. [0019]
    [0020] Referring to FIG. 1 for illustrating the structure of the add/drop cross connection apparatus of an SDH system, the data supplied from the west or east aggregate unit is divided into the lower and the higher order path data. The lower order path data is TU11 (Tributary Unit 11) or TU12 data processed by a TU pointer while the higher order path data is AU3 (Administration Unit 3) or AU4 data. [0020]
    [0021] The lower order path data supplied from the west or east aggregate unit is matched to the system clock through the multiplex section adaptation (MSA) circuits [0021] 100 or 102, and supplied to the higher order path overhead monitor (HPOM) circuits 104 or 106. The HPOM circuits 104 and 106 respectively monitor the higher order path overheads of the data respectively supplied from the MSA circuits 100 and 102, which are delivered to the higher order path connection (HPC) circuit 108. The HPC circuit 108 performs the cross connection to the data by space switching, and supplies the data to the lower order path data processor 110, which performs the cross connection to the data, aligns the data, and detects and monitors various path overheads. The data processed by the lower order path data processor 110 is delivered to the lower order tributary device.
    [0022] Meanwhile, the higher order path data supplied from the west or east aggregate unit is matched to the system clock through MSA circuits [0022] 100 or 102, and supplied to the HPOM circuits 104 or 106. The HPOM circuits 104 and 106 respectively monitor the higher order path overheads of the data respectively supplied from the MSA circuits 100 and 102, and delivers the data to HPC circuit 108. The HPC circuit 108 performs the cross connection to the data by space switching, and supplies the data to the higher order tributary device, which may be DS3, OC-1, STM-1 or STM-4 equipment.
    [0023] In addition, the lower order path data supplied from the lower order tributary device is subjected through the lower order path data processor [0023] 110 to the cross connection by time switching, and delivered to the HPC circuit 108. The HPC circuit 108 subjects the input data to cross connection by space switching, and delivers the data through the higher order unequipped generators (HUG) 112 or 114 to the west or east aggregate units. Meanwhile, the higher order path data supplied from the higher order tributary device is subjected through the HPC circuit 108 to cross connection by space switching, and delivered through HUGs 112 or 114 to the west or east aggregate units.
    [0024] Hence, such add/drop cross connection apparatus is so complicated as to have one connecting path connecting it to the lower order tributary device and to separately have a second connecting path connecting it to the higher order tributary device. [0024]
    [0025] Referring to FIG. 2, MSA circuits [0025] 200 and 202 respectively match the data received from the west and east aggregate units to the system clock through pointer processing. The data is then delivered to the respective HPOM circuits 204 and 206, which detect and monitor the higher order overheads to be delivered to the HPC circuit 208. The HUG circuits 226 and 228 generate unequipped signals to transfer the data from the HPC circuit 208 to the west or east aggregate unit. The MSA circuits 200 and 202, HPOM circuits 204 and 206, and HUGs 226 and 228 constitute the aggregate unit matching device to provide matching with the aggregate units.
    [0026] The HPC circuit [0026] 208 comprises an HPC device 210 and a selector 212. The HPC device 210 performs cross connection by space switching to the data supplied from the HPOM circuits 204 and 206, lower order path data processor 214, or higher order tributary device. The selector 212 selectively delivers the input data to the lower order path data processor 214, lower order tributary device, high order tributary device, or HPC device 210, which is initially determined by the operator.
    [0027] The lower order path data processor [0027] 214 comprises a higher order path termination (HPT) circuit 216 for processing POH of VC3/VC4, higher order path adaptation (HPA) circuit 218 for aligning data by unit of TU11 or TU12, lower order path overhead monitor (LPOM) circuit 220 for detecting known path overhead bytes (J2 (path trace signal), V5 (BIP-2: a bit interleaved parity operation), etc.), lower order unequipped generator (LUG) 224 for generating unequipped signals by unit of VC11 or VC12, and lower order path connection (LPC) circuit 222 for performing cross connection by time switching to TU11 or TU12 signals.
    [0028] Describing transference of data in the add/drop cross connection apparatus, the tributary device of DS1 (1.544 MBPS) or DS1E (3.152 MBPS) equipment inputs the lower order path data TU11 or TU12 subjected to TU pointer processing to the selector [0028] 212 in order to deliver it to the west aggregate unit. Then, the selector 212, as shown by the dash-dot-dash line in FIG. 2, delivers the input data through LPOM circuit 220 to LPC circuit 222 to LUG 224 to HPT circuit 216 to HPC device 210 to HUG circuit 226 to the west aggregate device.
    [0029] In addition, the tributary device of DS3, OC-1, STM-1 or STM-4 equipment inputs the higher order path data AU3 or AU4 to the selector [0029] 212 to deliver it to the west aggregate unit. Then, the selector 212, as shown by the dash-dash-dash line in FIG. 2, delivers the input data through HPC device 210 to HUG circuit 226 to the west aggregate. Accordingly, selector 212 routes the data based on whether the data is received from a high order tributary device or a low order tributary device. That is, selector 212 is a kind of space switching apparatus for selecting a path of TU11/TU11 (DS1/DS1E Interface Equipment) and VC3/VC4 (DS3/STM-1/STM-4 Interface Equipment). The selector does not discriminates the input date by using an any other specific method but select whether or not the input data is transmitted by way of HPT, HPA in response to a determination of whether the input data is input through the low speed interface apparatus (DS1/DS1E) or the high speed interface apparatus (DS3/STM-1/STM-4).
    [0030] In addition, the tributary device of DS3, OC-1, STM-1 or STM-4 equipment inputs the higher order path data AU3 or AU4 subjected to lower order path cross connection to the selector [0030] 212 to deliver it to the west aggregate unit. Then, the selector 212, as shown by the dash-dot-dash line in FIG. 3, delivers the input data through HPC device 210 to HPT 216 to HPA circuit 218 to LPOM circuit 220 to LPC circuit 222 to LUG circuit 224 to HPT circuit 216 for lower order path crossing, finally through HPC device 210 to HUG circuit 226 and then to the west aggregate unit. The HPC device routes the data according to the known ITU Standard G.783.
    [0031] When the west aggregate unit delivers the lower order path data to the tributary device of DS1 or DS1E equipment, the data input through MSA circuit [0031] 200 to HPOM circuit 204 is delivered through HPC device 210 to selector 212, which, as shown by the dash-dash-dash line in FIG. 4, delivers the data through HPT circuit 216 to HPA circuit 218 to LOPM circuit 220 to LPC circuit 222. Finally, the selector 212 delivers the data received from the LPC circuit 222 to the lower order tributary device.
    [0032] In addition, the west aggregate unit delivers the higher order path data through MSA circuit [0032] 200 to HPOM circuit 204 to HPC device 210 to selector 212 to the higher order tributary device of DS3, OC-1, STM-1 or STM-4 equipment, as shown by te dash-dot-dash line in FIG. 4.
    [0033] When the west aggregate unit sends the higher order path data to the east aggregate unit, the input data, as shown by the dash-dot-dash line in FIG. 5, is delivered through MSA circuit [0033] 200 to HPOM circuit 204 to HPC device 210 to HUG circuit 228 to the east aggregate unit.
    [0034] In addition, when the west aggregate unit sends the lower order path data to the east aggregate unit, the input data, as shown by the dash-dash-dash line in FIG. 5, is delivered through MSA circuit [0034] 200 to HPOM circuit 204 to HPC device 210 to UPT circuit 216 to HPA circuit 218 to LOPM circuit 220 to LPC circuit 222 to LUG circuit 224 to HPT circuit 216 to HPC device 208 and, finally, through HUG circuit 206 to the east aggregate unit.
    [0035] In addition, the lower order path data input from the lower order tributary device to the selector [0035] 212, as shown by the dash-dash-dash line in FIG. 6, is delivered through LPOM circuit 220 to LPC circuit 222 to LUG circuit 224 to the selector 212, returning to the lower order tributary device.
    [0036] In addition, the higher order path data input from the higher order tributary device to the selector [0036] 212, as shown by the dash-dot-dash line in FIG. 6, is delivered through HPC device 210 to the selector 212, returning to the higher order tributary device.
    [0037] Thus, the invention provides the HPC circuit [0037] 208 with the selector 212 so that the lower order data passes the lower order data processor to the tributary devices or aggregate units along the path determined by the user. Hence, the path for the lower order tributary device and the path for the higher order tributary are converged to the path through the selector 212, simplifying the structure of the add/drop cross connection apparatus.
    [0038] While the present invention has been described in connection with specific embodiments accompanied by the attached drawings, it will be readily apparent to those skilled in the art that various changes and modifications may be made thereto without departing the gist of the present invention. [0038]
    权利要求:
    Claims (4)
    [1" id="US-20010007564-A1-CLM-00001] 1. An add/drop cross connection apparatus connected between east and west aggregate units of a synchronous digital hierarchy system, comprising:
    an aggregate unit matching device for providing matching with the aggregate units;
    a higher order path connection circuit for subjecting received higher order path data to cross connection by space switching;
    a lower order path connection circuit for subjecting received lower order path data to cross connection by space switching; and
    a selector for selectively delivering the data supplied from said aggregate units, higher order tributary device, and lower order tributary device, wherein said selector delivers said data to said higher order path connection circuit or lower order path connection circuit according as said data is the higher or lower order path data.
    [2" id="US-20010007564-A1-CLM-00002] 2. The add/drop cross connection apparatus as set forth in
    claim 1 , wherein said higher order path connection circuit is constructed in the same module with said selector.
    [3" id="US-20010007564-A1-CLM-00003] 3. An add/drop cross connection apparatus having multiplex section adaptation circuits for matching high order path data to a system clock, high order path overhead monitor circuits for monitoring higher order path overheads of data respectively supplied from the east and west aggregate units and high order unequipped generators for generating unequipped signals and transferring data to the east and west units, said add/drop cross connection apparatus being connected between east and wet aggregate units of a synchronous digital hierarchy system, said add/drop cross connection apparatus comprising:
    a higher order path connection circuit for subjecting received higher order path data to cross connection by space switching;
    a lower order path connection circuit for subjecting received lower order path data to cross connection by space switching; and
    a selector connected via a single path to a higher order tributary device and a lower order tributary device, wherein said selector selectively delivers higher order path data from said higher order tributary device to said higher order path connection circuit and selectively delivers lower order path data from said lower order tributary device to said lower order path connection circuit based on whether said data is higher order path data or lower order path data.
    [4" id="US-20010007564-A1-CLM-00004] 4. The add/drop cross connection apparatus as set forth in
    claim 3 , wherein said selector receives data from one of said east and west aggregate units via said higher order path connection circuit and selectively provides the received data to said higher order tributary device when said received data is higher order path data and selectively provides the received data to said lower order tributary device via said lower order path connection circuit when said received data is lower order path data.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US6256292B1|1996-07-11|2001-07-03|Nortel Networks Corporation|Self-healing line switched ring for ATM traffic|
    US6011802A|1996-10-22|2000-01-04|Sprint Communications Co. L.P.|Method and system for conversion and transmission of communication signals|
    US6169753B1|1997-10-14|2001-01-02|Fujitsu Limited|Transmission device and signal transmission method in synchronous network|
    US6292485B1|1999-06-03|2001-09-18|Fujitsu Network Communications, Inc.|In-band management control unit software image download|DE10163310A1|2001-12-21|2003-07-17|Infineon Technologies Ag|Multi-protocol transmission method e.g. for data packets in Internet, involves separating header address data from useful data|
    CN100440772C|2004-03-19|2008-12-03|华为技术有限公司|A method for implementing SDH low order time division full cross|
    CN100455034C|2002-02-09|2009-01-21|中兴通讯股份有限公司|Cross cascade system based on add and drop multiplexer in optical synchronous digital transmission system|
    US20090058735A1|2007-08-28|2009-03-05|Hill Robert J|Hybrid slot antennas for handheld electronic devices|JP2897099B2|1993-09-20|1999-05-31|富士通株式会社|Tandem connection maintenance method|
    IT1265424B1|1993-12-22|1996-11-22|Alcatel Italia|METHOD AND CIRUITAL ARRANGEMENT FOR IMPLEMENTING THE FUNCTION OF HPA IN THE SDH EQUIPMENT|
    DE69534182T2|1994-05-17|2006-01-12|Nippon Telegraph And Telephone Corp.|Terminal in SDH networks using error correcting codes|
    KR960027720A|1994-12-23|1996-07-22|양승택|Hybrid network protection / recovery device for synchronous digital line splitter |
    KR0161759B1|1995-12-23|1998-12-01|양승택|Cross connecting apparatus of terminal unit|
    US6094440A|1996-07-05|2000-07-25|Hitachi, Ltd.|Multiplex type transmitting apparatus|KR100399413B1|2001-08-06|2003-09-26|삼성전자주식회사|High Order Connection Device of Synchronous Digital Hierarchy Transfer System|
    EP1641191A1|2004-09-22|2006-03-29|Alcatel|Multi-service switch for integrated transport networks|
    US7583664B2|2004-12-28|2009-09-01|Michael Ho|Techniques for transmitting and receiving traffic over advanced switching compatible switch fabrics|
    法律状态:
    2001-01-10| AS| Assignment|Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PARK, JAI-YOUNG;REEL/FRAME:011439/0146 Effective date: 20010109 |
    2009-02-04| FPAY| Fee payment|Year of fee payment: 4 |
    2013-02-27| FPAY| Fee payment|Year of fee payment: 8 |
    2017-04-14| REMI| Maintenance fee reminder mailed|
    2017-10-02| LAPS| Lapse for failure to pay maintenance fees|Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) |
    2017-10-02| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2017-10-24| FP| Expired due to failure to pay maintenance fee|Effective date: 20170906 |
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000000897A|KR100318904B1|2000-01-10|2000-01-10|Add/drop cross connection apparatus for sdh|
    KRP2000-897||2000-01-10||
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