• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A semiconductor package structure having universal lead frame and heat sink comprises a chip, a lead frame, a heat sink, a bonding wire, and a molding compound. The leads of the lead frame approaches toward the center portion of the lead frame in order to adapt to various sizes of the chip. The heat sink is mounted on and connected to the leads of the lead frame, and the periphery of the heat sink overlaps the front end of the leads wherein the dimension of the heat sink is not smaller than the size of the chip. The chip is disposed on the heat sink that is also functioned as die pad. The chip is electrically connected to the leads by a bonding wire that is designed to be the shortest. An “electrically insulative, and thermally conductive layer” is employed for bonding the heat sink to the lead frame. A molding compound is employed to encapsulate the chip, a portion or the whole piece of the heat sink, the leads of the lead frame, and the bonding wires that are electrically connected between the chip and the leads.
    公开号:US20010003372A1
    申请号:US09/490,724
    申请日:2000-01-25
    公开日:2001-06-14
    发明作者:Chien-Ping Huang；Wei-Chen Tseng
    申请人:Siliconware Precision Industries Co Ltd；
    IPC主号:H01L24-48
    专利说明:
    [0001] This application claims the priority benefit of Taiwan application serial no. 88119455, filed Nov. 8, 1999. [0001] BACKGROUND OF THE INVENTION
    [0002] 1. Field of the Invention [0002]
    [0003] This invention relates to semiconductor package structure, and more particularly to a semiconductor package structure having universal lead frame and heat sink. [0003]
    [0004] 2. Description of Related Art [0004]
    [0005] In the semiconductor industry, the semiconductor packaging, being the last stage of manufacturing process of integrated circuit products, is used for providing a medium of electrical connection between a chip and a printed circuit board (PCB) or other appropriate devices and is also used to protect the chip. Generally, the integrated circuit is encapsulated in a package, then the package is bonded to the printed circuit board or a substrate. [0005]
    [0006] It is the demand of the market makes the semiconductor industry grow very fast, and the level of integration of integrated circuit is getting higher than ever. Consequently, the number of input/output port is increasing, and the package is heading for developing the one with high density. Therefore, the design and fabrication of a die pad used for mounting the chip while performing packaging, and of a printed circuit board or a substrate such as a circuit carrier for the connection of electronic parts needs to be improved. As the speed of calculating process is getting higher and higher, the power consumed and the heat generated is also getting higher and higher. The heat generated after the chip is packaged is not easy to spread away. The conventional way of heat dissipation is to let the heat dissipate by means of the heat conduction through the molding compound, but the molding compound universally used is not a good thermally conductive material. For all of the above-mentioned reasons, the heat-dissipating effect of heat dissipation method provided by the conventional package is very limited. [0006]
    [0007] FIG. 1A is a cross-sectional view of a semiconductor package according to the prior art. As shown in FIG. 1A, a semiconductor package is constructed on a leaf frame [0007] 106. The package comprises a die pad 102 having a top surface 104, and a plurality of leads 108. The leads 108 are attached on the top surface 104 and are disposed at the periphery of the die pad 102. A chip 100 a mounted on the top surface 104 of the die pad 102 is electrically connected to the leads 108 by bonding wires 110 a.
    [0008] As the manufacturing technology of the semiconductor has advanced to 0.18 Micron of wire width or even smaller, there are a lot of breakthrough on increasing the integration. Accordingly, the chip size is diminished, and the electronic products are in the trend of “Light, Thin, Short, and Small”. However, as the chip is shrunk, under the same condition of using the same lead frame, the distance between the chip and the leads of the lead frame will be increased. [0008]
    [0009] Similar to FIG. 1A, shown in FIG. 1B is a schematic cross-sectional view of the semiconductor according to the prior art when the chip is shrunk. As shown in FIG. 1B, a chip [0009] 100 b mounted on the top surface 104 of the die pad 102 is electrically connected to the leads 108 by bonding wires 110 b. As compare with the package shown in FIG. 1A, when the chip is shrunk from 100 a to 100 b while all the other elements of the package keep the same size and same disposition, the required bonding wires become longer from 100 a to 100 b. This is due to the fact that the space between the chip 100 b and the leads 108 in FIG. 1B is larger than the space between the chip 100 a and the leads 108 in FIG. 1A. The length increase of bonding wires not only increases the manufacturing cost but also affects the electrical performance of the package. Moreover, the encapsulating process can cause the “Wire Sweep” or even the “Wire Cross” of the relatively long bonding wire that results in unnecessary “Short Circuit”.
    [0010] However, one way to keep the length of the bonding wires unchanged when the chip is shrunk from [0010] 100 a to 100 b is to make the leads approach toward the center of the lead frame, in other word, to make the leads relatively longer. Accordingly, the lead frame needs to be redesigned and remanufactured which will result in the increase in manufacturing cost too. In other word, the original lead frame can not be used when the size of the chip is changed (either shrunk or enlarged). SUMMARY OF THE INVENTION
    [0011] Therefore, it is the objective of the present invention to provide a semiconductor package structure having universal lead frame and heat sink to accommodate different sizes of the chip. Whenever there is a change in the dimension of the chip, the packaging process can be performed without making any changes in the design and manufacturing of new lead frames, in other word, the original lead frames still hold good. Moreover, the bonding wire electrically connecting the chip and the leads of the lead frame is the shortest one, thereby, it can enhance the electrical performance and the reliability of the overall package. In additions, there is a heat sink in the package that can dissipate the heat generated, and the heat sink is employed to substitute for the die pad for chip mounting. Furthermore, the heat sink can be exposed to directly contact the outside elements to facilitate the package to transfer the heat out, thereby, two kinds of this type of packages are available, i.e., Die pad Heat Sink (DPH) structures and Exposed Die Pad Heat Sinks (EDPH). [0011]
    [0012] In order to attain the foregoing and other objectives, the present invention provides a semiconductor package structure having universal lead frame and heat sink. The semiconductor package structure comprises a chip, a lead frame, a heat sink, a bonding wire, and a molding compound. The leads of the lead frame approaches toward the center portion of the lead frame in order to adapt to various sizes of the chip. The heat sink is mounted on and connected to the leads of the lead frame, and the periphery of the heat sink overlaps the front end of the leads wherein the dimension of the heat sink is not smaller than the size of the chip. The chip is mounted on the heat sink that is also functioned as die pad. The chip is electrically connected to the leads by a bonding wire that is designed to be the shortest. An “electrically insulative, and thermally conductive” layer is employed for bonding the heat sink to the lead frame. A molding compound is employed to encapsulate the chip, a portion or the whole piece of the heat sink, the leads of the lead frame. [0012] BRIEF DESCRIPTION OF DRAWINGS
    [0013] The foregoing and other objectives, characteristics, and advantages of the present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings as follows: [0013]
    [0014] FIG. 1A is a schematic cross-sectional view of a semiconductor package according to the prior art. [0014]
    [0015] FIG. 1B is a schematic cross-sectional view of the semiconductor according to the prior art when the chip is shrunk. [0015]
    [0016] FIG. 2A is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the first preferred embodiment according to the present invention. [0016]
    [0017] FIG. 2B is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the first preferred embodiment when the chip is shrunk according to the present invention. [0017]
    [0018] FIG. 3A is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the second preferred embodiment according to the present invention. [0018]
    [0019] FIG. 3B is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink and having the EDPH structure of the second preferred embodiment according to the present invention. [0019]
    [0020] FIG. 3C is a schematic cross-sectional view of another semiconductor package having universal lead frame and heat sink, and having the DPH and heat spreader structure of the second preferred embodiment according to the present invention. [0020]
    [0021] FIG. 4 is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the third preferred embodiment according to the present invention. [0021] DETAILED DESCRIPTION OF PREFERRED EMBODIMENT The First Preferred Embodiment
    [0022] Shown in FIG. 2A is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the first preferred embodiment according to the present invention. As shown in FIG. 2A, a semiconductor package [0022] 200 a is constructed on a lead frame 210. The package 200 a comprises a heat sink 204 a and a plurality of leads 212. The heat sink 204 a that is functioned as a die pad has a first surface 206 a and a second surface 208 a. The leads 212 are designed to be long enough to be approached to the center of the lead frame 210 in order to be attached on by the heat sink 204 a. Thus, the heat sink 204 a can have its second surface 208 a mounted at the inner periphery of the lead frame 210 and on the top surface of the leads 212 by an adhesive 218 a. Preferably, the material of the heat sink 204 a is aluminum or copper while that of the adhesive 218 a is “an electrically insulative and thermally conductive paste”.
    [0023] A chip [0023] 202 a that is mounted on the heat sink 204 a is electrically connected to the leads 212 with the bonding wires 214 a by Wire Bonding method for instance. Preferably, the material of the bonding wires 214 a is gold wire, aluminum wire etc. A molding compound 220 is employed to encapsulate the chip 202 a, the heat sink 204 a, the bonding wires 214 a and the leads 212 to accomplish a package 200 a. The preferred material for the molding compound 220 is an electrically insulative molding compound such as Resin, Epoxy etc.
    [0024] As mentioned above, the heat sink [0024] 204 a in the first embodiment of the present invention is functioned as a die pad, in other word, the package 200 a is a kind of “Die Pad Heat Sink” (DPH) structure. The heat generated in the chip 202 a is dissipated through a path of the heat sink 204 a, the adhesive 218 a, and the leads 212 of the lead frame 210 to be transferred out of the package 200 a.
    [0025] Normally, the dimension of the die pad, which is the heat sink [0025] 204 a in the present invention, is designed to be larger than the dimension of the chip 202 a. Noted that the bonding wire 214 a is designed to be the shortest one connected between the chip 202 a and the lead 212. To achieve this object, the lead 212 is disposed in a way such that the leads 212 is approached sufficiently toward the center of the lead frame 210 to be overlapped with the length of the chip 202 a. Moreover, the leads 212 and the chip 202 a are on the distinct sides of the heat sink 204 a to enable this overlapping.
    [0026] Shown in FIG. 2B is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the first preferred embodiment when the dimension of the chip is shrunk according to the present invention. As shown in FIG. 2B, a semiconductor package [0026] 200 b is constructed on a lead frame 210. The package 200 b comprises a heat sink 204 b and a plurality of leads 212. The heat sink 204 b that is functioned as a die pad has a first surface 206 b and a second surface 208 b. Shown in FIG. 2B is a package structure 200 b similar to the package structure 200 a of FIG. 2A. When the dimension of the chip 202 b is shrunk, the dimension of the heat sink 204 b is shrunk accordingly but the dimension of the heat sink 204 b still larger than that of the chip 202 b. The heat sink 204 b has its second surface 208 b mounted at the inner periphery of the lead frame 210 and on the top surface of the leads 212 by an adhesive 218 b. Preferably, the material of the heat sink 204 b is aluminum or copper while that of the adhesive 218 b is “an electrically insulative and thermally conductive paste”.
    [0027] A chip [0027] 202 b that is mounted on the heat sink 204 b is electrically connected to the leads 212 with the bonding wires 214 b by Wire Bonding method, for instance. Preferably, the material of the bonding wires 214 b is gold wire, aluminum wire etc. A molding compound 220 is employed to encapsulate the chip 202 b, the heat sink 204 b, the bonding wires 214 b and the leads 212 to accomplish a package 200 b. The preferred material for the molding compound 220 is an electrically insulative molding compound such as Resin, Epoxy etc.
    [0028] Moreover, the length of the lead frame [0028] 210 is the same as that of the lead frame 210 shown in FIG. 2A, and the length of the bonding wires 214 b is also the same as that of the bonding wires 214 a in FIG. 2A. What is different is the overlapped length, that is, the overlapped length between the heat sink 204 b and the lead frame 210 in FIG. 2B is smaller than the overlapped length between the heat sink 204 a and the lead frame 210 in FIG. 2A. In other word, when the dimension of the chip is shrunk, all one has to do is use a relatively small dimension of the heat sink accordingly while still use the same lead frame and the same bonding wires. The Second Preferred Embodiment
    [0029] Shown in FIG. 3A is a schematic cross-sectional view of a semiconductor package having universal lead frame and heat sink of the second preferred embodiment according to the present invention. As shown in FIG. 3A, a semiconductor package [0029] 300 a is constructed on a lead frame 312. The package 300 a comprises a heat sink 304 a and a plurality of leads 316. The heat sink 304 a that is functioned as a die pad has a first surface 306 and a second surface 308. The heat sink 304 a also has a projection 310 a added to the center portion of its second surface 308 and disposed at the opening center region of the lead frame 312. The leads 314 are designed to be long enough to be approached to the center of the lead frame 312 in order to be attached on by the heat sink 304 a. Thus, the heat sink 304 a can have its second surface 308 mounted at the inner periphery of the lead frame 312 and on the top surface of the leads 314 by an adhesive 318. Preferably, the material of the heat sink 304 a is aluminum or copper while that of the adhesive 318 is “an electrically insulative and thermally conductive paste”.
    [0030] A chip [0030] 302 that is mounted on the heat sink 304 a is electrically connected to the leads 314 by the bonding wires 316 by Wire Bonding method for instance. Preferably, the material of the bonding wires 316 is gold wire, aluminum wire etc. A molding compound 320 is employed to encapsulate the chip 302, the heat sink 304 a, the bonding wires 316 and the leads 314 to accomplish a package 300 a. Since the package 300 a contains a heat sink 304 a that is functioned as a die pad as mentioned above, thereby, the package 300 a is a kind of Die Pad Heat Sink (DPH) structure. The preferred material for the molding compound 320 is an electrically insulative molding compound such as Resin, Epoxy etc.
    [0031] The heat generated in the chip [0031] 302 is dissipated through a path of the heat sink 304 a, the adhesive 318, and the leads 314 of the lead frame 312 to be transferred out of the package 300 a. Moreover, the leads 314 and the chip 302 are on the opposite sides of the heat sink 304 a to enable the overlapping between the leads 314 and the chip 302. This overlapping will enable the design of the bonding wires 316 to be the shortest one connected between the chip 302 and the lead 314 as mentioned before.
    [0032] As mentioned above, the heat sink [0032] 304 a functioned as a die pad has a projection structure 310 a added. The heat sink 304 a together with the projection 310 a can increase the heat-dissipating area so as to provide a relatively better heat-dissipating effect. Moreover, the projection can be used to balance the mold flow during the encapsulating process, thus the packaging reliability can be enhanced by the use of “balanced mold flow” method.
    [0033] FIG. 3B is a schematic cross-sectional view of another semiconductor package having universal lead frame and heat sink and having the EDPH structure of the second preferred embodiment according to the present invention. The package structure [0033] 300 b in FIG. 3B is exactly the same as a package structure 300 a in FIG. 3A, and same element numbers are used except that the projection 310 b added is exposed. An “exposed projection” 310 b is added to the heat sink 304 b at the center portion of its second surface 308 and is disposed at the opening center region of the lead frame 312 similar to the projection 310 a in FIG. 3A. The difference is that the projection 310 b as shown in FIG. 3B has its bottom surface expose to the bottom surface of the package 300 b, thereby, the package 300 b is a kind of “Exposed Die Pad Heat Sink” (EDPH) structure. As compare with the package structure 300 a in FIG. 3A, an extra heat-dissipating path is added to the package structure 300 b in FIG. 3B. That is, a path from the chip 302 through the heat sink 304 b, and the “exposed projection 310 b”. Consequently, the heat-dissipating effect of the package 300 b can be enhanced further.
    [0034] FIG. 3C is a schematic cross-sectional view of one other semiconductor package having universal lead frame and heat sink and having the EDPH structure of the second preferred embodiment according to the present invention. The package structure [0034] 300 c in FIG. 3C is exactly the same as a package structure 300 a in FIG. 3A, and same element numbers are used except that a heat spreader 322 which has its bottom surface exposed is added to the bottom surface of the projection 310 a. As shown in FIG. 3C, an “exposed heat spreader” 322 is added to the projection 310 a at the opening center region of the lead frame 312. The heat spreader 322 has its bottom surface exposed at the bottom surface of the package 300 c. An extra heat-dissipating path from the chip 302 through the heat sink 304 a and the heat spreader 322 is then created. This heat spreader has a much larger area exposed, thereby, the heat-dissipating effect of the package 300 c will be significantly improved. The Third Preferred Embodiment
    [0035] FIG. 4 is a schematic cross-sectional view of one other semiconductor package having universal lead frame and heat sink of the third preferred embodiment according to the present invention. This package structure is similar to the package structure of the first embodiment shown in FIG. 2. As shown in FIG. 4, a semiconductor package [0035] 400 is constructed on a lead frame 412. The package 400 comprises a heat sink 404 and a plurality of leads 414. The heat sink 404 that is functioned as a die pad has a first surface 406 and a second surface 408. The leads 414 are designed to be long enough to be approached to the center of the lead frame 412 in order to be attached on by the heat sink 404. Thus, the heat sink 404 can have its second surface 408 mounted at the inner periphery of the lead frame 412 and on the top surface of the leads 414 by an adhesive 418. Preferably, the material of the heat sink 404 is aluminum or copper while that of the adhesive 418 is an “electrically insulative and thermally conductive paste”.
    [0036] A chip [0036] 402 that is mounted on the heat sink 404 is electrically connected to the leads 414 with a plurality of bonding wires 416 by Wire Bonding method for instance. Preferably, the material of the bonding wires 416 is gold wire, aluminum wire etc. A molding compound 420 is employed to encapsulate the chip 402, the heat sink 404, the bonding wires 416 and the leads 414 to accomplish a package 400. The preferred material for the molding compound 420 is an electrically insulative molding compound such as Resin, Epoxy etc.
    [0037] As one can see both in FIG. 2A and FIG. 2B in the first embodiment of the present invention, when the chip is shrunk from [0037] 202 a to 202 b, the dimension of the heat sink is decreased from 204 a to 204 b accordingly. This is for the sake of keeping the length of the bonding wires 214 b and 214 a unchanged instead of increasing the wire length. In other word, if the heat sink 204 b keeps the same dimension as that of the heat sink 204 a, the bonding wires 214 b have to be increased to be greater than those of the bonding wires 214 a. This will enable the bonding wires 214 b to electrically connect the chip 202 b to the leads 212. Consequently, the manufacturing cost will be high since the bonding wire is rather expensive.
    [0038] As the heat sink is shrunk as shown in FIG. 2B, the heat-dissipating area become relatively smaller. In this situation, the disadvantage of decreasing the heat-dissipating area of the heat sink is traded for the advantage of saving the cost of not using a relatively long bonding wire. [0038]
    [0039] However, there is a way to cover both of the above-mentioned advantages. This is shown in FIG. 4 in the present embodiment of the present invention. A plurality of via holes [0039] 410 is disposed on the perimeter of the heat sink 404 at the locations where the bonding wires needed to be penetrated through for electrically connecting the chip 402 to the leads 414. Therefore, when the dimension of the chip is decreased, the bonding wires 316 electrically connected between the chip 302 and the lead 314 are penetrated through the via holes 410 without making the dimension of the heat sink 404 shorter while the length of bonding wires can still keep the same.
    [0040] Likewise, an adhesive [0040] 418 is employed to bond the second surface 408 of the heat sink 404 to the leads 414. The preferred adhesive 418 is an “electrically insulative, and thermally conductive paste” etc. Besides, the chip 402, the heat sink 404, the leads 414 of the lead frame 412, bonding wire 416, and a portion of the lead frame 412 are all encapsulated by a molding compound 420.
    [0041] Therefore, the package of the present invention can make the length of the bonding wires the shortest one. Besides, when the dimension of the chip is shrunk, the same structural members, such as heat sink and lead frame, can still be used by changing only the location of the “via holes” on the heat sink. [0041]
    [0042] To summarize the foregoing illustration disclosed by preferred embodiments of the present invention, the semiconductor package of the present invention comprise the following advantages: [0042]
    [0043] 1. When the dimension of the chip is changed, by employing the semiconductor package having universal lead frame and heat sink of the present invention, the original lead frame can be used for performing packaging without redesign and remanufacturing new lead frames. All one has to do is to change the dimension of the heat sink. In this way, one can keep the length of the bonding wires unchanged and the shortest ones without shortening the dimension of the heat sink so as to enhance the electrical performance and reliability of the overall package. [0043]
    [0044] 2. The semiconductor package having universal lead frame and heat sink of the present invention has either a DPH structure or a EDPH structure. Therefore, the heat generated by the chip can be transferred out of the package through an effective heat path. The heat path is passing through the heat sink functioned as die pad, the thermal conductive paste, the lead frame, and heat spreader etc. in order to enhance the heat-dissipating efficiency and the reliability of the device, and to prolong the service life of the device. [0044]
    [0045] The invention has been described using an exemplary preferred embodiment. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. [0045]
    权利要求:
    Claims (13)
    [1" id="US-20010003372-A1-CLM-00001] 1. A semiconductor package comprising:
    a lead frame, having a plurality of leads wherein a plurality of leads approaches toward a central portion of the lead frame;
    a heat sink, having a first surface and a second surface wherein the heat sink has its second surface mounted on the inner periphery of the lead frame;
    a chip, mounted on the first surface of the sink wherein the area of the first surface is not small than the area of the chip;
    a plurality of bonding wires, electrically connected to the chip and the leads respectively; and
    a molding compound, encapsulating the chip, the bonding wires, the heat sink, and the leads.
    [2" id="US-20010003372-A1-CLM-00002] 2. The semiconductor package of
    claim 1 further comprising an adhesive used for bonding the heat sink and the lead frame.
    [3" id="US-20010003372-A1-CLM-00003] 3. The semiconductor package of
    claim 2 wherein the adhesive comprises an electrically insulative, and thermally conductive paste.
    [4" id="US-20010003372-A1-CLM-00004] 4. The semiconductor package of
    claim 1 wherein the heat sink further includes a projection connected to the second surface of the heat sink.
    [5" id="US-20010003372-A1-CLM-00005] 5. The semiconductor package of
    claim 4 wherein the projection is encapsulated by the molding compound.
    [6" id="US-20010003372-A1-CLM-00006] 6. The semiconductor package of
    claim 4 further comprising a heat spreader connected to the projection.
    [7" id="US-20010003372-A1-CLM-00007] 7. The semiconductor package of
    claim 6 wherein the molding compound encapsulates the chips, the bonding wires, the sink, and the leads while exposes a portion of the heat sink.
    [8" id="US-20010003372-A1-CLM-00008] 8. The semiconductor package of
    claim 4 wherein the molding compound encapsulates the chips, the bonding wires, the sink, and the leads while exposes a portion of the surface of the projection.
    [9" id="US-20010003372-A1-CLM-00009] 9. The semiconductor package of
    claim 1 wherein the heat sink also has a plurality of via holes disposed on the periphery of the chip, and the bonding wires are penetrated through the via holes to electrically connect the chip to the leads.
    [10" id="US-20010003372-A1-CLM-00010] 10. A semiconductor package comprising:
    a lead frame, having a plurality of leads wherein a plurality of leads approaches toward a central portion of the lead frame;
    an “electrically insulative, and thermally conductive layer” bonded at the inner periphery of the lead frame, and on the surface of the leads;
    a heat sink, having a first surface, a second surface, and a projection, wherein the second surface has the projection attached, and the heat sink is bonded to the “electrically insulative, and thermally conductive layer”, and the perimeter of the second surface is connected to and overlapped with the front end of the leads through the “electrically insulative, and thermally conductive layer”;
    a chip, mounted on the first surface wherein the area of the first surface is not small than the area of the chip;
    a plurality of bonding wires, electrically connected to the chip and the leads respectively; and
    a molding compound, encapsulating the chip, the bonding wires, the heat sink, the leads, and the projection.
    [11" id="US-20010003372-A1-CLM-00011] 11. A semiconductor package comprising:
    a lead frame, having a plurality of leads wherein a plurality of leads approaches toward a central portion of the lead frame;
    an “electrically insulative, and thermally conductive layer” disposed on the lead frame, and positioned on the surface of the leads;
    a heat sink, having a first surface, a second surface, and a projection, wherein the second surface has the projection attached, and the heat sink is mounted on the “electrically insulative, and thermally conductive layer”, and the periphery of the second surface is connected to and overlapped with the front end of the leads through the “electrically insulative, and thermally conductive layer”;
    a chip, mounted on the first surface wherein the area of the first surface is not small than that of the chip;
    a plurality of bonding wires, electrically connected to the chip and the leads respectively; and
    a molding compound, encapsulating the chip, the bonding wires, the heat sink, the leads, and exposing a portion of the surface of the projection.
    [12" id="US-20010003372-A1-CLM-00012] 12. A semiconductor package comprising:
    a lead frame, having a plurality of leads wherein a plurality of leads approaches toward a central portion of the lead frame;
    an “electrically insulative, and thermally conductive layer” disposed on the lead frame, and positioned on the surface of the leads;
    a heat sink, having a first surface, a second surface, and a projection, wherein the second surface has the projection attached, and the heat sink is mounted on the “electrically insulative, and thermally conductive layer”, and perimeter of the second surface is connected to and overlapped with the front end of the leads through the “electrically insulative, and thermally conductive layer”;
    a chip, disposed on the first surface wherein the area of the first surface is not small than the area of the chip;
    a plurality of bonding wires, electrically connected to the chip and the leads respectively; and
    a molding compound, encapsulating the chip, the bonding wires, the heat sink, the leads, and exposing a portion of the surface of the heat spreader.
    [13" id="US-20010003372-A1-CLM-00013] 13. A semiconductor package comprising:
    a lead frame, having a plurality of leads wherein a plurality of leads approaches a central portion of the lead frame;
    an “electrically insulative, and thermally conductive layer” disposed on the lead frame, and positioned on the surface of the leads;
    a heat sink, having a first surface, a second surface, and a projection, wherein the second surface has the projection attached, and the heat sink is disposed on the “electrically insulative, and thermally conductive layer”, and the perimeter of the second surface is connected to and overlapped with the front end of the leads through the “electrically insulative, and thermally conductive layer”;
    a chip, disposed on the first surface wherein the area of the first surface is not small than that of the chip;
    a plurality of bonding wires, electrically connected to the chip and the leads respectively; and
    a molding compound, encapsulating the chip, the bonding wires, the heat sink, the leads.
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    引用文献:
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    法律状态:
    2000-01-25| AS| Assignment|Owner name: SILICONWARE PRECISION INDUSTRIES CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, CHIEN-PING;TSENG, WEI-CHEN;REEL/FRAME:010554/0522 Effective date: 19991215 |
    2001-07-19| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2004-12-09| FPAY| Fee payment|Year of fee payment: 4 |
    2008-12-07| FPAY| Fee payment|Year of fee payment: 8 |
    2013-01-08| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    TW88119455||1999-11-08||
    TW088119455A|TW546806B|1999-11-08|1999-11-08|Semiconductor package with common lead frame and heat sink|
    TW088119455||1999-11-08||
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