• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method for fabricating a capacitor of a semiconductor device is provided. In the capacitor fabricating method, the step of forming a lower electrode by using gas including chlorine is included after the step of forming hemispherical grained silicon (HSG-Si) seeds. Also, after the step of selectively growing only HSG-Si seeds formed on the lower electrode, the step of removing the HSG-Si seeds formed on an insulation layer pattern through an etching process using a gas including chlorine is included. Thus, the surface area of the lower electrode is increased, so that capacitance is increased. Also, an electrical short between the lower electrodes of each adjacent capacitor can be prevented without decreasing capacitance.
    公开号:US20010003065A1
    申请号:US09/742,650
    申请日:2000-12-21
    公开日:2001-06-07
    发明作者:Young-sun Kim；Young-wook Park
    申请人:Kim Young-Sun；Park Young-Wook；
    IPC主号:H01L28-84
    专利说明:
    [0001] The present invention relates to a capacitor fabricating method of a semiconductor device, and more particularly, to a capacitor fabricating method of a semiconductor device in which a ridge and valley-type lower electrode is formed using a hemispherical grained silicon (HSG-Si). [0001]
    [0002] A decrease in cell capacitance according to the decrease of cell memory area is an obstacle to the increase in stability of a dynamic random access memory (DRAM). The decrease in cell capacitance lowers the reading and writting abilities of the memory cell, increases the soft error ratio, and further disturbs the operation of the device at lower voltages. Thus, for high integration of the semiconductor memory device, the decrease in cell capacitance should be overcome. [0002]
    [0003] Generally, in 64Mb DRAMs having a memory cell area of approximately 1.5 μm[0003] 2, it is difficult to provide sufficient capacitance even when a dielectric substance such as Ta2O5 is used in a general stacked-type capacitor having a two-dimensional structure. Thus, recently, a capacitor having a three-dimensional structure has been suggested to increase cell capacitance, such as a lower electrode having a fin structure (Fujitsu), a lower electrode having a box structure (Toshiba), a lower electrode having a cylindrical structure (Mitsubishi), etc.
    [0004] However, in the case of the capacitor having a three-dimensional structure, the fabrication process thereof is complicated and a defect may occur in the fabrication process, thus applying such structure is difficult. Also, research into a high dielectric film has been conducted in order to increase the capacitance of the capacitor, however, the high dielectric film has many problems in application. Thus, research into a method for fabricating a ridge and valley-type lower electrode, in which area is locally increased, has been performed to increase capacitance. [0004]
    [0005] In one method of fabricating the ridge and valley-type lower electrode, multiple bumps of HSG-Si are formed on the surface of the lower electrode to form ridges and valleys in the surface thereof, thereby increasing the surface area of the lower electrode. [0005]
    [0006] As a method for forming HSG-Si on the surface of the lower electrode, there are following methods: 1) a chemical vapor deposition method in which silicon is deposited at a temperature where phase transformation occurs from amorphous silicon to polysilicon, 2) a method for annealing amorphous silicon without native oxide layer in a vacuum, and 3) a seeding method in which HSG-Si seeds are formed by a low pressure chemical deposition (LPCVD) method using SiH[0006] 4 or Si2H6 gas, or by irradiating SiH4 or Si2H6 beam on the amorphous silicon, and then the formed seeds are grown.
    [0007] It has been reported that the surface area of the lower electrode is effectively increased when the ridge and valley-type silicon lower electrode is formed using the seeding method in an article by H. Watanabe et al., [0007] A New Cylindrical Capacitor Using HSG-Si for 256Mb DRAMs, IEDM '92, pp. 259-262.
    [0008] FIGS. 1 through 3 are cross-sectional diagrams for illustrating a conventional method for fabricating a capacitor of a semiconductor device. [0008]
    [0009] FIG. 1 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern [0009] 20 and a lower electrode 40. First, an insulation layer such as a silicon oxide layer is formed on a semiconductor substrate 10 and then the insulation layer is patterned by a photolithography process to form the insulation pattern 20 having a contact hole which exposes a predetermined area of the semiconductor substrate 10.
    [0010] Subsequently, after an amorphous silicon layer doped with impurity is formed on the entire surface of the substrate having the insulation later pattern [0010] 20 to fill the contact hole, the resultant structure is patterned by a general method. As a result, the lower electrode 40 having a cylindrical structure is formed on a predetermined area of the insulation layer pattern 20, which is connected to the exposed semiconductor substrate via the contact hole.
    [0011] FIG. 2 is a cross-sectional diagram for illustrating the step of forming HSG-Si seeds [0011] 50 a and 50 b, wherein the HSG-Si seeds are formed on the lower electrode 40 by a low-pressure chemical deposition (LPCVD) method using a silicon source gas. Here, since the HSG-Si seeds are formed first at a portion of the lower electrode 40 with high surface energy, the HSG-Si seeds are scattered on the surface of the lower electrode 40. Also, as the silicon source gas, SiH4, Si2H6, Si3H8, SiH2Cl2 or SiH2Cl2 is used.
    [0012] Of course, the HSG-Si seeds may be formed on the lower electrode [0012] 40 by irradiating the silicon source gas as a beam on the entire surface of the substrate having the lower electrode 40.
    [0013] Since the selectiveness of the HSG-Si seed formation process is very low, the HSG-Si seeds are formed on the insulation layer pattern [0013] 20 during the step of forming HSG-Si seeds on the lower electrode 40. Hereinafter, HSG-Si seeds formed on the lower electrode 40 will be referred to as first HSG-Si seeds 50 a, and HSG-Si seeds formed on the insulation layer pattern 20 will be referred to as second HSG-Si seeds 50 b, respectively.
    [0014] FIG. 3 is a cross-sectional diagram for illustrating the step of forming HSG-Si [0014] 50 c. Here, the substrate having the first and second silicon seeds 50 a and 50 b is heated to selectively grow the first HSG-Si seeds 50 a, thereby forming the HSG-Si 50 c on the lower electrode 40. As a result, the surface area of the lower electrode 40 is increased. Here, since the first HSG-Si seeds 50 a grow by receiving silicon from the lower electrode 40 differently from the second HSG-Si seeds 50 b which cannot receive silicon required for growth, only the first HSG-Si seeds 50 a are grown.
    [0015] Here, the second HSG-Si seeds [0015] 50 b remain on the insulation layer pattern 20, so that the lower electrode 40 and a lower electrode of a capacitor adjacent thereto are electrically shorted, causing mis-operation of the semiconductor device. Also, since an increase in area at the lower electrode 40 depends only on the growth of the first HSG-Si seeds 50 a, it is difficult to obtain sufficient cell capacitance for ensuring reliable operation of the semiconductor device.
    [0016] Further, a dielectric layer and an upper electrode are formed in sequence on the entire surface of the substrate having the HSG-Si [0016] 50 c to complete a capacitor, wherein this step is not shown.
    [0017] As described above, in the conventional method for fabricating a capacitor of a semiconductor device, the second HSG-Si seeds [0017] 50 b remain on the insulation pattern 20, so that the lower electrodes of each adjacent capacitors are susceptible to electrical shorts. Also, since the increase in area of the lower electrode 40 depends only on the growth of the first HSG-Si seeds 50 a, there are difficulties in the ensuring sufficient cell capacitance. Thus, reliability of the semiconductor device is decreased. SUMMARY OF THE INVENTION
    [0018] To overcome the above problems, it is an object of the present invention to provide a method for fabricating a capacitor of a semiconductor device, which can improve reliability of the semiconductor device. [0018]
    [0019] According to the first embodiment for achieving the object, there is provided a method for forming a capacitor of a semiconductor device comprising the steps of: (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate; (b) forming a lower electrode on a predetermined area of the insulation layer pattern, the lower electrode is connected to the exposed semiconductor substrate via the contact hole; (c) forming HSG-Si seeds on the surfaces of the lower electrode and the insulation layer pattern; (d) etching the surface of the lower electrode by using the HSG-Si seeds formed on the surface of the lower electrode as an etching mask to form a depressed portion on the surface of the lower electrode, resulting in the formation of a modified lower electrode; and (e) growing the HSG-Si seeds formed on the surface of the lower electrode to form multiple bumps of HSG-Si. [0019]
    [0020] Here, the step (d) of etching the surface of the lower electrode is performed using a gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl[0020] 2, BCl3, ClF3 and HCl.
    [0021] Also, preferably, the step (d) of etching the surface of the lower electrode is performed by anisotropically etching while varying the incident angle of etching gas. [0021]
    [0022] Preferably, the step (e) of growing the HSG-Si seeds is performed by heating the substrate having the HSG-Si seeds, and the heating is performed at 560˜630°C. [0022]
    [0023] Also, it is preferably that the method for forming a capacitor of a semiconductor device further comprises the step of removing the HSG-Si seeds formed on the surface of the insulation layer pattern by an etching after the step (e). Here, the step of removing HSG-Si seeds formed on the surface of the insulation layer pattern by an etching is performed by using the gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl[0023] 2, BCl3, ClF3 and HCl.
    [0024] According to the second embodiment for achieving the object, there is provided a method for forming a capacitor of a semiconductor device comprising the steps of: (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate; (b) forming a lower electrode on a predetermined area of the insulation layer pattern, the lower electrode is connected to the exposed semiconductor substrate via the contact hole; (c) forming HSG-Si seeds on the surfaces of the lower electrode and the insulation layer pattern; (d) selectively growing the HSG-Si seeds formed on the surface of the lower electrode to form multiple bumps of HSG-Si on the surface of the lower electrode; (e) removing the HSG-Si seeds formed on the surface of the insulation layer pattern through an etching process. [0024]
    [0025] Also, the step (c) of forming the HSG-Si seeds is performed by a chemical vapor deposition (CVD) method using a silicon source gas. [0025]
    [0026] It is preferably that the step (d) of forming the HSG-Si is performed by heating the substrate having the HSG-Si seeds, and the heating is performed at 560˜630°C. [0026]
    [0027] In addition, the step of removing the HSG-Si seeds formed on the surface of the insulation layer pattern by an etching is performed by using a gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl[0027] 2, BCl3, ClF3 and HCl.
    [0028] In the method for fabricating a capacitor of a semiconductor device according to the present invention, the surface area of the lower electrode is increased, so that a high cell capacitance can be ensured compared to that of the conventional device. Also, an electrical short between the lower electrodes of adjacent capacitors can be prevented without decreasing capacitance. [0028] BRIEF DESCRIPTION OF THE DRAWINGS
    [0029] The above object and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: [0029]
    [0030] FIGS. 1 through 3 are diagrams illustrating a conventional method for fabricating a capacitor of a semiconductor device; [0030]
    [0031] FIGS. 4 through 7 are diagrams illustrating a method for fabricating a capacitor of a semiconductor device according to a preferred embodiment of the present invention; and [0031]
    [0032] FIGS. 8 through 11 are diagrams illustrating a method for fabricating a capacitor of a semiconductor device according to another preferred embodiment of the present invention. [0032] DETAILED DESCRIPTION OF THE INVENTION Embodiment 1
    [0033] The method for fabricating a capacitor of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 4 through 7. [0033]
    [0034] FIG. 4 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern [0034] 120 and a lower electrode 140, and FIG. 5 is a cross-sectional diagram for illustrating the step of forming first and second hemispherical grained silicon (HSG-Si) seeds 150 a and 150 b. Here, the insulation pattern 120, the lower electrode 140, the first HSG-Si seeds 150 a and the second HSG-Si seeds 150 b are formed in the same manner as the conventional method described with reference to FIGS. 1 and 2.
    [0035] FIG. 6 is a cross-sectional diagram for illustrating the step of forming a modified lower electrode [0035] 140 a. Here, the surface of the lower electrode 140 is etched by using the first HSG-Si seeds 150 a as an etching mask to form a depressed portion on the surface of the lower electrode 140, resulting in the formation of a modified lower electrode 140 a. Also, preferably, gas including chlorine such as Cl2, BCl3, ClF3 and HCl is used during the etching process.
    [0036] The HSG-Si seeds [0036] 150 a and 150 b and the insulation layer pattern 120 are more resistant to etching than the lower electrode 140 with respect to the gas including chlorine, so that the HSG-Si seeds 150 a and 150 b, and the insulation layer pattern 120 are etched less than the lower electrode 140. Here, preferable, anisotropic etching is performed while varying the incident angle, for effectively forming the depressed portion to create a larger surface area.
    [0037] FIG. 7 is a cross-sectional diagram for illustrating the step of forming HSG-Si [0037] 150 c, wherein the substrate having the modified lower electrode 140 a is heated at 560˜630°C. to selectively grow the first HSG-Si seeds 150 a, thereby forming the HSG-Si 150 c on the modified lower electrode 140 a. Here, since the first HSG-Si seeds 150 a grows by receiving silicon from the modified lower electrode 140 a while the second HSG-Si seeds 150 b does not receive silicon required for growth, the first HSG-Si seeds 150 a are grown selectively.
    [0038] According to this preferred embodiment, after forming the HSG-Si seeds [0038] 150 a and 150 b, the step of etching the lower electrode 140 using gas including chlorine is further performed differently from the conventional method, resulting in a ridge and valley-type lower electrode in which the ridges and valleys is more severe than that of the conventional one. Thus, the surface area of the lower electrode is increased, so that a capacitance can be provided which is greater than that of the conventional method. Embodiment 2
    [0039] FIGS. 8 through 10 are cross-sectional diagrams for illustrating a method for fabricating a capacitor of a semiconductor device according to a second embodiment of the present invention. [0039]
    [0040] FIG. 8 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern [0040] 121 and a lower electrode 141, and FIG. 9 is a cross-sectional diagram for illustrating the step of forming first and second HSG-Si seeds 151 a and 151 b. Here, the insulation layer 121, the lower electrode 141, and the first and second HSG-Si seeds 151 a and 151 b are formed in the same manner as the conventional method described with reference to FIGS. 1 and 2.
    [0041] FIG. 10 is a cross-sectional diagram for illustrating the step of forming HSG-Si [0041] 151 c. Here, the substrate having first and second HSG-Si seeds 151 a and 151 b is heated at 560˜630°C. to selectively grow only the first HSG-Si seeds 151 a, resulting in the formation of HSG-Si 151 c on the lower electrode 141. Since the first HSG-Si seeds 151 a grows by receiving silicon from the lower electrode 141 while the second HSG-Si seeds 151 b do not receive silicon required for growth, only the first HSG-Si seeds 151 a grow.
    [0042] FIG. 11 is a cross-sectional diagram for illustrating the step of removing the second HSG-Si seeds [0042] 151 b, wherein the entire surface of the substrate having the HSG-Si 151 c is etched using gas including chlorine such as Cl2, BCl3, ClF3 and HCl, thereby removing the second HSG-Si seeds 151 b.
    [0043] Here, the HSG-Si [0043] 151 c are slightly etched, resulting in the formation of a modified HSG-Si 151 d whose size is reduced. Also, when removing the second HSG-Si seeds 151 b, the lower electrode 141 is etched for the same reason described with reference FIG. 6, so that a modified lower electrode 141 a having a depressed portion on the surface thereof is formed. Thus, the surface area of the lower electrode 141 is not changed significantly.
    [0044] According to this preferred embodiment, after selectively growing only the first HSG-Si seeds [0044] 151 a, the second HSG-Si seeds 151 b are removed through an etching process using a gas including chlorine. As a result, an electrical short between the lower electrodes of each adjacent capacitor can be prevented without a decrease in capacitance.
    [0045] Also, preferably, the first embodiment of the present invention further includes the step of removing the second HSG-Si seeds [0045] 150 b of FIG. 7 through the etching process described in FIG. 10, after the step of forming HSG-Si 150 c of FIG 7.
    [0046] As described above, in the method of fabricating a capacitor of a semiconductor device according to the present invention, the surface area of the lower electrode is increased, so that a capacitance higher than that of the conventional method can be ensured. Also, the electrical short between the lower electrodes of each adjacent capacitor can be prevented without a decrease in capacitance. [0046]
    [0047] The present invention is not limited to the particular forms illustrated, and further modifications and alterations will be apparent to those skilled in the art within the spirit and scope of this invention. [0047]
    权利要求:
    Claims (15)
    [1" id="US-20010003065-A1-CLM-00001] 1. A method for forming a capacitor of a semiconductor device comprising the steps of:
    (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate;
    (b) forming a lower electrode on a predetermined area of said insulation layer pattern, said lower electrode is connected to the exposed semiconductor substrate via said contact hole;
    (c) forming HSG-Si seeds on the surfaces of said lower electrode and said insulation layer pattern;
    (d) etching the surface of said lower electrode by using said HSG-Si seeds formed on the surface of said lower electrode as an etching mask to form a depressed portion on the surface of said lower electrode, resulting in the formation of a modified lower electrode; and
    (e) growing said HSG-Si seeds formed on the surface of said lower electrode to form multiple bumps of HSG-Si.
    [2" id="US-20010003065-A1-CLM-00002] 2. A method for forming a capacitor of a semiconductor device as claimed in
    claim 1 , wherein said step (d) of etching the surface of said lower electrode is performed using a gas including chlorine.
    [3" id="US-20010003065-A1-CLM-00003] 3. A method for forming a capacitor of a semiconductor device as claimed in
    claim 2 , wherein said gas including chlorine is one selected from the group consisting of Cl2, BCl3, ClF3 and HCl.
    [4" id="US-20010003065-A1-CLM-00004] 4. A method for forming a capacitor of a semiconductor device as claimed in
    claim 1 , wherein said step (d) of etching the surface of said lower electrode is performed by anisotropically etching while varying the incident angle of etching gas.
    [5" id="US-20010003065-A1-CLM-00005] 5. A method for forming a capacitor of a semiconductor device as claimed in
    claim 1 , wherein said step (e) of growing said HSG-Si seeds is performed by heating the substrate having said HSG-Si seeds.
    [6" id="US-20010003065-A1-CLM-00006] 6. A method for forming a capacitor of a semiconductor device as claimed in
    claim 5 , wherein said heating is performed at 560˜630°C.
    [7" id="US-20010003065-A1-CLM-00007] 7. A method for forming a capacitor of a semiconductor device as claimed in
    claim 1 , further comprising the step of removing said HSG-Si seeds formed on the surface of said insulation layer pattern by an etching after said step (e).
    [8" id="US-20010003065-A1-CLM-00008] 8. A method for forming a capacitor of a semiconductor device as claimed in
    claim 7 , wherein said step of removing HSG-Si seeds formed on the surface of said insulation layer pattern by an etching is performed by using said gas including chlorine.
    [9" id="US-20010003065-A1-CLM-00009] 9. A method for forming a capacitor of a semiconductor device as claimed in
    claim 8 , wherein said gas including chlorine is one selected from the group consisting of Cl2, BCl3, ClF3 and HCl.
    [10" id="US-20010003065-A1-CLM-00010] 10. A method for forming a capacitor of a semiconductor device comprising the steps of:
    (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate;
    (b) forming a lower electrode on a predetermined area of said insulation layer pattern, said lower electrode is connected to the exposed semiconductor substrate via said contact hole;
    (c) forming HSG-Si seeds on the surfaces of said lower electrode and said insulation layer pattern;
    (d) selectively growing said HSG-Si seeds formed on the surface of said lower electrode to form multiple bumps of HSG-Si on the surface of said lower electrode;
    (e) removing said HSG-Si seeds formed on the surface of said insulation layer pattern through an etching process.
    [11" id="US-20010003065-A1-CLM-00011] 11. A method for forming a capacitor of a semiconductor device as claimed in
    claim 10 , wherein said step (c) of forming said HSC-Si seeds is performed by a chemical vapor deposition (CVD) method using a silicon source gas.
    [12" id="US-20010003065-A1-CLM-00012] 12. A method for forming a capacitor of a semiconductor device as claimed in
    claim 10 , wherein said step (d) of forming said HSG-Si is performed by heating the substrate having said HSG-Si seeds.
    [13" id="US-20010003065-A1-CLM-00013] 13. A method for forming a capacitor of a semiconductor device as claimed in
    claim 10 , wherein said heating is performed at 560˜630°C.
    [14" id="US-20010003065-A1-CLM-00014] 14. A method for forming a capacitor of a semiconductor device as claimed in
    claim 10 , wherein said step of removing said HSG-Si seeds formed on the surface of said insulation layer pattern by an etching is performed by using a gas including chlorine.
    [15" id="US-20010003065-A1-CLM-00015] 15. A method for forming a capacitor of a semiconductor device as claimed in
    claim 14 , wherein said gas including chlorine is one selected from the group consisting of Cl2, BCl3, ClF3 and HCl.
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    法律状态:
    2005-11-18| FPAY| Fee payment|Year of fee payment: 4 |
    2010-01-18| REMI| Maintenance fee reminder mailed|
    2010-06-11| LAPS| Lapse for failure to pay maintenance fees|
    2010-07-12| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2010-08-03| FP| Expired due to failure to pay maintenance fee|Effective date: 20100611 |
    优先权:
    申请号 | 申请日 | 专利标题
    KR95-34751||1995-10-10||
    KR19950034751||1995-10-10||
    KR1019960042688A|KR100224710B1|1995-10-10|1996-09-25|Method for manufacturing of capacitor in semiconductor device|
    KR96-42688||1996-09-25||
    US08/729,232|US6194263B1|1995-10-10|1996-10-09|Methods for forming capacitor structures including etching pits|
    US09/742,650|US6403495B2|1995-10-10|2000-12-21|Capacitor fabricating method of semiconductor device|US09/742,650| US6403495B2|1995-10-10|2000-12-21|Capacitor fabricating method of semiconductor device|
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