• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
    公开号:US20010002304A1
    申请号:US09/769,603
    申请日:2001-01-24
    公开日:2001-05-31
    发明作者:Christophe Pierrat；James Burdorf；William Baggenstoss；William Stanton
    申请人:Christophe Pierrat；Burdorf James E.；William Baggenstoss；William Stanton；
    IPC主号:G03F1-36
    专利说明:
    [0001] The present invention relates to methods of reducing proximity effects in lithographic processes. [0001] BACKGROUND OF THE INVENTION
    [0002] Fabrication of integrated circuitry typically involves lithographically transferring a pattern which is disposed on a mask onto a layer of material such as photoresist received over a substrate. The pattern on the mask generally defines integrated circuitry patterns and alignment patterns. It has been observed that differences in pattern development of circuit features can depend upon the proximity of the features relative to one another. So-called “proximity effects” in a lithographic process can arise during imaging, resist pattern formation, and subsequent pattern transfer steps such as etching. The magnitude of the proximity effects depends on the proximity or closeness of the two features present on the masking pattern. Proximity effects are known to result from optical diffraction in the projection system used to form the pattern over the substrate. This diffraction causes adjacent features to interact with one another in such a way as to produce pattern-dependent variations. These variations can affect the integrity of the finished devices. [0002]
    [0003] This invention arose out of concerns associated with improving the manner in which integrated circuitry is formed. In particular, this invention arose out of concerns associated with reducing proximity effects. [0003] SUMMARY OF THE INVENTION
    [0004] Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension. [0004] BRIEF DESCRIPTION OF THE DRAWINGS
    [0005] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0005]
    [0006] FIG. 1 is a top plan view of a portion of a mask pattern. [0006]
    [0007] FIG. 2 is a top plan view of a portion of a mask pattern in accordance with one embodiment of the invention. [0007]
    [0008] FIG. 3 is a top plan view of a mask pattern in accordance with one embodiment of the present invention. [0008]
    [0009] FIG. 4 is a side elevational view of the semiconductor wafer fragment which has been processed in accordance with one embodiment of the invention. [0009]
    [0010] FIG. 5 is a top plan view of a portion of a mask pattern in accordance with one embodiment of the invention. [0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0011] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). [0011]
    [0012] Referring to FIG. 1, a portion of a mask pattern on a mask is shown generally at [0012] 10 and comprises at least one main feature 12 and at least one proximity effects-correcting feature 14. In this example, two proximity effects-correcting features 14 are shown. Mask 10 is to be utilized in a lithographic process wherein an integrated circuitry pattern corresponding to main feature 12 is transferred from the mask onto a semiconductor substrate. In the illustrated example, main feature 12 has a plurality of sides or edges 16, 18 which define a first width dimension. For purposes of the ongoing discussion, side 16 comprises a first side and side 18 comprises a second side. The illustrated first and second sides are generally parallel with one another and are laterally displaced from proximity effects-correcting features 14. A proximity effects-correcting feature is disposed on either side of main feature 12. It is possible, however, for only one proximity effects-correcting feature to be disposed on one side of main feature 12.
    [0013] In the illustrated and preferred embodiment, proximity-effects correcting features [0013] 14 comprise sub-resolution features which are not ultimately transferred onto the substrate. In this example, main feature 12 comprises a conductive line pattern which is to be transferred onto a substrate. Any number of main features can be defined on the mask. Accordingly, a plurality of main features comprising conductive line patterns can be defined on the mask. Main feature 12 and proximity effects-correcting features 14 each have respective width dimensions, with the width dimension of the proximity effects-correcting features 14 being shown at S, and the width of main feature 12 being shown at CD1. The proximity effects-correcting features can have different widths.
    [0014] In accordance with one embodiment of the invention, a desired spacing D[0014] 1 is defined between main feature 12 and at least one adjacent proximity effects-correcting feature 14. The desired spacing between the main feature and the proximity effects-correcting features can be the same, as is shown, or can be different. In this example, and because there are two illustrated proximity effects-correcting features, two such desired spacings are defined which happen to be the same in magnitude. In one embodiment, the definition of the desired spacing is conducted to optimize the depth of focus (DOF) in the lithographic process. Depth of focus is an important characteristic of an exposure tool and is defined as the range in which the aerial image (of a near resolution sized feature) will stay in focus. In a lithographic process in which an image is transferred into a photoresist layer, a minimum or optimized DOF is required. This minimum or optimized DOF ensures that the image remains sufficiently in focus throughout the resist layer. Thus, the minimum or optimized DOF range is typically greater than or equal to the thickness of the resist layer. Other parameters can, of course, be considered in the context of defining the desired spacing between a main feature and a proximity effects-correcting feature, e.g. exposure latitude and image log slope.
    [0015] Referring to FIG. 2, the dimensions or shape of main feature [0015] 12 are adjusted relative to the proximity effects-correcting feature (S) to achieve a desired transferred main feature dimension. The dimensional or shape adjustment of the main feature can take place through a change in the area size of the main feature. In the illustrated example, the area size of main feature 12 is adjusted by increasing the area size from that which is shown in FIG. 1 to that which is shown in FIG. 2. Such adjustment takes place by moving at least a portion of one or both of sides or edges 16, 18 from its previous position (shown in dashed lines), to its illustrated position in FIG. 2. In this example, both of sides or edges 16, 18 are moved or repositioned relative to their original positions.
    [0016] The adjustment of the main feature dimension can take place through movement of an associated side or edge, or a portion(s) thereof, either toward or away from an adjacent proximity effects-correcting feature. Where only one proximity effect-correcting feature is used, movement of the associated side of the main feature can take place toward or away from the proximity effects-correcting feature. In this example, each side is repositioned by moving it closer to or toward its next adjacent proximity effects-correcting feature; Movement of one or more of the edges can, however, be conducted away from a proximity effects-correcting feature or, particularly, away from a next-adjacent proximity effects-correcting feature. Such movement can either increase or decrease the dimensions of the main feature. The main feature shape or dimension can also be adjusted by moving individual portions of individual sides toward or away from the proximity effects-correcting feature. Such can result in a staggered construction such as is shown in FIG. 5. [0016]
    [0017] In a preferred embodiment, the desired transferred main feature dimension which is ultimately formed over a substrate is approximately equal to a minimum photolithographic feature size from which the integrated circuitry is fabricated. This will become more apparent in connection with the discussion relative to FIG. 4. [0017]
    [0018] In a preferred embodiment, a width dimension of main feature [0018] 12, i.e. CD1, is changed without changing any dimensions of the proximity effects-correcting or sub-resolution features. Specifically, and as is apparent from a comparison of FIGS. 1 and 2, CD2 of main feature 12 is different from and, in this example greater than CD1 in FIG. 1. At the same time, the widths of the proximity effects-correcting features 14, i.e. S, are consistent between FIGS. 1 and 2. Such change in main feature width also changes the spacing between the main feature and its associated proximity effects-correcting feature. Specifically, a spacing D2 (FIG. 2) is defined between the main feature and each of the associated proximity effects-correcting features 14. In this example, D2 is less than D1. The spacing D2 can vary as between a main feature's sides and the next-adjacent proximity effects-correcting features, or between different portions of a main feature's side and the next-adjacent proximity effects-correcting feature for that side.
    [0019] Referring to FIG. 3, a plurality of main features [0019] 20, 22, 24, and 26, e.g. conductive line patterns, are defined on a mask. As initially defined, however, and not specifically illustrated here, main features 20-26 would have substantially common width dimensions. However, due to proximity effects, the ultimately provided patterned main features over the substrate corresponding to the main features on a mask would not result in uniformly-patterned main features over the substrate.
    [0020] As ultimately provided on mask [0020] 10, however, main features 22, 24, and 26 would have width dimensions comparable to CD1 which is shown in FIG. 1, and main feature 20 would have a width dimension comparable to CD2 which is shown in FIG. 2. With these width dimensions, main feature patterns can be formed over a substrate with width dimensions which are no greater than a minimum photolithographic feature size from which the integrated circuitry is fabricated. Main feature 20, and more likely a plurality of similar main features are spaced from other main features a distance which is effective to form one or more patterned main features over the substrate which is (are) spaced from other patterned main features a distance which is greater than the minimum photolithographic feature size. This variation in spacing is one factor which can lead to proximity effect-related irregularities in the ultimately patterned feature.
    [0021] Prior to provision of the illustrated mask in FIG. 3, processing can take place with respect to main feature [0021] 20 as described above in connection with FIGS. 1 and 2. Specifically, a desired spacing is defined between main feature 20 and at least one proximity effects-correcting features 28, 30. After definition of the desired spacing which, in a preferred embodiment, is selected to achieve a desired depth of focus (DOF), at least portions of one or more of the sides or edges of main feature 20 are moved or repositioned to define a second width dimension (corresponding to CD2 in FIG. 2) which is different from the first originally-defined width dimension. In the illustrated example, both of the sides or edges have been moved or repositioned to be closer to their next adjacent or nearest proximity effects-correcting feature 28, 30. Accordingly, such movement increases the area size of the main feature 20. Changing the dimensional size, shape, or area of the main feature as just described, relative to one or more adjacent proximity effects-correcting features, can enable a patterned main feature to be formed on the substrate to have a width dimension which is no greater than a minimum photolithographic feature size which is utilized to form the integrated circuitry.
    [0022] For example, and with respect to FIG. 4, a plurality of conductive lines [0022] 20 a, 22 a, 24 a, and 26 a are formed over a substrate 32. Lines 20 a-26 a have been formed through the use of a mask such as one containing main feature patterns 20-26. As can be seen, each formed conductive line has a width w which, in a preferred embodiment, is no greater than the minimum photolithographic feature size from which the integrated circuitry is formed. It will be observed that the conductive line 20 a (corresponding to main feature 20 (FIG. 3)) has a width which is similar to, or the same as the widths of conductive lines 22 a-26 a which are spaced closer together. Accordingly, proximity effects which previously affected the subsequently patterned main feature widths have been substantially reduced, if not eliminated. Thus, lines 20 a-26 a have substantially common patterned width dimensions.
    [0023] Advantages achieved by the various embodiments of the invention include better dimensional control of substrate features through correction of the defined main features after placement of the proximity effects-correcting features. This can also reduce processing overhead through reductions in the data volume required to implement the various methods by the various industry processors utilized to do so. [0023]
    [0024] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0024]
    权利要求:
    Claims (36)
    [1" id="US-20010002304-A1-CLM-00001] 1. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
    defining a desired spacing between a main feature which is to reside on the mask and which is to be transferred onto the substrate and an adjacent proximity effects-correcting feature; and
    after said defining, adjusting the dimensions of the main feature relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension.
    [2" id="US-20010002304-A1-CLM-00002] 2. The method of
    claim 1 , wherein the defining of the desired spacing comprises selecting a spacing to optimize the depth of focus in the lithographic process.
    [3" id="US-20010002304-A1-CLM-00003] 3. The method of
    claim 1 , wherein the adjusting of the dimensions of the main feature comprises changing area size of the main feature.
    [4" id="US-20010002304-A1-CLM-00004] 4. The method of
    claim 1 , wherein the adjusting of the dimensions of the main feature comprises changing the shape of the main feature.
    [5" id="US-20010002304-A1-CLM-00005] 5. The method of
    claim 1 , wherein the adjusting of the dimensions of the main feature comprises increasing area size of the main feature.
    [6" id="US-20010002304-A1-CLM-00006] 6. The method of
    claim 1 , wherein the main feature has a plurality of sides and the adjusting of the dimensions of the main feature comprises moving at least a portion of one of the sides.
    [7" id="US-20010002304-A1-CLM-00007] 7. The method of
    claim 1 , wherein the main feature has a plurality of sides and the adjusting of the dimensions of the main feature comprises moving at least a portion of at least one of the sides.
    [8" id="US-20010002304-A1-CLM-00008] 8. The method of
    claim 1 , wherein the main feature has first and second sides which are generally parallel with one another and laterally displaced from the proximity effects-correcting feature, and wherein the adjusting of the dimensions of the main feature comprises moving portions of each of the first and second sides.
    [9" id="US-20010002304-A1-CLM-00009] 9. The method of
    claim 1 , wherein the defining of the desired spacing comprises defining said spacing between said main feature and two proximity effects-correcting features.
    [10" id="US-20010002304-A1-CLM-00010] 10. The method of
    claim 1 , wherein the defining of the desired spacing comprises defining said spacing between said main feature and two proximity effects-correcting features, wherein the main feature has first and second sides which are spaced apart from one another, and wherein a proximity effects-correcting feature is disposed on either side of the main feature laterally spaced from a respective one of the first and second sides, and wherein the adjusting of the dimensions of the main feature comprises repositioning at least a portion of one of the first and second sides relative to its next adjacent proximity effects-correcting feature.
    [11" id="US-20010002304-A1-CLM-00011] 11. The method of
    claim 1 , wherein the defining of the desired spacing comprises defining said spacing between said main feature and two proximity effects-correcting features, wherein the main feature has first and second sides which are spaced apart from one another, and wherein a proximity effects-correcting feature is disposed on either side of the main feature laterally spaced from a respective one of the first and second sides, and wherein the adjusting -of the dimensions of the main feature comprises repositioning portions of each of the first and second sides relative to its next adjacent proximity effects-correcting feature.
    [12" id="US-20010002304-A1-CLM-00012] 12. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
    defining a desired spacing between a main feature which is to reside on the mask and which is to be transferred onto the substrate and an adjacent sub-resolution feature, the main feature having an edge; and
    moving the edge of the main feature relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
    [13" id="US-20010002304-A1-CLM-00013] 13. The method of
    claim 12 , wherein the defining of the desired spacing comprises selecting the spacing to achieve a desired depth of focus.
    [14" id="US-20010002304-A1-CLM-00014] 14. The method of
    claim 12 , wherein the moving of the edge comprises moving said edge away from the sub-resolution feature.
    [15" id="US-20010002304-A1-CLM-00015] 15. The method of
    claim 12 , wherein the moving of the edge comprises moving said edge away from the sub-resolution feature, wherein said moving increases the dimensions of the main feature.
    [16" id="US-20010002304-A1-CLM-00016] 16. The method of
    claim 12 , wherein the moving of the edge comprises moving said edge toward the sub-resolution feature.
    [17" id="US-20010002304-A1-CLM-00017] 17. The method of
    claim 12 , wherein the moving of the edge comprises moving said edge toward the sub-resolution feature, wherein said moving increases the dimensions of the main feature.
    [18" id="US-20010002304-A1-CLM-00018] 18. The method of
    claim 12 , wherein said moving increases the dimensions of the main feature.
    [19" id="US-20010002304-A1-CLM-00019] 19. The method of
    claim 12 , wherein the main feature comprises a conductive line pattern, and the desired transferred main feature dimension is approximately equal to a minimum photolithographic feature size from which the integrated circuitry is fabricated.
    [20" id="US-20010002304-A1-CLM-00020] 20. The method of
    claim 12 , wherein the main feature comprises a conductive line pattern and said moving increases the dimensions of the main feature, and wherein the desired transferred main feature dimension is approximately equal to a minimum photolithographic feature size from which the integrated circuitry is fabricated.
    [21" id="US-20010002304-A1-CLM-00021] 21. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
    defining a plurality of main features which are to appear on the mask and be transferred onto a substrate, the main features having width dimensions;
    defining a desired spacing between a sub-resolution feature and one of the main features;
    changing a width dimension of the one main feature and not changing any dimensions of the sub-resolution feature; and
    forming a plurality of patterned main features on the substrate using the mask, said plurality of main features having substantially common patterned width dimensions.
    [22" id="US-20010002304-A1-CLM-00022] 22. The method of
    claim 21 , wherein the forming of the plurality of patterned main features comprises forming said features to have width dimensions which are approximately equal to the minimum photolithographic feature size from which the integrated circuitry is formed.
    [23" id="US-20010002304-A1-CLM-00023] 23. The method of
    claim 21 , wherein the defining of the desired spacing comprises selecting said spacing to achieve a desired depth of focus.
    [24" id="US-20010002304-A1-CLM-00024] 24. The method of
    claim 21 , wherein the defining of the plurality of main features comprises defining at least one conductive line pattern.
    [25" id="US-20010002304-A1-CLM-00025] 25. The method of
    claim 21 , wherein the defining of the plurality of main features comprises defining at least one conductive line pattern, and the forming of the plurality of patterned main features comprises forming said features to have at least one conductive line width which is approximately equal to the minimum photolithographic feature size from which the integrated circuitry is formed.
    [26" id="US-20010002304-A1-CLM-00026] 26. The method of
    claim 21 , wherein the defining of the plurality of main features comprises defining a plurality of conductive line patterns.
    [27" id="US-20010002304-A1-CLM-00027] 27. The method of
    claim 21 , wherein:
    the defining of the plurality of main features comprises defining a plurality of conductive line patterns;
    said one main feature has a pair of spaced-apart edges; and
    wherein said changing of the width dimension of said one main feature comprises moving one of said edges toward the sub-resolution feature.
    [28" id="US-20010002304-A1-CLM-00028] 28. The method of
    claim 21 , wherein:
    the defining of the plurality of main features comprises defining a plurality of conductive line patterns;
    said one main feature has a pair of spaced-apart edges; and
    wherein said changing of the width dimension of said one main feature comprises moving one of said edges toward the sub-resolution feature, said one edge being the nearest of the spaced-apart edges relative to the sub-resolution feature.
    [29" id="US-20010002304-A1-CLM-00029] 29. A method of reducing proximity effects in a lithographic process wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate, the method comprising:
    defining a plurality of main features which are to appear on the mask at least some of which having width dimensions effective to form main feature patterns over a substrate with width dimensions which are no greater than a minimum photolithographic feature size from which the integrated circuitry is fabricated, one of the main features being spaced from other main features a distance which is effective to form a patterned main feature over the substrate which is spaced from other patterned main features over the substrate a distance which is greater than the minimum photolithographic feature size, the one main feature having a pair of edges defining a first width dimension;
    defining a desired spacing between the one main feature and a proximity effects-correcting feature which is to appear on the mask adjacent the one main feature; and
    after said defining of the desired spacing, moving one of the edges of the one main feature to define a second width dimension which is different from the first width dimension, said moving enabling a patterned main feature to be formed on the substrate corresponding to the one main feature to have a width dimension which is no greater than the minimum photolithographic feature size.
    [30" id="US-20010002304-A1-CLM-00030] 30. The method of
    claim 29 , wherein the proximity effects-correcting feature comprises a sub-resolution feature.
    [31" id="US-20010002304-A1-CLM-00031] 31. The method of
    claim 29 , wherein the defining of the desired spacing comprises defining said spacing to achieve a maximum depth of focus.
    [32" id="US-20010002304-A1-CLM-00032] 32. The method of
    claim 29 , wherein the moving of the one edge of the one main feature comprises moving the edge nearest the proximity effects-correcting feature.
    [33" id="US-20010002304-A1-CLM-00033] 33. The method of
    claim 29 , wherein the moving of the one edge of the one main feature comprises moving the edge nearest the proximity effects-correcting feature toward said proximity effects-correcting feature.
    [34" id="US-20010002304-A1-CLM-00034] 34. The method of
    claim 29 , wherein the second width is greater than the first width.
    [35" id="US-20010002304-A1-CLM-00035] 35. The method of
    claim 29 , wherein the moving of the one edge of the one main feature comprises moving the edge nearest the proximity effects-correcting feature, and wherein the second width is greater than the first width.
    [36" id="US-20010002304-A1-CLM-00036] 36. The method of
    claim 29 , wherein the defining of the plurality of main features comprises defining a plurality of conductive line patterns.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6319644B2|2001-11-20|Methods of reducing proximity effects in lithographic processes
    US7202148B2|2007-04-10|Method utilizing compensation features in semiconductor processing
    US6869735B2|2005-03-22|Method of pattern layout of a photomask for pattern transfer
    JP2004118194A|2004-04-15|3d opc by substrate topography compensation:anchored topography in mask design
    US7122453B2|2006-10-17|Methods of patterning radiation, methods of forming radiation-patterning tools, and radiation-patterning tools
    US8435884B2|2013-05-07|Method for forming an interconnect structure
    KR100732753B1|2007-06-27|Manufacturing method for semiconductor device
    US5900349A|1999-05-04|Method for forming fine patterns of semiconductor device
    US7144690B2|2006-12-05|Photolithographic methods of using a single reticle to form overlapping patterns
    KR20010113838A|2001-12-28|Method to produce high density memory cells and small spaces by using nitride spacer
    US9329471B1|2016-05-03|Achieving a critical dimension target based on resist characteristics
    JP2002116529A|2002-04-19|Correction method for semiconductor circuit design pattern data and photomask made by pattern data obtained by this correction method
    JP2005259991A|2005-09-22|Patterning method
    KR100599507B1|2006-07-13|Photo Mask Making Method
    US6767672B2|2004-07-27|Method for forming a phase-shifting mask for semiconductor device manufacture
    KR100755074B1|2007-09-06|Photomask and manufacturing method therefor
    US20050058915A1|2005-03-17|Photomask
    CN107490932B|2020-11-27|Method for correcting mask graph
    CN106610563B|2020-10-09|Mask and double patterning method
    US20030117605A1|2003-06-26|Apparatus and method for contact hole exposure
    US20090311865A1|2009-12-17|Method for double patterning lithography
    US20040043306A1|2004-03-04|Phase shift mask
    KR100668731B1|2007-02-05|Half Tone Mask and Method for Fabricating of the Same
    US20030186557A1|2003-10-02|Fabrication method for lines of semiconductor device
    同族专利:
    公开号 | 公开日
    AU6280799A|2000-04-17|
    AT467858T|2010-05-15|
    EP1125167A1|2001-08-22|
    WO2000019272B1|2000-05-25|
    EP1125167B1|2010-05-12|
    US6120952A|2000-09-19|
    KR20010075482A|2001-08-09|
    US6319644B2|2001-11-20|
    DE69942370D1|2010-06-24|
    US6284419B2|2001-09-04|
    JP3461336B2|2003-10-27|
    JP2002526792A|2002-08-20|
    WO2000019272A1|2000-04-06|
    US20010023045A1|2001-09-20|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20040044980A1|2002-08-27|2004-03-04|Werner Juengling|Method and apparatus for designing a pattern on a semiconductor surface|
    US20040044978A1|2002-08-28|2004-03-04|Werner Juengling|Pattern generation on a semiconductor surface|
    US6803157B2|2002-03-01|2004-10-12|Micron Technology, Inc.|Pattern mask with features to minimize the effect of aberrations|
    US20060270068A1|2005-05-31|2006-11-30|Taiwan Semiconductor Manufacturing Co., Ltd.|Method for fabricating right-angle holes in a substrate|
    US20100273303A1|2006-08-21|2010-10-28|Micron Technology, Inc.|Memory Arrays and Methods of Fabricating Memory Arrays|
    US8389363B2|2006-02-02|2013-03-05|Micron Technology, Inc.|Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates|
    US8399920B2|2005-07-08|2013-03-19|Werner Juengling|Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls|
    US8426273B2|2005-08-30|2013-04-23|Micron Technology, Inc.|Methods of forming field effect transistors on substrates|
    US8446762B2|2006-09-07|2013-05-21|Micron Technology, Inc.|Methods of making a semiconductor memory device|
    US8551823B2|2006-07-17|2013-10-08|Micron Technology, Inc.|Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines|
    US10515801B2|2007-06-04|2019-12-24|Micron Technology, Inc.|Pitch multiplication using self-assembling materials|US5242770A|1992-01-16|1993-09-07|Microunity Systems Engineering, Inc.|Mask for photolithography|
    JP3194155B2|1992-01-31|2001-07-30|キヤノン株式会社|Semiconductor device manufacturing method and projection exposure apparatus using the same|
    CA2132005A1|1992-04-06|1993-10-14|Jang Fung Chen|Method for improved lithographic patterning in a semiconductor fabrication process|
    US5256505A|1992-08-21|1993-10-26|Microunity Systems Engineering|Lithographical mask for controlling the dimensions of resist patterns|
    US5447810A|1994-02-09|1995-09-05|Microunity Systems Engineering, Inc.|Masks for improved lithographic patterning for off-axis illumination lithography|
    JPH08202020A|1995-01-31|1996-08-09|Sony Corp|Evalulating method of pattern in photomask, photomask, production of photomask, forming method of pattern in photomask and exposing method|
    US5663893A|1995-05-03|1997-09-02|Microunity Systems Engineering, Inc.|Method for generating proximity correction features for a lithographic mask pattern|
    JPH0915833A|1995-06-30|1997-01-17|Sony Corp|Scanning data forming device and scanning data forming method in exposing mask manufacturing device|
    US5972541A|1996-02-27|1999-10-26|Lsi Logic Corporation|Reticle and method of design to correct pattern for depth of focus problems|
    US5707765A|1996-05-28|1998-01-13|Microunity Systems Engineering, Inc.|Photolithography mask using serifs and method thereof|
    US5795688A|1996-08-14|1998-08-18|Micron Technology, Inc.|Process for detecting defects in photomasks through aerial image comparisons|
    US5821014A|1997-02-28|1998-10-13|Microunity Systems Engineering, Inc.|Optical proximity correction method for intermediate-pitch features using sub-resolution scattering bars on a mask|
    US5958635A|1997-10-20|1999-09-28|Motorola, Inc.|Lithographic proximity correction through subset feature modification|
    US5858591A|1998-02-02|1999-01-12|Taiwan Semiconductor Manufacturing Company Ltd.|Optical proximity correction during wafer processing through subfile bias modification with subsequent subfile merging|
    US6120952A|1998-10-01|2000-09-19|Micron Technology, Inc.|Methods of reducing proximity effects in lithographic processes|US6499003B2|1998-03-03|2002-12-24|Lsi Logic Corporation|Method and apparatus for application of proximity correction with unitary segmentation|
    US6120952A|1998-10-01|2000-09-19|Micron Technology, Inc.|Methods of reducing proximity effects in lithographic processes|
    JP2000235251A|1999-02-16|2000-08-29|Sony Corp|Exposure pattern correction method, exposure method, aligner, photomask and semiconductor device|
    US6301697B1|1999-04-30|2001-10-09|Nicolas B. Cobb|Streamlined IC mask layout optical and process correction through correction reuse|
    US6467076B1|1999-04-30|2002-10-15|Nicolas Bailey Cobb|Method and apparatus for submicron IC design|
    US6335128B1|1999-09-28|2002-01-01|Nicolas Bailey Cobb|Method and apparatus for determining phase shifts and trim masks for an integrated circuit|
    US6643616B1|1999-12-07|2003-11-04|Yuri Granik|Integrated device structure prediction based on model curvature|
    TW440903B|2000-02-15|2001-06-16|Winbond Electronics Corp|Method to reduce the deviation of optical proximity effect in the photolithography process|
    US6361911B1|2000-04-17|2002-03-26|Taiwan Semiconductor Manufacturing Company|Using a dummy frame pattern to improve CD control of VSB E-beam exposure system and the proximity effect of laser beam exposure system and Gaussian E-beam exposure system|
    US7412676B2|2000-06-13|2008-08-12|Nicolas B Cobb|Integrated OPC verification tool|
    US6425113B1|2000-06-13|2002-07-23|Leigh C. Anderson|Integrated verification and manufacturability tool|
    US6541165B1|2000-07-05|2003-04-01|Numerical Technologies, Inc.|Phase shift mask sub-resolution assist features|
    US6777141B2|2000-07-05|2004-08-17|Numerical Technologies, Inc.|Phase shift mask including sub-resolution assist features for isolated spaces|
    US6516459B1|2000-07-10|2003-02-04|Mentor Graphics Corporation|Integrated circuit design correction using fragment correspondence|
    US6430737B1|2000-07-10|2002-08-06|Mentor Graphics Corp.|Convergence technique for model-based optical and process correction|
    DE10038928A1|2000-08-09|2002-02-28|Infineon Technologies Ag|Photolithographic mask|
    US6519760B2|2001-02-28|2003-02-11|Asml Masktools, B.V.|Method and apparatus for minimizing optical proximity effects|
    US6574784B1|2001-06-14|2003-06-03|George P. Lippincott|Short edge management in rule based OPC|
    DE10143723B4|2001-08-31|2006-09-28|Infineon Technologies Ag|A method for optimizing a layout for a mask for use in semiconductor fabrication|
    US7014956B2|2002-01-04|2006-03-21|Intel Corporation|Active secondary exposure mask to manufacture integrated circuits|
    US7013439B2|2002-01-31|2006-03-14|Juan Andres Torres Robles|Contrast based resolution enhancing technology|
    US7293249B2|2002-01-31|2007-11-06|Juan Andres Torres Robles|Contrast based resolution enhancement for photolithographic processing|
    US6783904B2|2002-05-17|2004-08-31|Freescale Semiconductor, Inc.|Lithography correction method and device|
    US6973633B2|2002-07-24|2005-12-06|George Lippincott|Caching of lithography and etch simulation results|
    US6857109B2|2002-10-18|2005-02-15|George P. Lippincott|Short edge smoothing for enhanced scatter bar placement|
    US6928634B2|2003-01-02|2005-08-09|Yuri Granik|Matrix optical process correction|
    US7147975B2|2003-02-17|2006-12-12|Matsushita Electric Industrial Co., Ltd.|Photomask|
    US6777146B1|2003-02-21|2004-08-17|International Business Machines Corporation|Method of optical proximity correction with sub-resolution assists|
    US7001693B2|2003-02-28|2006-02-21|International Business Machines Corporation|Binary OPC for assist feature layout optimization|
    US6964032B2|2003-02-28|2005-11-08|International Business Machines Corporation|Pitch-based subresolution assist feature design|
    US7205633B2|2003-06-27|2007-04-17|Micron Technology, Inc.|Capacitor layout orientation|
    US7558419B1|2003-08-14|2009-07-07|Brion Technologies, Inc.|System and method for detecting integrated circuit pattern defects|
    US7003758B2|2003-10-07|2006-02-21|Brion Technologies, Inc.|System and method for lithography simulation|
    US7073162B2|2003-10-31|2006-07-04|Mentor Graphics Corporation|Site control for OPC|
    DE10356693A1|2003-11-27|2005-07-14|Infineon Technologies Ag|A method of generating an aberration avoiding mask layout for a mask|
    US7539954B2|2004-02-24|2009-05-26|Konstantinos Adam|OPC simulation model using SOCS decomposition of edge fragments|
    US7536660B2|2004-02-24|2009-05-19|Konstantinos Adam|OPC simulation model using SOCS decomposition of edge fragments|
    US7861207B2|2004-02-25|2010-12-28|Mentor Graphics Corporation|Fragmentation point and simulation site adjustment for resolution enhancement techniques|
    US7234130B2|2004-02-25|2007-06-19|James Word|Long range corrections in integrated circuit layout designs|
    WO2005111874A2|2004-05-07|2005-11-24|Mentor Graphics Corporation|Integrated circuit layout design methodology with process variation bands|
    US7240305B2|2004-06-02|2007-07-03|Lippincott George P|OPC conflict identification and edge priority system|
    US7547945B2|2004-09-01|2009-06-16|Micron Technology, Inc.|Transistor devices, transistor structures and semiconductor constructions|
    US7459248B2|2005-02-24|2008-12-02|James Word|Performing OPC on structures with virtual edges|
    US8037429B2|2005-03-02|2011-10-11|Mentor Graphics Corporation|Model-based SRAF insertion|
    US7493587B2|2005-03-02|2009-02-17|James Word|Chromeless phase shifting mask for integrated circuits using interior region|
    US7434199B2|2005-09-27|2008-10-07|Nicolas Bailey Cobb|Dense OPC|
    US7506285B2|2006-02-17|2009-03-17|Mohamed Al-Imam|Multi-dimensional analysis for predicting RET model accuracy|
    US7712068B2|2006-02-17|2010-05-04|Zhuoxiang Ren|Computation of electrical properties of an IC layout|
    US8056022B2|2006-11-09|2011-11-08|Mentor Graphics Corporation|Analysis optimizer|
    US7966585B2|2006-12-13|2011-06-21|Mentor Graphics Corporation|Selective shielding for multiple exposure masks|
    US7802226B2|2007-01-08|2010-09-21|Mentor Graphics Corporation|Data preparation for multiple mask printing|
    US7799487B2|2007-02-09|2010-09-21|Ayman Yehia Hamouda|Dual metric OPC|
    US7739650B2|2007-02-09|2010-06-15|Juan Andres Torres Robles|Pre-bias optical proximity correction|
    JP4557994B2|2007-02-22|2010-10-06|株式会社日立製作所|Method for manufacturing magnetic recording medium|
    US8713483B2|2007-06-05|2014-04-29|Mentor Graphics Corporation|IC layout parsing for multiple masks|
    CN101349861B|2007-07-19|2010-09-08|上海华虹Nec电子有限公司|Method of smoothing regulation type optical approach correcting light mask pattern|
    US7647569B2|2007-08-01|2010-01-12|Micron Technology, Inc.|Systems, methods, and computer-readable media for adjusting layout database hierarchies for more efficient database processing and storage|
    US7805699B2|2007-10-11|2010-09-28|Mentor Graphics Corporation|Shape-based photolithographic model calibration|
    US8037446B2|2008-07-16|2011-10-11|Micron Technology, Inc.|Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same|
    US8176446B2|2008-09-11|2012-05-08|International Business Machines Corporation|Method for compensating for variations in structures of an integrated circuit|
    法律状态:
    2001-08-16| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-02-09| FPAY| Fee payment|Year of fee payment: 4 |
    2009-02-04| FPAY| Fee payment|Year of fee payment: 8 |
    2010-01-04| AS| Assignment|Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Effective date: 20091223 Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Effective date: 20091223 |
    2013-02-06| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    US09/164,786|US6120952A|1998-10-01|1998-10-01|Methods of reducing proximity effects in lithographic processes|
    US56429600A| true| 2000-05-03|2000-05-03||
    US09/769,603|US6284419B2|1998-10-01|2001-01-24|Methods of reducing proximity effects in lithographic processes|US09/769,603| US6284419B2|1998-10-01|2001-01-24|Methods of reducing proximity effects in lithographic processes|
    [返回顶部]