• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A multi-chip module (MCM) that fails testing after its assembly is repaired by generating a wire-bonding solution for a repair die during testing, storing the repair solution in a computer system in association with a unique ID code read from the MCM, and then using the repair solution at a wire-bonding station to correctly bond out a repair die for the MCM. The use of a stored repair solution at the wire-bonding station eliminates the need for a human operator to manually select the repair solution, and thus reduces the opportunity for error while shortening the length of time it takes to complete the repair process.
    公开号:US20010000489A1
    申请号:US09/734,383
    申请日:2000-12-11
    公开日:2001-04-26
    发明作者:Warren Farnworth
    申请人:Farnworth Warren M.；
    IPC主号:H01L22-22
    专利说明:
    [1] 1. This application is a continuation of application Ser. No. 09/056,408, filed Apr. 7, 1998, pending. BACKGROUND OF THE INVENTION
    [2] 2. 1. Technical Field
    [3] 3. This invention relates in general to multi-chip modules and, more specifically, to methods for repairing such modules by bonding out a module repair site using a repair solution generated during module testing.
    [4] 4. 2. State of the Art
    [5] 5. As shown in FIG. 1, multi-chip modules (MCMs), comprising multiple dice carried on a printed circuit board (PCB) or other carrier substrate bearing circuit traces, are generally tested after being assembled, and those MCMs that pass testing are then shipped to customers. Those MCMs that fail testing are marked as such, typically by printing an “X” on the top of the “bad” (i.e., at least partially defective) dice that caused each MCM to fail testing. After being marked, any bad dice on a given MCM are disabled through various means including, for example, cutting conductive traces on the MCM to isolate the bad dice, or shorting conductive traces together to force a high-impedance condition on all inputs and outputs of the bad dice (e.g., by pulling the RAS* input of a Dynamic Random Access Memory (DRAM) permanently high).
    [6] 6. Once the bad dice are disabled, known-good die (KGD) repair dice are attached to each failing MCM at an empty repair site. The failing MCMs with attached repair dice then proceed to a wire-bonding station, where an operator manually selects the wire-bonding pattern (also referred to as a wire-bonding “solution” herein) necessary to connect the repair dice to traces on the carrier substrate to replace the disabled bad dice. The repair dice are wire-bonded using the manually selected wire-bonding solution, and the repaired MCMs are then retested, with those repaired MCMs that pass the retesting proceeding on to shipping, and those repaired MCMs that fail retesting proceeding once again to repair or, alternatively, to scrap.
    [7] 7. Because a wire-bonding machine operator manually selects a particular wire-bonding pattern for each MCM to be repaired, the process of repairing MCMs is subject to human error. Specifically, the operator generally selects the particular wire-bonding pattern to be used based on which dice are marked as bad (e.g., with the “X” described above), so the operator may make a mistake in observing which dice are marked as bad, or in selecting the appropriate wire-bonding pattern, or both.
    [8] 8. Therefore, there is a need in the art for a method of selecting a wire-bonding solution for an MCM to be repaired that avoids the chance for human error associated with the conventional method described above. BRIEF SUMMARY OF THE INVENTION
    [9] 9. In one embodiment of this invention, a multi-chip module (MCM) proceeds to testing after it is assembled. During testing, an ID code (e.g., a bar code) of the MCM is read. Then, if the MCM fails testing, a wire-bonding repair solution is generated and stored in a computer system in association with the ID code. The wire-bonding repair solution may identify, for example, which of several sets of bonding pads on the surface of a substrate of the MCM a repair integrated circuit (IC) die or dice should be wire-bonded to. A bad IC die or dice of the MCM that caused the MCM to fail testing may then be disabled by, for example, disconnecting the bad IC die or dice from the rest of the MCM, or by permanently connecting the bad IC die or dice so all of its inputs and outputs are in a high-impedance state. The repair IC die or dice is then attached to the substrate of the MCM, the stored repair solution is accessed, and the repair IC die or dice is wire-bonded to the substrate in accordance with the accessed repair solution. As a result, the opportunity for human error is avoided, and the length of time it takes to repair the MCM is shortened. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
    [10] 10.FIG. 1 is a flow diagram illustrating a conventional method for wire-bonding a repair die in a multi-chip module (MCM);
    [11] 11.FIG. 2 is a flow diagram illustrating a method in accordance with this invention for wire-bonding a repair die in an MCM;
    [12] 12.FIG. 3 is a top view of an MCM illustrating the arrangement of repair sites on the MCM; and
    [13] 13.FIG. 4 is an isometric view showing the MCM of FIG. 3 in more detail. DETAILED DESCRIPTION OF THE INVENTION
    [14] 14. As shown in FIGS. 2 and 3, the manufacture of a multi-chip module (MCM) 10 using the principles of this invention begins in assembly, where integrated circuit (IC) dice 12 and 14 are attached to a printed circuit board (PCB) 16 or other carrier substrate and are then wire-bonded to conductive traces (FIG. 4) on the surface of the PCB 16.
    [15] 15. It will be understood by those having skill in the technical field of this invention that the invention is applicable to any MCM including, for example, Dynamic Random Access Memory (DRAM) Single In-Line Memory Modules (SIMMs) and Dual In-Line Memory Modules (DIMMs). Also, it will be understood that this invention is applicable to any IC dice including, for example, DRAM dice, SRAM dice, Synchronous DRAM (SDRAM) dice, Sync-Link DRAM (SLDRAM) dice, processor dice (e.g., Intel Corp.'s Pentium® and Pentium II® chips), Extended Data-Out DRAM (EDO DRAM) dice, and flash Erasable Electrically Programmable Read Only Memory (EEPROM) dice.
    [16] 16. After assembly, the MCM 10 proceeds to testing. If the MCM 10 passes testing, it is generally ready for shipping to customers. If, instead, it fails because of a bad die 14, a wire-bonding repair solution is generated during testing that will later allow a repair die 18 positioned at one of two repair sites 20 to be wire-bonded such that it replaces the bad die 14. Specifically, this repair solution may identify, for example, which one of multiple sets of pads (see FIG. 4) on the PCB 16 the repair die 18 should be wire-bonded to in order for it to replace the identified bad die 14 (i.e., one set of pads connects the repair die 18 to replace the bad die 14, while the other sets of pads can connect the repair die 18 to replace other dice 12 if they are bad). The repair solution is stored in a computer system 22 in association with a unique identification (ID) code of the MCM 10 read during testing. This ID code may be, for example, a bar code, an Optical Character Recognition (OCR) code, an optically readable punch hole code, or an electronically readable laser fuse code embedded in the PCB 16.
    [17] 17. Once the repair solution is generated, the MCM 10 moves on to a rework station, where the bad die 14 is isolated or disabled by cutting conductive traces (FIG. 4) on the PCB 16 connected to the bad die 14, or by shorting such conductive traces together in order to bring all inputs and outputs of the bad die 14 to a high-impedance state (e.g., by pulling the RAS* input of a DRAM permanently high).
    [18] 18. After the rework station, the MCM 10 moves to a die attach station, where the repair die 18 is attached at the repair site 20 shown in FIG. 3. The particular repair site 20 used as shown in FIG. 3 is dedicated ti repairing any bad dice among the four dice 12 (including the bad die 14) shown at the top of the MCM 10 in FIG. 3, while the other repair site 20 is dedicated to repairing any bad dice among the four dice 12 shown at the bottom of the MCM 10 in FIG. 3. Of course, it will be understood that this invention is not restricted to the configuration of repair sites and dice shown in FIG. 3. Rather, this invention includes within its scope MCMs having more or less than the eight dice shown in FIG. 3, and having more or less than the two repair sites shown in FIG. 3.
    [19] 19. Once the repair die 18 is attached, the MCM 10 moves to a wire-bonding station. There, a wire-bonding machine reads the unique ID code of the MCM 10, accesses the repair solution stored in the computer system 22 in association with this ID code, and wire bonds the repair die 18 accordingly. As a result, the opportunity for human error in selecting the appropriate repair solution is minimized or eliminated.
    [20] 20. As shown in FIG. 4, the die 12 is wire-bonded to bond pads 30 on the surface of the PCB 16, while the repair die 18 is wire-bonded to one of multiple sets of bond pads and conductive traces 32 on the same surface.
    [21] 21. Although the present invention has been described with reference to a particular embodiment, the invention is not limited to this embodiment. For example, while the various steps of this embodiment have been described as occurring in a particular order, it will be understood that these steps need not necessarily occur in the described order to fall within the scope of the present invention. Thus, the invention is limited only by the appended claims, which include within their scope all equivalent methods that operate according to the principles of the invention as described.
    权利要求:
    Claims (8)
    [1" id="US-20010000489-A1-CLM-00001] 1. A method of wire-bonding a repair die in a multi-chip module (MCM), the method comprising wire-bonding the repair die in accordance with a wire-bonding repair solution generated during prior testing of the MCM.
    [2" id="US-20010000489-A1-CLM-00002] 2. A method of repairing a multi-chip module (MCM) having a defective integrated circuit (IC) die, the method comprising:
    generating and storing a wire-bonding repair solution for the MCM;
    disabling the defective IC die;
    attaching a repair IC die to the MCM;
    accessing the stored repair solution; and
    wire-bonding the repair IC die in accordance with the accessed repair solution.
    [3" id="US-20010000489-A1-CLM-00003] 3. The method of
    claim 2 , wherein the act of storing the repair solution comprises storing the repair solution in a computer system.
    [4" id="US-20010000489-A1-CLM-00004] 4. The method of
    claim 2 , wherein the act of disabling the defective IC die includes at least one of the following acts: electrically disconnecting the defective IC die from the MCM, and causing all inputs and outputs of the defective IC die to enter a high-impedance state.
    [5" id="US-20010000489-A1-CLM-00005] 5. The method of
    claim 2 , wherein the act of generating a wire-bonding repair solution comprises generating a repair solution that indicates which of several sets of bonding pads on a surface of a substrate of the MCM the repair IC die should be wire-bonded to.
    [6" id="US-20010000489-A1-CLM-00006] 6. A method of repairing a multi-chip module (MCM) having a defective integrated circuit (IC) die, the method comprising:
    automatically generating and storing a repair solution for the MCM;
    attaching a repair IC die to the MCM;
    wire-bonding the repair IC die in accordance with the stored repair solution.
    [7" id="US-20010000489-A1-CLM-00007] 7. The method of
    claim 6 , wherein the act of attaching the repair IC die comprises attaching the repair IC die at one of at least two repair sites on the MCM.
    [8" id="US-20010000489-A1-CLM-00008] 8. The method of
    claim 6 , wherein the act of generating a repair solution comprises generating a repair solution that indicates which of several sets of bonding pads on a surface of a substrate of the MCM the repair IC die should be wire-bonded to.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6379983B2|2002-04-30|Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module
    US7502659B2|2009-03-10|Sorting a group of integrated circuit devices for those devices requiring special testing
    US7155300B2|2006-12-26|Method for using data regarding manufacturing procedures integrated circuits | have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
    US7875821B2|2011-01-25|Method for sorting integrated circuit devices
    KR20010034519A|2001-04-25|Non-lot based method for assembling intergrated circuit devices
    US7885782B2|2011-02-08|Method in an integrated circuit | manufacturing process for identifying and redirecting ICs mis-processed during their manufacture
    US7276672B2|2007-10-02|Method for sorting integrated circuit devices
    US6301121B1|2001-10-09|Direct-chip-attach | multiple chip module | with repair-chip ready site to simplify assembling and testing process
    US7394268B2|2008-07-01|Carrier for test, burn-in, and first level packaging
    US7561938B2|2009-07-14|Method for using data regarding manufacturing procedures integrated circuits | have undergone, such as repairs, to select procedures the ICs will undergo, such as additional repairs
    EP1081757B1|2016-12-07|Multichip module packaging process for known good die burn-in
    US6557244B1|2003-05-06|Wafer level board/card assembly apparatus
    KR100312809B1|2001-12-28|Recoverable Memory Modules and How to Recover Memory Modules
    KR100234025B1|1999-12-15|Module test apparatus
    同族专利:
    公开号 | 公开日
    US6379983B2|2002-04-30|
    US6395566B2|2002-05-28|
    US20010034080A1|2001-10-25|
    US6238942B1|2001-05-29|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20040164393A1|2001-02-22|2004-08-26|Rambus, Inc.|Stacked semiconductor module|
    US20070176331A1|2005-03-10|2007-08-02|Husky Injection Molding Systems Ltd.|Post-Molding Molded Article Conditioning Apparatus with a Selectively Controlled Transfer Flow Structure and a Related Method|
    GB2541970A|2015-09-02|2017-03-08|Infiniled Ltd|Display manufacture|
    GB2544728A|2015-11-17|2017-05-31|Oculus Vr Llc|Redundancy in inorganic light emitting diode displays|
    US20170350521A1|2016-06-06|2017-12-07|Honda Motor Co., Ltd.|Fuel cutoff valve|JPH0574909A|1990-12-17|1993-03-26|Asia Electron Inc|Wafer test method|
    US5137836A|1991-05-23|1992-08-11|Atmel Corporation|Method of manufacturing a repairable multi-chip module|
    JPH05121496A|1991-10-25|1993-05-18|Nec Corp|Removing method for defective chip|
    JPH06310581A|1993-04-27|1994-11-04|Hitachi Ltd|Inspection method and equipment for semiconductor memory device|
    US5539752A|1995-06-30|1996-07-23|Advanced Micro Devices, Inc.|Method and system for automated analysis of semiconductor defect data|
    US5796746A|1995-12-22|1998-08-18|Micron Technology, Inc.|Device and method for testing integrated circuit dice in an integrated circuit module|
    US5807762A|1996-03-12|1998-09-15|Micron Technology, Inc.|Multi-chip module system and method of fabrication|
    US5723907A|1996-06-25|1998-03-03|Micron Technology, Inc.|Loc simm|
    US5927512A|1997-01-17|1999-07-27|Micron Technology, Inc.|Method for sorting integrated circuit devices|
    US5844803A|1997-02-17|1998-12-01|Micron Technology, Inc.|Method of sorting a group of integrated circuit devices for those devices requiring special testing|
    US5915231A|1997-02-26|1999-06-22|Micron Technology, Inc.|Method in an integrated circuit manufacturing process for identifying and redirecting IC's mis-processed during their manufacture|
    US5856923A|1997-03-24|1999-01-05|Micron Technology, Inc.|Method for continuous, non lot-based integrated circuit manufacturing|
    US5907492A|1997-06-06|1999-05-25|Micron Technology, Inc.|Method for using data regarding manufacturing procedures integrated circuits have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs|
    US6238942B1|1998-04-07|2001-05-29|Micron Technology, Inc.|Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module|
    US6329832B1|1998-10-05|2001-12-11|Micron Technology, Inc.|Method for in-line testing of flip-chip semiconductor assemblies|US6238942B1|1998-04-07|2001-05-29|Micron Technology, Inc.|Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module|
    KR100315912B1|1998-04-27|2002-02-19|윤종용|Automation system using file server and method for controlling the same|
    JP3747807B2|2001-06-12|2006-02-22|ソニー株式会社|Device mounting substrate and defective device repair method|
    US6605479B1|2001-07-27|2003-08-12|Advanced Micro Devices, Inc.|Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same|
    US6764869B2|2001-09-12|2004-07-20|Formfactor, Inc.|Method of assembling and testing an electronics module|
    US6700142B1|2001-12-31|2004-03-02|Hyperchip Inc.|Semiconductor wafer on which is fabricated an integrated circuit including an array of discrete functional modules|
    US7111213B1|2002-12-10|2006-09-19|Altera Corporation|Failure isolation and repair techniques for integrated circuits|
    KR100723486B1|2005-05-12|2007-05-30|삼성전자주식회사|Memory module having SIMM/DIMM structure and memory system|
    TW200717680A|2005-07-19|2007-05-01|Koninkl Philips Electronics Nv|Method of manufacturing a system in package|
    JP4450046B2|2007-10-05|2010-04-14|ソニー株式会社|Manufacturing method of electronic component substrate|
    US20110156033A1|2009-12-31|2011-06-30|Stmicroelectronics Asia Pacific Pte. Ltd.|Method and system for tracing die at unit level|
    JP5811803B2|2011-11-22|2015-11-11|住友電気工業株式会社|Semiconductor device and manufacturing method of semiconductor device|
    法律状态:
    2005-10-07| FPAY| Fee payment|Year of fee payment: 4 |
    2009-09-30| FPAY| Fee payment|Year of fee payment: 8 |
    2013-12-06| REMI| Maintenance fee reminder mailed|
    2014-04-30| LAPS| Lapse for failure to pay maintenance fees|
    2014-05-26| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2014-06-17| FP| Lapsed due to failure to pay maintenance fee|Effective date: 20140430 |
    优先权:
    申请号 | 申请日 | 专利标题
    US09/056,408|US6238942B1|1998-04-07|1998-04-07|Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module|
    US09/734,383|US6379983B2|1998-04-07|2000-12-11|Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module|US09/734,383| US6379983B2|1998-04-07|2000-12-11|Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module|
    [返回顶部]