• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    "PROCESS CONTROL APPARATUS" includes two transducers for measuring two parameters of the process, and a memory unit to which the outputs from the transducers are fed. The memory unit produces an output dependent on the values of the two parameters, this output being binary, and being coupled to a counter which also receives clock pulses. The counter samples the memory unit output, and produces an output pulse when the clock pulse reading is equal to the sample reading. The output pulses are then used to control the process.
    公开号:SU904537A3
    申请号:SU721862674
    申请日:1972-12-20
    公开日:1982-02-07
    发明作者:Майкл Айронсайд Джон；Муррей Бертиоли Майкл；Барри Ходгсон Дункан；Вильямс Малькольм
    申请人:Джозеф Лукас (Электрикал)Лимитед (Фирма)；
    IPC主号:
    专利说明:

    (5) DEVICE FOR AUTOMATIC CONTROL OF THE PRODUCTION PROCESS
    one
    The invention relates to devices for automatic control of the production process, in which the process is controlled by an input pulse, the duration of which is controlled by the progress of the process, the values of at least two parameters related to the production process and be applied, for example, in the jo system of fuel injection of an internal combustion engine.
    A device for automatic control of the production process is known, in which the controlling effect is a function of two parameters.
    Closest to the proposed. is a device containing a plurality of generators of one-dimensional AND functions, interpolation devices and digital-analogue converters with corresponding links 2},
    A disadvantage of the known devices is the complexity of the construction.25
    The purpose of the invention is to simplify the device.
    The goal is achieved by the fact that in the device containing a memory the first and second groups of inputs are connected respectively to the outputs of the first and second decoders, the inputs of which are connected respectively to the outputs of the first and second adders, the sensors of the first and second parameters, and the outputs of the sensor of the first parameter are connected through the code converter with the first group of inputs of the first adder, the sensor outputs of the second parameter are connected to the first group of inputs of the second adder, output counter , a group of inputs of which is connected to a group of code outputs of a memory device, the first output of which is connected to the first input of a shaper-. sa and the first input element And, and the second output - with the second input element And, the output of which is connected
    with the output of the output counter and the second input of the pulse generator, the output of which is connected to the first input of the control unit connected by two-way communications with the output counter and the counter of the samples, the input of the control unit being the input of the device clock, and the output connected to the triggering unit Introduced an increment counter and an increment decoder, the first and second groups of outputs of which are connected to the second groups of inputs of the first and second adders, respectively, and the outputs of the increment counter are connected to input pr.irascheny decoder rows, one of the increment of the counter output is connected to the third input of the pulse shaper, increments the counter input coupled to a corresponding output control blokach.
    Figure 1 shows the diagram of the device; figure 2 - diagram of the storage device.
    The proposed device contains a storage device 1, the sensor
    2 first parameter converter
    3 codes, the first adder C, the first decoder 5, the sensor 6 of the second parameter, the second adder 7, the decoder 8, the decoder 9 and the increment counter 10, the output counter 11, element 12, the counter 13 counts, the start block, the control unit 15, the driver 16 impulses, inputs
    17 and 18 and the outputs 19 of the storage device (memory) 1.
    The memory device 1 (Fig. 2) contains groups of switches 20 and groups of crossing wires 21 forming a diode array.
    Positions 22 and 23 in Figure 1 designate the clock inputs of the device.
    The device works as follows.
    Sensor 2 provides the output signal as a code group of seven bits in the binary code Gre. This signal is sent to converter 3, which converts the binary signal Gre to a direct binary signal and transmits this signal to adder k. The four most significant binary digits in the adder C are transmitted to the decoder 5, which outputs a signal to one of the inputs 17. The other sensor 6 outputs a direct output binary signal of seven binary units, representing the second parameter. This signal arrives at the adder 7, and the four most significant bits are fed to the decoder 8, which outputs a signal to one of the inputs 18. Then the memory 1 outputs the output signal to the outputs 19, the value of which depends on the magnitude of the two parameters. The output signal from the outputs 19 is transmitted to the counter 11, where the element 12 is switched on between the memory 1 and the counter 11. When the counter 11 receives the trigger signal, it is connected to the outputs 19 and outputs a count depending on the code on the outputs 19. Then the counter 11 disconnects from the outputs 19. An input 22 is connected to the counter 11, which is powered by fixed-frequency clock pulses, after which the signal stored in the counter 11 is counted. Upon termination of the counter, the counter 11 outputs a signal that goes to the control unit, which again starts the counter 11 vsl Therefore, the counter 11 again selects the signal at the outputs 19. Then the counting is resumed and thus, the counter 11 automatically selects the signals at the outputs 19 again and outputs output pulses to the control unit. The time interval between these output pulses depends on the signal at the outputs 19.
    The output from reader 11 also goes to counter 10, which controls decoder 9, which is connected to adders 4 and 7, and the contents of decoder 9 is added to the low-order bits transmitted to adders 4 and 7, and may, depending on the indicators in adders and and 7 force one of the four most significant digits to change, and any of them causes a change in the output signal of memory 1.
    权利要求:
    Claims (2)
    [1]
    1. Circle E.K. and others. Digital controllers. M.-L., Energie, 1966,
    with. 21, Fig. 8-13.
    [2]
    2. US Patent No., cl. 235-197, 19b7 (prototype). & connected with the input of the output counter and the second input of the pulse former, the output of which is connected to the first input of the control unit connected by two-way communication with the output counter and the counter of readings, the input of the control unit being the input of the device clock pulses and the output connected to the unit startup, characterized in that, in order to simplify the device, it contains an increment counter and an increment decoder, the first and second groups of outputs of which are connected respectively to the second groups of inputs of the first and the second combiner, the outputs of the increment counter are connected to the inputs of the increment decoder, one of the outputs of the increment counter is connected to the third input of the pulse former, the input of the increment counter is connected to the corresponding output of the control unit.
    fig 1
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    . 2
    类似技术:
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    同族专利:
    公开号 | 公开日
    GB1422324A|1976-01-28|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    NL278186A|1961-05-08|1900-01-01|
    DE1263141B|1961-06-23|1968-03-14|Continental Elektro Ind Ag|Digital controller|
    FR1380450A|1963-05-03|1964-12-04|Device generating functions of several independent variables which can be used, in particular, in industrial control, regulation and automation equipment|
    DE1272427B|1964-11-05|1968-07-11|Demag Zug Gmbh|Method and device for digital regulation or control|
    US3578960A|1966-04-06|1971-05-18|Beckman Instruments Inc|Radiation detection system with automatic sample counting rate determination|
    US3548169A|1967-03-14|1970-12-15|Fluor Corp|Process controlling digital to analog converter|
    US3621228A|1969-09-24|1971-11-16|Nasa|Digital function generator|
    US3681581A|1969-12-31|1972-08-01|Nasa|Digital control and information system|
    JPS5336108A|1976-09-16|1978-04-04|Fujitsu Ltd|Circuit connection system|GB1516302A|1974-06-18|1978-07-05|Lucas Electrical Ltd|Process control apparatus|
    GB1503338A|1974-11-30|1978-03-08|Felten & Guilleaume Carlswerk|Methods of and apparatuses for measuring temperature and evaluating its effects on a process|
    JPS5725119B2|1976-03-22|1982-05-27|
    JPS5642233B2|1976-12-23|1981-10-03|
    US4968864A|1978-06-05|1990-11-06|Keiichiro Doi|Magnetic card control microwave oven|
    JPS558562A|1978-07-04|1980-01-22|Sharp Corp|Electric oven|
    SE430106B|1979-06-18|1983-10-17|Ibm Svenska Ab|Hierarchical Computer System|
    US4276770A|1979-07-27|1981-07-07|Ethyl Corporation|Rapid octane rating|
    US4291355A|1979-07-30|1981-09-22|General Electric Company|Programmable overload circuit|
    JPS6279501A|1985-10-03|1987-04-11|Toto Ltd|Heater control device|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    GB5950671A|GB1422324A|1971-12-21|1971-12-21|Process control apparatus|
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