• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a work pulse again connects the charge source with each of the capacitors.
    公开号:SU843787A3
    申请号:SU772467160
    申请日:1977-03-30
    公开日:1981-06-30
    发明作者:Дэвид Прайсер Уилбер
    申请人:Интернэшнл Бизнес Машинз Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    one . The invention relates to computing, in particular, to J CT memory devices on semiconductor elements. In the technique of integrated circuits in the manufacture of semiconductor memory devices, the most compact are devices — a, in which memory cells have a minimum of elements. High density can be obtained with capacitive memory cells, which consist only of a storage capacitor and an electronic key. A semiconductor matrix storage device is known that contains a memory chip, which is switched by a field-effect transistor. bit tires with silicon oxide insulating layers, and dictionaries above the bit tires in an orthogonal direction are located Expansion accumulator field of application due to the possibility of using it in the storage devices with recording-reading and recording signals induced inversion capacitors used as memory elements. This goal is achieved by the fact that a semiconductor matrix accumulator containing a boron doped P-conductivity semiconductor substrate — in which depletion areas are located, over which parallel discharge buses with insulated silicon oxide layers are placed, and the discharge buses in the orthogonal direction vocabulary tires are located, contains in the semiconductor substrate of p-conductivity two doped phosphorus or MEL com-bus diffusion buses of n-conductivity, placed on the ends of the substrate p There are two insulating layers located between the P-conductivity semiconductor substrate and the discharge buses, the first layer, made of silicon dioxide, is placed on the surface of the semiconductor JS X
    ,, p
      FI.6
    Compiled by V.Vakar Editor E.Dichinska Tehred A.Ach; Proofreader O. Bilak
    Order 5086/49 Circulation 645Subscription
    VNIIPI USSR State Committee
    for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. 4 / &
    Branch PPP Patent, Uzhgorod, st. Project, 4
    Date: 03/05/2001
    Number of pages: 4
    Previous document: SU 843787
    Next Document: SU 843789
    权利要求:
    Claims (1)
    [1]
    20 For which the fixed longitudinal bars have grooves 8, and the main transverse bar and extenders - grooves 9. A side trailer 10 is attached to the extender to assemble the implement in the transport position. The frame of the gun, consisting of the main transverse beam 1, extension cords 5, central longitudinal beam 2 and fixed bars 4, rests on pneumatic self-aligning wheels 11. Between the wheels and the frame are installed hydraulic
    类似技术:
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    US7609573B2|2009-10-27|Embedded memory databus architecture
    US4319342A|1982-03-09|One device field effect transistor | AC stable random access memory | array
    US5294819A|1994-03-15|Single-transistor cell EEPROM array for analog or digital storage
    US6809967B2|2004-10-26|Data writing method for semiconductor memory device and semiconductor memory device
    US5596523A|1997-01-21|Electrically erasable programmable read-only memory with an array of one-transistor memory cells
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    US4336603A|1982-06-22|Three terminal electrically erasable programmable read only memory
    US6845030B2|2005-01-18|Nonvolatile ferroelectric memory device and method of fabricating the same
    KR100786428B1|2007-12-17|Ferroelectric memory device
    KR19980064679A|1998-10-07|Serial Access Semiconductor Memory
    US4300210A|1981-11-10|Calibrated sensing system
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    EP0083418B1|1988-10-26|Non-volatile dynamic ram cell
    US4301519A|1981-11-17|Sensing technique for memories with small cells
    US3781831A|1973-12-25|Read only memory utilizing floating gate transistors and method of programming
    USRE32236E|1986-08-26|One device field effect transistor | AC stable random access memory | array
    WO1988002174A3|1988-07-28|Nonvolatile memory cell array
    US4652898A|1987-03-24|High speed merged charge memory
    Chawla et al.1976|A cross-point MNOS capacitor memory
    WO2021041029A1|2021-03-04|Erasing memory
    EP0003413A3|1979-08-22|Improvements relating to semiconductor memories
    Mohsen1979|Vertical charge-coupled devices
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    同族专利:
    公开号 | 公开日
    AU2365177A|1978-09-28|
    AU501754B2|1979-06-28|
    DE2705992B2|1978-05-24|
    JPS5634953B2|1981-08-13|
    ES457351A1|1978-02-01|
    CH607232A5|1978-11-30|
    JPS52119828A|1977-10-07|
    AT377378B|1985-03-11|
    DD130698A5|1978-04-19|
    SE417381B|1981-03-09|
    FI63127C|1983-04-11|
    NL7701055A|1977-10-04|
    US4080590A|1978-03-21|
    BR7701807A|1978-01-24|
    SE7702445L|1977-10-01|
    DE2705992A1|1977-10-13|
    FI63127B|1982-12-31|
    FI770896A|1977-10-01|
    DE2705992C3|1979-01-25|
    ATA97377A|1984-07-15|
    IT1113763B|1986-01-20|
    BE851845A|1977-06-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3852800A|1971-08-02|1974-12-03|Texas Instruments Inc|One transistor dynamic memory cell|
    US3931465A|1975-01-13|1976-01-06|Rca Corporation|Blooming control for charge coupled imager|
    US3987474A|1975-01-23|1976-10-19|Massachusetts Institute Of Technology|Non-volatile charge storage elements and an information storage apparatus employing such elements|
    US3979734A|1975-06-16|1976-09-07|International Business Machines Corporation|Multiple element charge storage memory cell|
    US3986180A|1975-09-22|1976-10-12|International Business Machines Corporation|Depletion mode field effect transistor memory system|US4230954A|1978-12-29|1980-10-28|International Business Machines Corporation|Permanent or semipermanent charge transfer storage systems|
    US4287576A|1980-03-26|1981-09-01|International Business Machines Corporation|Sense amplifying system for memories with small cells|
    US4301519A|1980-05-02|1981-11-17|International Business Machines Corporation|Sensing technique for memories with small cells|
    US4445201A|1981-11-30|1984-04-24|International Business Machines Corporation|Simple amplifying system for a dense memory array|
    US4574365A|1983-04-18|1986-03-04|International Business Machines Corporation|Shared access lines memory cells|
    US4652898A|1984-07-19|1987-03-24|International Business Machines Corporation|High speed merged charge memory|
    US4648073A|1984-12-31|1987-03-03|International Business Machines Corporation|Sequential shared access lines memory cells|
    US5589707A|1994-11-07|1996-12-31|International Business Machines Corporation|Multi-surfaced capacitor for storing more charge per horizontal chip area|
    US7031136B2|2002-04-09|2006-04-18|Ngimat Co.|Variable capacitors, composite materials|
    US9595526B2|2013-08-09|2017-03-14|Apple Inc.|Multi-die fine grain integrated voltage regulation|
    US10468381B2|2014-09-29|2019-11-05|Apple Inc.|Wafer level integration of passive devices|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US05/672,197|US4080590A|1976-03-31|1976-03-31|Capacitor storage memory|
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