• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A coupling for several active computing devices, one of which is a master and the rest slave units, involves couplers, address, control, and data highways combined to enable a synchronous data exchange using an interrupt method. It is of the simplest possible construction, low circuit complexity and high efficiency and makes extensive use of standardised component groups. Bidirectional programmable input/output gate circuits for each computer contain data, address, and control sections and are interconnected via highways. Special control circuits prevent accessing conflicts.
    公开号:SU1337902A1
    申请号:SU797770531
    申请日:1979-04-10
    公开日:1987-09-15
    发明作者:Вольфгенг Хенцлер；Карл Херрманн；Эберхард Круг；Вольфганг Шене；Гюнтер Волленберг
    申请人:Феб Нумерик "Карл Маркс" (Инопредприятие)；
    IPC主号:
    专利说明:

    The invention relates to the field of computing and can be applied, in particular, when using microprocesses for various tasks, for example, to control processing and processing processes that operate in real time.
    A system for connecting several computing devices is known. In DE-OS 24 46 970, several BbRHC-powered devices operating independently of one another are connected to a common storage device via an interface, the sequence of the computing devices when accessing the storage device is established by the priority determining unit.
    With this kind of connection, the exchange of data, 2-arr, direct and infinite is always carried out through a common storage device.
    Peripheral-type connections are known through special mating control devices. According to DE-OS 26 45 341, an interface device is arranged for each connection between the two computing devices. It can be designed as a compact, self-contained unit, or it can be included in each connected computing device.
    In devices with more than two computing devices, systems of several computing devices can be implemented according to the structure of a ring or a star.
    The disadvantage of such computational ycTpoficTB systems is that for each connection between two computing devices, separate interfaces are required.
    The purpose of the invention is to create an interconnection scheme for a system of several computing devices, so that at very low circuit design and construction costs a high performance is achieved and at the same time a cost-effective, simply manageable design with a high degree of unification is provided.
    The invention is based on the task of creating a possible, by its simple design, interface systems for several active computing devices operating simultaneously and autonomously on the common task.
    of which one is provided as the main one, the rest as subordinate computing devices with programmable input-output selector circuits included in them, which would allow asynchronous connections of separate computing devices to be made by calling an interrupt.
    The goal is achieved by the fact that each computing device is connected to a common collecting line through a selector I / O circuit.
    for data and address information, and that each input selector circuit through a specific control circuit for transmitting control signals is connected to a collecting line for asynchronous data exchange between the main computing device and slave computing devices, and the selector circuit for the main computing device I / O has its data direction output controlled by it, which is connected to the remaining I / O selector circuits to set the direction nor the transmission and priority of the main computing device.
    The input / output selector scheme of the control computing device has a device for determining the priority of several simultaneously accessing slave computing devices.
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    The control circuit has a conjunctive logical link for the data direction signal sent by the main computing device and received by slave computing devices, and for the ready-to-wake-up signal, the output of which is connected to a second conjunctive logic link with a time delay characteristic. The second input of a conjunctive logical link with a time characteristic is connected to an input for an I / O readiness signal, its output is connected via a third logic element to an output for a data direction signal for the main computing device, its negation for the slave computing devices is connected to the inputs of the I / O call other computing devices, and through the fourth logical link, which by its other input is connected to the second input of the second conjunctive logical link and water for the input signal readiness signal, the second input of the conjunctive logic link is connected to the input call of the input-output selector circuit of the input / output slave of the connected computing device.
    The control circuit has an activation input, through which it is called by the computing device through an appropriate input / output selector circuit for data exchange. Each input / output selector scheme has a time scheme for determining the waiting time, during which the data word sent or received by it must be received or sent by the computing device involved in the data transfer, and the time signal programmed by the output computing device error in case of failure of the confirmation signal during the waiting time from the computational device
    Slave computing devices are designed to manage different process steps or other tasks that are the same or different from one another. Their functions are controlled and coordinated by the main computing device. The search for data transmission can be carried out by one of the slave computing devices or the main computing device by means of the address and control lines, which are connected to the collecting lines through the selector-output device.
    FIG. 1 is a block diagram for four computing devices connected to each other; Fig. 2 is a block diagram of selectable input-output circuits connected by collecting lines; in fig. 3 — logical control circuit; 4 is a signal diagram for a data transmission device.
    Figure 1 shows a system of several computing devices with one main computing device MR1 and three slave computing devices i-fRZ-MRA. All computing devices MR1MR4 are interconnected by means of collecting lines and connecting bus B1. Each MR1-MRA computing device consists of a central data processing device ZVE1-ZVE4, a Dlll-DtJ4 data transfer device with an EA1-EA4 input-output selector circuit and a Spl-Sp4 storage device, which are equipped with AE1-AE4 and AA1 input and output batteries -AA4.
    Figure 2 shows the selector circuits EA1-EA4 connected by collecting lines for data B11, addresses B12, and control signals of the HS field.
    The selector input-output schemes EA1-EA4 are divided into the PortA data part and the PortB address part.
    The EA1-EA4 input / output selector circuits are built for bi-directional operation. Each selector circuit EA1-EA4 has a control circuit LS1-LS4, which are interconnected by a collecting line (HS bus). The computing device MR1-MR4, which requires data exchange, through the PortB of its selector input-output scheme EA1-EA4 selects the participant he needs.
    FIG. 3 shows the logical control circuit diagram LS.
    EA denotes the communication input of the input-selector selector circuit, the HS field denotes the collecting LINE; The bo output, which sends the data direction signal, is connected to the inverter N1 and to the collecting line (HS).
    N1 inverter output and bo output
    selector circuit input-output EA through switch S1 connected to the input element HUl and through the second inverter N2 - to the input element I2.
    In each MR1-MR4 computing device, the design groups are interconnected by a common bus B21-B24. The slave computing devices MR2-MR4 manage the processing of the same or different, simultaneously processed programs. With the encouragement of such programs, machining processes, for example, are controlled. To do this, the MR2 computing device can be transferred control of the input from the punch card reader, keypad or other programming sensor and the viewport to alphanumeric
    indicator, video display, printer, punch device, or other data output device. Other slave computing devices MR3 and MRA can be used to process control information and response signals. For this, for example, the slave computing device MR3 can, in turn, serve as the master computing device for lower-rank devices that are also communicating with each other via the connection bus B1. These slave computing devices can be used, for example, to control individual axes of the processing machine. Subordinate computing devices MR2, MR3, MR4 with this design can be used. Also for additional tasks, such as inspection and control functions, control program and the like.
    The main computing device MR1 coordinates the work of the slave computing devices MR2-MR4 provides them with information from its storage device SP 1 and can also perform the control functions itself. In this case, the data transfer is always between the controlling computing device MR1 and one of the slave computing devices MR2-MR4.
    If, for example, data is required to be transferred from the MR1 master computing device to the MR3 slave computing device, then the MR1 computing device, via the selector IO device of EA1 of its data transfer device DiJl, sends a control signal and an address signal to the B1 connecting bus, which by the input selector circuit The BAS output of the DiJ 3 data transmission devices will be recognized as defined for the MR3 slave computing device. As long as the slave MR3 is able to receive data, i.e. it does not deal with the execution of other priority tasks through the EAZ I / O selector scheme of its DtJ3 data transfer device, the B1 connection bus and the EA1 I / O input / output selector circuit of the DUl data transmission device.
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    the main computing device MR1 it sends signals to receive. In this way, a connection is established between the two computing devices, and the data transfer can begin.
    The transmitted information is first found as a layer-built output unit in the lateral battery of the MR1 main computing device. The first transmitted word is recorded in the word counter of the data transfer device Dl) 3 of the receiving subordinate computing device MR3
    the number of transmitted words of the output block, from which each inserted word is counted during the subsequent transmission. The last transmitted word has a special binary structure. As soon as the word counter counts zero, it dials the comparison device, which the last transmitted word checks for error. This will receive a statement about the correctness of the transfer of the output unit.
    The transfer of data from the slave computing device MR2-MR4 occurs in the same way in the opposite direction. In this case, the main computing device MR1 determines with which of the slave computing devices MR2 MR4 it will first communicate when they simultaneously call the main computing device I d.
    If, for example, data is to be transferred from the MR primary Q device to the MR2 slave computing device, then the MR1 primary computing device requires data exchange. The signals sent by the main computing device MR1 are fed to the corresponding inputs of the PortB selector I / O EA2 and EA4. At the same time, the main computing device MR1, through its selector circuit of the I / O EA1, wakes up its control circuit LSI and sends it a signal of the direction of input-output data from the main computing device MR1.
    The called slave computing device MR2 recognizes the call, sends an acknowledgment to the host computing device G1, and puts its control scheme into operation in the state set
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    my data direction signal. In the LSI and LS2 control circuits, the signals are associated with the data input or data output RDY signal. The master computing device sending the data sends a corresponding ready signal to the control line (HS bus) for control signals. The data receiving slave computing device MR2 forms in its control circuit LS2 a send signal (data copy) which is sent to the collecting line (HS bus) for control signals. In response, this is the transfer of data from the PortA of the selector EA1 input-output scheme of the main computing device MR1 through the collecting data line B11 to the PortA selector scheme of input-output EA2 of the slave computing device MR2. In the same way, the slave computing device MR2-MR can cause data exchange with the master computing device MR1. The master computing device MR1 sets the data direction signal b to a state that indicates the direction of transmission from the slave computing device MR2 to the master computing device MR1.
    The second input of the HUl element is connected to the RDY output of the Shg element, the first input of which is connected to the ARDY output of the input selector circuit EA, the second input of which is connected to the output Lg of the input selector circuit EA. The output of the Shg element is connected to the input of the I & 3 element and a conjunctive connection to the input of the switching element with a time delay MV. The second input of the SHZ element is connected disjunctively to the output of the element II2 and to the input a collection line of control signals (HS bus) for the PSTB I / O demand signals in such a way that a bi-directional action is provided. The output of the SHZ element is connected to the input of the I / O command STB of the EA I / O selector circuit. The second input element II2 is connected to the output of the switching element with an exposure time of the data exchange process.
    change MV. For the main computing device, the switch SI includes an input A for the slave computing devices — an output of the N1 inverter.
    The letter A is the side of the transmitting computing device and the letter E is the side of the receiving computing device. Exchange yes
    The data direction signal b is sent to the control computing device. The control circuit LS is output through the input b | .
    As long as the corresponding computing device sprinkles a signal through the ARDY input of the input-output selector circuit, it arrives at the output of the Shg element, which is output from the Sh. Based on this, the I1 element, together with the data direction signal B, forms the ready signal of the data output PRDY, which is sent to the collecting line (HS bus). Signal
    directing data b in the LSI control circuit for the main villus; the snoring device MR1 from the corresponding output of the selector input-output scheme EA1 through the switch S1 falls directly into the element Ш1, while in the control circuits LS2-LS4 it falls into the element Ш1 from the collecting line (HS bus) via the inverter and switch S1. The output readiness signal PRDY sent to the collecting line (HS bus) identifies the corresponding computing device MR1-MR4 as an information transmitter.
    To generate a STB I / O request signal, a switching element with a time delay MV from the PRDY data output readiness signal sent by the MR1-MR4 computing device ready for data output and an RDY output readiness signal sent via the EG element from the EA I / O selector circuit, forms a signal of short duration, during which the exchange of the data word should occur. This signal is connected by the element Ш2 with the negative signal of the direction of the data b and via the caused element ШЗ gets into the selector input-output scheme ЕА of the receiving computer device MRl-l-IRA and from the output of the element Ш2 directly through the collecting line (bus HS) as The PSTB signal enters the data computing device fiRl-MRA.
    Fig 4 is a sequence.
    The letter A is the side of the transmitting computing device and the letter E is the side of the receiving computing device. The data exchange starts with a call R in the transmitting side A, which appears on the receiving side as a signal R, which sets the input state there. For a given waiting time t, a confirmation signal O must be sent by the receiving party E, which is received by the transmitting side And as Q, Otherwise, there is no data link connection.
    With acknowledgment Q, the call signal R on the transmitting side is cleared, and the output state of the AG is set. Then, the first one is sent, which contains the number of transmitted words within the unit, as the word AS1 and during the specified casting time t: w it is received by the receiving party. The following words, AS2-ASn-l, are recalculated and received in the same way, and the incoming signals are always transmitted for some specific time, during which they must be received. At the end of the data transfer, the word ASn is sent to verify the signaling transmission is correct. In the case of data transfer without errors, the word ASn + 1 may additionally be transmitted. During the check, the input state of the EG weft is reset.
    权利要求:
    Claims (5)
    [1]
    Invention Formula
    1, A system for connecting several operating devices, one of which functions as the main computing device, and the rest as subordinate B1, numerals, with input-viewer selector circuits connected to them, and which are interconnected via address transfer, control and data lines for each asynchronous data exchange according to the breaking principle, characterized in that each computing device through a selector I / O circuit is connected to a common collecting line for information about the data and addresses that each I / O selector circuit, through a control circuit for transmitting control signals, is connected to a collecting line for asynchronous, direct and connectionless data exchange to the melode by the main one and one of the slave ones
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    devices, and that the I / O selector circuit of the main computing device has a data direction signal output controlled by it, which is connected to the other I / O selector circuits to determine the transmission direction and priority of the main computing device,
    [2]
    2. The pop system, 1, is different in that the selector input / output circuit of the main computing device is equipped with
    to determine priority in the case of several simultaneously requesting slave computing devices,
    [3]
    3. The system of PP, 1 and 2, so that the control circuit has the first conjunctive logic element for the sent by the main computing device
    and, via the inverter, the subordinate computing device receives the data direction signal and the input-output readiness signal, the output of which is connected to the second conjunctive logic element with the Q characteristic of time delay, the second input of which is connected to the input-output readiness signal and which output through the third logic element is connected to the data direction signal for the main computing device, and its negation for the slave computing devices is connected to the inputs of the input-output call and the remaining computing devices and through the fourth logic element, which is connected by another input to the second input of the second conjunctive logic element, is connected to the input of the I / O call of the selector I / O scheme of the switched on main device.
    [4]
    4. The system of PP. 1-3, that is, the control circuit has an activation input through which it is connected to its computing device through an appropriate input viewer selector circuit for calling data exchange,
    [5]
    5. The system of PP. 1-4, this is such that each selector I / O circuit has a timing circuit for determining the waiting time during which the data word sent (received) by it
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    must be received (sent) by another, participating in the data transfer, computing device, and programmed, included by the computing device requiring data exchange
    i -M
    1337902
    12
    a timing circuit for posting an error signal in the event of a confirmation signal from a vyzgayemy computing device during the waiting time.
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    Fig 2
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    Editor I. Casard Order 4133/48
    Tehred M. Khodanych
    Corrector
    Circulation 672 Subscription
    VNIIPI State Committee (X SR
    for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d./5
    Production and printing company, f. Uzhgorod, Proektna str., 4
    - / V
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    Have
    Corrector S.Cherni
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    同族专利:
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    引用文献:
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    WO1998027690A1|1996-12-16|1998-06-25|Samsung Electronics Co. Ltd.|Method for sending e-mail messages in a local area network, and device for applying same|US3634830A|1969-06-13|1972-01-11|Ibm|Modular computer sharing system with intercomputer communication control apparatus|
    BE786342A|1971-04-15|1973-01-17|Int Standard Electric Corp|IMPROVEMENTS TO SYSTEMS USING CALCULATORS|
    US3921145A|1973-10-12|1975-11-18|Burroughs Corp|Multirequest grouping computer interface|
    US3972023A|1974-12-30|1976-07-27|International Business Machines Corporation|I/O data transfer control system|
    CA1080318A|1975-10-14|1980-06-24|Daren R. Appelt|Communication bus coupler|DE3026362C2|1980-07-11|1984-12-06|Siemens AG, 1000 Berlin und 8000 München|Device for fast block-oriented data transfer between two computers in operation|
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    FR2569290B1|1984-08-14|1986-12-05|Trt Telecom Radio Electr|PROCESSOR FOR SIGNAL PROCESSING AND HIERARCHIZED MULTI-PROCESSING STRUCTURE COMPRISING AT LEAST ONE SUCH PROCESSOR|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DD20514178A|DD142135A3|1978-05-03|1978-05-03|MORE COMPUTER COUPLING|
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