Coding or decoding byte generator

专利摘要:

公开号:SU1207407A3
申请号:SU833547557
申请日:1983-01-10
公开日:1986-01-23
发明作者:Клод Гийу Луи；Ле Бри Раймон；Ле Рес Амбруаз
申请人:Этаблиссман Пюблик Де Диффюзьон Ди "Теледиффюзьон Де Франс" (Фирма)；Лъъэта Франсэ Репрезанте Пар Ле Министр П.Т.Т./Сантр Насьональ Дъъэтюд Де Телекоммюникасьон/ (Фирма)；
IPC主号:

专利说明:

A swarm pseudo-random sequence generator consists of seven elements EXCLUSIVE OR, seven. registers and adder modulo 127, with the first inputs of the first second, third, fourth, fifth, sixth and seventh elements EXCLUSIVE OR being the sixth, seventh, eighth, first, second, third and fourth inputs of the generator of encoding or decoding bytes respectively .., the output of the j-ro element EXCLUSIVE OR (where j is 1, 7) connect to the j-th input of the first register, the j-th output of which is connected to the JM input of the second register and the first group of inputs modulo 127, j-th output the second register is connected to the (J - 1) -th input of the second group of the adders modulo 127, the jth output of which is connected to the JM input of the third register, the jth output of which is connected to the jth input of the fourth register and is the output of the second pseudo-random sequence generator, the jth output of the fourth register is connected to the JM input The 5th register, the jth output of which is connected to the jth input of the sixth register, the jth output of the sixth register connected to the jth input of the seventh register, the jth output of which is connected to the second input of the j-ro element EXCLUSIVE OR, invention refers to devices that form encoding or decoding bytes, and can be used in video recording systems
The aim of the invention is to increase speed by reducing the duration of the formation and increasing the length of the sequence of bytes. ,
FIG. 1 shows a structural electrical circuit for a generator of encoding or decoding bytes; FIG. 2 - time diagrams that show his work.
07407
the pseudo-random sequence generator consists of six EXCLUSIVE OR elements, - five registers and a modulo 31 adder, the first inputs of the first, second, third, fourth and fifth elements of the EXCLUSIVE OR are the fourth, fifth, sixth, seventh and the eighth inputs of the generator of encoding and decoding bytes, the output of the K-th element of the UTILITTING OR (where K 1, ..., 5) is connected to the K-input of the first register, the K-th output of which is connected to the K-th input of the second
the register and the first group of inputs of the adder modulo 31, the K-th output of the second register is connected to the K-m input of the third register and the first group of inputs of the sixth element EXCLUSIVE OR, the K-th output of the third. register is connected to the K-th input of the second group of inputs of the adder
modulo 31, the K-th output of which is connected to the K-th input of the fourth register, the K-th code of which is connected to the K-th input of the fifth register and the second group of inputs of the sixth element EXCLUSIVE OR, the output of which is the output of the third pseudo-random generator sequence, and the K-th output of the p register is connected to. the second input of the Kth element is EXCLUSIVE OR.
The generator contains the first, second and third generators 1-3 of a pseudo-random sequence, the corresponding inputs of which are -. with inputs 4-11 of the generator of encoding or decoding bytes, the first and second elements AND 12 and 13, the element OR 14, the adder 15 modulo 2, the generator 16 clock pulses, having output 17 and block
18 controls with outlets 19-21. The first generator 1 consists of six elements EXCLUSIVE OR 22-21 seven registers 28-34 and adder 35
modulo 31, the second generator 2 consists of seven elements EXCLUSIVE OR 36-42, seven registers 43-49 and adder 50 modulo 127. The third generator 3 consists of six elements EXCLUSIVE OR 51-56, five registers 57-61 and adder 62 modulo 31.
The generator works as follows.
The inputs 4-11 are supplied with an input signal that triggers a generator of coding or decoding bytes, which is characterized at each moment in time by a combination of states of generators 1-3, depending on the previous states of generators 1-3.
, t.,, - 1 + 2-r; .g no to module 31,
Ui i-5 2-S; , no module
 . 127 i t. + t. no module 31
where r, s and t are the states of generators 1-3, respectively;
i, j, and K are the bit indices of the corresponding generator registers 1-3. The general state of the generator of coding or decoding bytes is determined at any time by a set of words contained in registers

RA; RB; RC; RD; RE; RF; RG SA; SB; sc; SD; SE; SF; SG /, TAi TV; ts; TD; TE J
RA, RB, RC,
RE, RF, RG - the contents of the registers 32, 33, 34 28, 29, 30 and 31, respectively;
SB, SC, SD,
SF, SG - the contents of the registers 45, 46, 47, 48, 49, 43 and 44, respectively;
TV, TS,
TD, TE
- the contents of registers 60, 61, 57, 58 and 59, respectively.
In this state, 109 binary elements are distributed, distributed as follows: seven words of 5 bits each for the sequence r (registers 28-34), seven words of 7 bits each
for the sequence s (registers 43-49), five words of 5 bits each for the sequence t (registers 57-61). At time n + 1
 RD + 2RG mod 31 RA, RB / RC 0 RI, RD, RE; RF
SF + 2SG mod 127
SA;
SB; SC; SD; SE ® si; SF
TC + TE mod 31; TA, TV @ TI, TC; Td
where RI, SI and TI are the contents of the signals corresponding to the trigger signals of generators 1-3;
0 - operation EXCLUSIVE OR or at once. - -
modular addition mod 2,
mod 31. and mod 127 mean that the output of the corresponding adders 35, 50 and 62 subtract 31 or 127, if the result is strictly more than 31 or 127.
The triggering bytes RI, SI, TI appear at inputs 4-11 only at the time of startup, and inputs 4-11 are maintained in the zero state, while the generator generates encoding or decoding bytes.
The definition of the output byte is carried out depending on the conditions x using the elements EXCLUSIVE OR 27 and 56, elements AND 12 and 13, and element OR 14. Each of the five bits of the content of the SA register 45 depending on the value equal to O or 1, control the selection of the RA®RE bit or the TA © TD.
If the RA® RE bits, SA and TA®TD are written as
  .SjS, 3 ,,; ty4t tzt
then the encoding byte is written bit by bit
c, r, -s, n- s, -t, modulo
Su + Sj ty modulo
Се 0.- с, О,
Sd 0, +. ... + C at software module 2.
For decoding bytes, when the parity bit is already replaced by the correct parity bits, the three bits of the large weight are zero.
The generator, encoding or decoding bytes, is triggered using overhead information consisting of 64 binary elements K, - Kg, a row number varying from 1 to 24 and encoded in two bytes NRj and NRg, and a page number changing 001 to 999 and encoded in three bytes NP,, NP and NP ,.
The NK bytes (IK2, encoding the row number yes, are written respectively as X 8x7x6x5x4x3x2x1 and y8y7ub1 | 5 (|
4ij3Vj2ii1o For the generation of bytes of the start, the bytes H ((), H (ij8i | 7ij6ij5), H 4x3x2x1) and H (h8x7x6)) are used, obtained by Hamming coding as follows.
If we denote the various bits of such a byte H by g 8 g 7 ... 1 then we have
g7 g8 ® g6 © g4i
. g5 g6 ® g4 ® g2;
g3 g4 ® g2 Ф g8;
gi g2 ® g8 © g6:
The correspondence of the value of numbers in a hexadecimal system with the values of different bits is given in Table. one.
In this case, the bits g8, §6, g4, g2 correspond to the information bits, and the bits g7, g5, g3, g1 correspond to the redundancy bits.
Bytes 1A, ..., 1H, used for starting and translating the number of rows in the combination of binary elements K, -K, determine the following possible combination:
These eight triggering bytes make it possible to make all three RI, SI and TI triples by selecting some of the bits that make them up, and this choice is determined by the connections of the inputs of generators 1-3; these
ID (x8x7x6x5) IE K, ® NR ,; IF K © NR. IG K ® NR; Ih Kg.
Example. The process of generating triggering bytes. The service information is determined by the following eight bytes (recorded in the hexadecimal system, i.e. according to the code in Table 1):
TO
, 17i K BE; K, 62; K A9, K 65; To ZS-, K ,. 84; To 0.
Suppose that the coding series is determined using US IF NR, 45; NRg C, and that this series belongs to the page defined by ZON 01; RS 9E, NP, 15; NPg. 64, NP, 73 ..
According to the byte notation system, the code 1/5 means 0001/0101, i.e. Oh, taking into account the Hamming code given in Table. 1, 6/4 corresponds in the same way to 4, and 7/3 to 5. This page, defined by NP, 15; NPg 64 and NP, 73, therefore, is page 045.
Four bytes defining the considered series NR ,, NRz are respectively H (NR2)., H (ЫЕрр), H (NR, p, H (NR, p), if they denote respectively 4 bits of small and large weight NR and NR ,,
NR
I | F
- four bits small and large
th weight NR ,. In this case, the four bytes H (1), H (C), H (5), H (4), respectively, are according to the Hamming codes table.
triples are used dp run generators 1-3.
The values of the words RI, SI and TI in the binary and decimal systems are given in Table. 2
If byte I is written as L8 L7 L6 L5 L4 L3 L3 L, then RI is written L l 5 L3 L3 L2, SI - L ′ L L L H L L H L H L H L6 and TI - L l 5 L H L H L L H L H L H L H L L L L L L L L L L L L L L L L L I M L L L L L G L L L L G L G L L G L G L L G L G L L G L L L L G L L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G L L G L G L G L L G L L G L L G L L L L L G L L L G L C L T L R-5
At the beginning of the considered series, the generator sequentially takes into account the launching bytes. This means that each of generators 1-3 takes into account eight consecutive starting words RI, SI, or TI, which are relevant to them. The first registers 28, 43 and 57 receive these trigger words, which are then shifted to registers 29, 44 and 58, while registers 28, 43 and 57 receive the second trigger words.
A step-by-step change in the contents of the various registers depending on the change in the trigger words is given in table. 3
After processing the eighth trigger byte, the generator is ready to issue the first encoding byte. Register contents 32: RA 26; RE 0; RA®R 26 11010; register 45: SA 41, we have SA 41 01 01001; register 60: TA 13; TO 12; TA ® TDO 01 OOOOK
5 bits, received at the output of the element OR 14, 10011. Therefore, the first coding byte 93 in the hexadecimal system.
The following states are obtained using the sequences
г; „г ;, + 2.г ,. mod 31,
S;
 S-, + 2 S; , mod 127,
 J, (t
M. H-g + tk-4 ™ od 31.
The five major bits of the coding byte are obtained using
(, ®) j- (H +, ®CH)
Thirteen first coding bytes: 93, 96, 9A, 82, 1D 12, 17, 8B, 87, ID, M8, 95 ....
ten
15
20
25
thirty
35
ABOUT
10 s
D;
2074078
In the general case, denoted by d, djd are pure bytes of one row, through C ,, Cj, C, encoding bytes formed by the generator, and through 5 D, encoded bytes, we have a sequence of the following codes. Pure outlets: US NR, NR.j
Coding
bytes:, C4CyCgC ... Coded bytes: US NR, NRjD, D2D,. ... dj if d; belongs
columns O or 1, d. 0 s. if dj- belongs to columns 2-7. Thus, for a reduced series starting with ... IF, 45, Cl and continuing 20, 20, 20, 9B, 4F, 57, 45, SG, 54, 48, 45, 52, 20, the corresponding coded row - ... IF, 45, SG, VZ, B6, VA, 9B, 52, 45, 52, DC, DF, 4F, 58, 4A, B5.
FIG. 2 shows the variation of various signals in the device.
FIG. 2 denotes pure signals (US, NR, and NR2) and the actual data d ,, d, ..., FIG. 2S represents the addition of the register read signal obtained from output 19 of block 18; FIG. 2 & - coding sequence C, C, C, ..., FIG. 2d is the reset pulse to zero received from block 18; FIG. 2 - start points I, - 1, FIG. 2- addition of the write signal to the registers by triggering the bits; FIG. 2calls the clock pulses from the output 17 of the generator 16. At the same time (from the output 19 of the block 18, the registers are read, from the output 20 - reset to O, from the output 21 - the command to write, which occurs by connecting the outputs 19-21 to the inputs of the corresponding registers.
45
ABOUT
ABOUT
oh oh oh oh oh 1 1 1 1 1 1 1 1
about about 1
one
eleven
about about 1 1 about about about 1
Bytes
 CD 1100 1101 16 0001 0110
 58 0101 1000
 91 1001 0001
DO 1101 0000
one
about about 1
about 1 1
about 1 about about 1
about 1 1 about
about
about
one
one
about
about
one
1o
about
one
one
about
about
one
one
one
about o 1 1 1
about 1 about 1 1 about about 1 1 about
about 1
about 1
about 1
about 1 about 1 about 1
about 1
about 1
one
about 1
about about 1
about 1 about 1 about 1 1
about 1 about
table 2
RI
SI
Ti


1101 0110
1000 0001 0000 T
11001 25 00010 2
01011 11 10010 18 11010 26
tfs hfft HRz
.
di dg dj rf (rLJ-LJL-TL

权利要求:
Claims (1)
[1]
A Coding or Decoding Byte Generator, comprising three pseudo-random sequence generators whose inputs are inputs of a coding or decoding byte generator, the output of the first pseudo-random sequence generator is connected to the first input of the first AND element, the output of the second pseudo-random sequence generator, to the second input of the first AND element and the first input the second element And, and the output of the third generator of the pseudo-random sequence to the second input of the second element And, distinguishing the fact that, in order to improve performance by reducing the duration of the formation and increase the length of the byte sequence, an OR element is introduced into it, the first and second inputs of which are connected to the outputs of the first and second AND elements, and the adder modulo 2, the inputs of which are connected to the corresponding outputs of the OR element, and the first pseudo-random sequence generator consists of six EXCLUSIVE OR elements, seven registers and an adder modulo 31, while the first inputs of the first, second, t of the fourth, fifth and fifth elements EXCLUSIVE OR are respectively the first, second, third, fourth and fifth inputs of the generator of coding or decoding bytes, the output of the i-ro element EXCLUSIVE OR (where i = 1, ..., 5) is connected to the i-th the input of the first register, the i-th output of which is connected to the i-th input of the second register and the first group of inputs of the adder modulo 31, the i-th output of the second register is connected to the .. i-th input of the third register and the first group of inputs of the sixth of the element EXCLUSIVE OR, the i-th output of the third register is connected to the i-th input of the fifth register, the i-th output of which is connected to the (i - 1) -th input of the second group of inputs of the adder modulo 31, the i-th output of which is connected to the i-th input of the fifth register, the i-th output of the fifth register is connected to i- the sixth register input and the second group of inputs of the sixth element EXCLUSIVE OR, the output of which is the output of the first pseudo-random sequence generator, the i-th output of the sixth register is connected to the i-th input of the seventh register, the i-th output of which is connected to the second i-ro input EXCLUSIVE OR element, second pseudo-random generator th sequence consists of seven elements XOR, seven. registers and the adder modulo 127, while the first inputs of the first, second, third, fourth, fifth, sixth and seventh elements EXCLUSIVE OR are respectively the sixth, seventh, eighth, first, second, third and fourth inputs of the generator of encoding or decoding bytes the j-ro output of the EXCLUSIVE OR element (where j = 1, 7) is connected to the jth input of the first register, the jth output of which is connected to the j'th input of the second register and the first group of adder inputs modulo 127, j- the second output of the second register is connected to the (j - 1) -th input of the second group the adder inputs modulo 127, the jth output of which is connected to the jth input of the third register, the jth output of which is connected to the jth input of the fourth register and is the output of the second pseudo-random sequence generator, the jth output of the fourth register is connected to j the fifth input of the fifth register, the jth output of which is connected to the jth input of the sixth register, the jth output of the sixth register is connected to the jth input of the seventh register, the jth output of which is connected to the second input of the jth element EXCLUSIVE OR , 1207407 thium pseudo-random generator sequentially This consists of six EXCLUSIVE OR elements, - five registers and an adder modulo 31, while the first inputs of the first, second, third, fourth and fifth elements of EXCLUSIVE OR are the fourth, fifth, sixth, seventh and eighth inputs of the generator of encoding and decoding bytes, respectively , the output of the Kth element EXCLUSIVE OR (where K = 1 ..... 5) is connected to the K-input of the first register, the K-th output of which is connected to the K-th input of the second register and the first group of inputs of the adder modulo 31 , The K-th output of the second register is connected to the K-m input t of the third register and the first group of inputs of the sixth element EXCLUSIVE OR, the Kth output of the third register is connected to the Kth input of the second group of inputs of the adder modulo 31, the Kth output of which is connected to the Kth input of the fourth register, Kth the output of which is connected to the Kth input of the fifth register and the second group of inputs of the sixth element EXCLUSIVE OR, the output of which is the output of the third generator of the pseudo-random sequence, and the Kth output of the fifth register is connected to. the second input of the K-th element is EXCLUSIVE OR.

类似技术:

---

公开号 | 公开日 | 专利标题

---

US5396239A|1995-03-07|Data and forward error control coding techniques for digital signals

---

US4506372A|1985-03-19|Method and apparatus for recognizing in a receiver the start of a telegram signal consisting of a bit impulse sequence

---

US3369229A|1968-02-13|Multilevel pulse transmission system

---

AU669746B2|1996-06-20|Method and device for detection and correction of errors in ATM cell headers

---

JPH0296982A|1990-04-09|M scramble circuit

---

US4829300A|1989-05-09|Signal generation

---

CA1236218A|1988-05-03|Method and apparatus for digital huffman decoding

---

SU1207407A3|1986-01-23|Coding or decoding byte generator

---

EP0414368B1|1998-03-04|Apparatus for data and forward error correction coding for low DC-offset andshort run length

---

EP0240146B1|1992-08-05|Method and apparatus for the channelized serial transmission of redundantly encoded binary data

---

RU2022332C1|1994-10-30|Orthogonal digital signal generator

---

SU1711342A1|1992-02-07|Frame synchronization method and system thereof

---

SU1164789A1|1985-06-30|Redundant storage

---

SU1510014A1|1989-09-23|Device for correcting errors in memory blocks with serial access

---

SU1327173A1|1987-07-30|Apparatus for magnetic record of information

---

JPH05300486A|1993-11-12|Variable length encoding and decoding circuit

---

SU922877A1|1982-04-23|Self-checking storage device

---

SU951738A2|1982-08-15|Cycle synchronization device

---

SU1081637A1|1984-03-23|Information input device

---

SU1061288A2|1983-12-15|Device for receiving multiposition composite signals

---

SU896614A1|1982-01-07|Decoder

---

SU843273A1|1981-06-30|Cyclic synchronization device

---

SU1453416A1|1989-01-23|Device for converting codes from language to language

---

SU734687A1|1980-05-15|Microprogramme control device

---

SU1525922A1|1989-11-30|Device for remote monitoring of intermediate stations of communication system

同族专利:

---

公开号 | 公开日

---

ES8400215A1|1983-10-16|

---

US4543559A|1985-09-24|

---

CA1209704A|1986-08-12|

---

JPS58175052A|1983-10-14|

---

DE3363306D1|1986-06-12|

---

FR2519828B2|1986-01-31|

---

BR8300090A|1983-09-20|

---

EP0083998A1|1983-07-20|

---

FR2519828A2|1983-07-18|

---

EP0083998B1|1986-05-07|

---

ES518860A0|1983-10-16|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

---

LU58605A1|1969-05-08|1969-08-22|

---

DE2634353C2|1976-07-30|1978-08-31|Siemens Ag, 1000 Berlin Und 8000 Muenchen|Message transmission system for pulse code modulation with scrambler on the sending side and synchronized descrambler on the receiving side|

---

US4160120A|1977-11-17|1979-07-03|Burroughs Corporation|Link encryption device|

---

FR2448824B1|1979-02-06|1983-09-02|Telediffusion Fse|

---

EP0028272A1|1979-11-03|1981-05-13|PATELHOLD Patentverwertungs- & Elektro-Holding AG|Method and device for the transmission of enciphered information|GB2185664B|1986-01-17|1989-10-25|Philips Electronic Associated|Teletext transmission systems|

---

FR2619976A1|1987-09-01|1989-03-03|Mouly Michel|Very long pseudo-random character sequence generator|

---

FR2671647B1|1991-01-16|1994-08-19|France Etat|

---

US5535367A|1991-03-04|1996-07-09|Motorola, Inc.|Demultiplexing initialization data to be transferred to memory through a plurality of registers with error detection data|

---

DE19921852A1|1999-05-11|2000-11-16|Bosch Gmbh Robert|Pseudo random number generator|

---

US6763363B1|1999-12-02|2004-07-13|Honeywell International Inc.|Computer efficient linear feedback shift register|

---

NL2000187C1|2006-01-17|2007-07-18|Cornelis Hendricus Liet|Device for processing material, such as a biomass or feed for cattle.|

法律状态:

优先权:

---

申请号 | 申请日 | 专利标题

---

FR8200288A|FR2519828B2|1982-01-11|1982-01-11|VIDEOTEX SYSTEM PROVIDED WITH INFORMATION ACCESS CONTROL MEANS|

---