• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The device DPN CONTROL SYNCHRONES, containing a group of registers, the information inputs of each of which are connected to the information outputs of the previous one, the information inputs of the first register, the groups are information inputs of the device, and the information you; each registrar of the group is connected to the output of the corresponding clock signal generator, the inputs of the clock signal generator are connected to the generator outputs inhrosignalov, characterized in that in order to control the Enhance reliability, it introduced a shift pulse generator. a comparator and a display unit, the output and the first input of the comparator are connected respectively to the input and the first output of the shift pulse generator, the second output of which is connected to the second input of the check bit of the first group register, the output of the check bit of each register group is connected to the second input of the control bit Yes, the next register, and the test bit output of the last group register is connected to the second input of the comparator, the output group of which is connected to the group of inputs of the display unit, the outputs the control bits of the group registers are connected to the group of compass outputs of the orator.
    公开号:SU1109073A3
    申请号:SU762404801
    申请日:1976-09-29
    公开日:1984-08-15
    发明作者:Эрланд Персон Йенс；Геста Роос Стуре
    申请人:Телефонактиеболагет Л.М.Эрикссон (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to a device for controlling clock signals in a digital information system, having one or several registers through which the clock signals successively advance information.
    A device for testing connections in digital information switches is known. The test is performed immediately after switching on and contains parcel 10 of the Special Combination or any combination of data with irregular parity through the switch. At the appropriate output of the switch, it is checked whether the test combination is received by 15 NACs or a combination with a broken parity. Failure to test connections usually means that the circuit is not properly installed through
    switch C13.20
    The closest to this technical solution is a device for controlling a clock signal generator, containing one stable state circuitry associated with each-25-d buffer output of the sing signal on each printed circuit board in a digital system. Moreover, each of the clock signal generators, feeding the register on the board through the buffer circuit, also feeds a circuit with one stable state. A circuit with one steady state works in such a way that if it does not receive sync signals for a specific period of time, then it will overturn into its steady state and fail to work with a label (pointer) of non-operability. These tags can then be viewed in the usual way using a local process. Consequently, a quick indication of the type of failure and its location is carried out. This system performs very well a quick diagnosis of clock faults and reveals a specific fault location. The device contains a pulse distributor that uses valves AND multivibrators for each syncro, “signal” to control faults 23.
    However, these known devices have a number of drawbacks.
    The failure to test the connections of 55. can be caused by a variety of types of faults, including a clock generator fault. It is difficult to establish the type of fault and its location.
    It may take a long time until a malfunction is detected, since the frequency of repeating a connection check depends on the amount of information passing. Obviously, this test can be performed at a frequency that does not depend on the amount of information being passed, but this can cause processor overload. ;
    A disadvantage of the known devices is the low reliability of the control.
    The purpose of the invention is to increase the reliability of the control.
    The goal is achieved by the fact that a known device for controlling clock signals containing a group of registers, the information inputs of each of which are connected to the information outputs of the previous one, the information inputs of the first register of the group are the information inputs of the device, and the information outputs of the last register of the group are outputs of the device, the first the input of the check bit of each register of the group is connected to the output of the corresponding clock generator, the inputs of the synchronizer drivers These signals are connected to the clock generator outputs, a shift pulse generator, a comparator and a display unit are entered, the output and the first input of the comparator are connected respectively to the input and the first output of the shift pulse generator, the second output of which is connected to the second input of the control, bit of the first register group, output the test bit of each register of the group is connected to the second input of the check bit of the next register, and the output of the check bit of the last register of the group is connected to the second input Odara comparator group of outputs which is connected to. the group of inputs of the display unit, the outputs of the control bits of the registers of the group are connected to the group of inputs of the comparator,
    In this Invention, a sync check bit is advanced through control bits, each of which is associated with a register, and all together form a control chain controlled by control sync signals, so the absence of one or
    several synchronization signals prevent the synchronization check bit from progressing to the end of the check chain, and after passing the check bit of synchronization through the check chain, it is checked whether the check bit has passed through this check chain or not.
    The drawing shows a block diagram of a device for controlling clock signals implemented on a printed circuit board.
    Printed circuit board 1 contains a group of registers 2 through which data passing along the input lines advances to the incoming lines, in each register 2 for each synchronization input 3-6 a separate clock signal is provided. Each sync signal is applied to a corresponding register 2 through an individual sync driver 7. In addition, the device contains a shift pulse generator 8, an output 9, a control output 10, a comparator 11, a control output 12, a check bit 13 of a register 2, a clock generator 14, an indication unit 15, a check bits output 16, 17 and 18 .
    In most cases, the registers from which re-synchronized registers 2 are executed do not provide for the exact number of bits that it is desirable to synchronize, and therefore spare bits exist in the re-synchronized registers. Although necessary. to take into account that spare bits may not always be available and in some cases for implementing the invention it may be necessary to design redundant registers 2 to provide additional bits. It is also possible to implement the invention using a trigger executed independently of the register and controlled controlled
    sequence of sync signals.
    I.
    In the present invention, the main injection of the shift pulse generator 8 on the board 1, which supplies the timing check bit to the output 9. The shift pulse generator 8 is controlled by a control signal from output 10 from a local processor including a comparator 11, which (comparator 11) has a second the output connected to the input of the display unit 15. The synchronization control signal from output 9 can be connected to all registers 2, as shown in the diagram, and can appear at the output of board 12. Each register 2 contains a bit 13, which It consists of one of the bits of the register, to one of the inputs of which a control signal is applied. When receiving a signal from the clock signal generator 14 connected to the register, the control bit is set and the control signal is sent to the next register. This process is continuously carried out throughout the whole group of registers.
    The work is as follows.
    The local processor controls the generator of the shift pulses 8 so as to set its output to the state 11 if there is no fault
    clock generator 14, this bit will pass through the board 1 and all the other boards. Local processor
    allocates sufficient time to complete the control
    synchronization bit through the boards, then analyzes this bit at the output of the last sync stage of the last board by comparing at the comparator 11 the received
    the control bit and the control bit sent from the generator 8 shift pulses. If the bit is a logical 1, then for a local processor this means
    that all clock phases were present. Then, the local processor sets the output of the shift pulse generator to the state O and checks / correct passage of the zero
    through all the boards. This process is continuously repeated. .If the control. the synchronization bit did not go through the circuits, then the local processor can check the state of the bit on
    output of each board, for example, by means of the connected display unit 15, thereby allowing the fault to be localized on a specific board. It is considered sufficient to establish the location of the irregular states. This device allows you to locate a particular clock phase on a $ 1 specific board. It should be noted that the normal flow of information passing through the registers is controlled in the usual way, for example; using parity, regardless of the described method of controlling synchronization signals. The main advantage of the invention in comparison with the well-known one is that it provides reliable control of synchronizing pulses and does not require as many additional logic circuits as necessary to implement known solutions to this problem. (
    权利要求:
    Claims (1)
    [1]
    DEVICE FOR CONTROL OF SYNCHRONOUS SIGNALS, containing a group of registers, the information inputs of each of which are connected to the information outputs of the previous one, the information inputs of the first register of the group are the information inputs of the device, and the information outputs of the last register of the group are the outputs of the device, the first input of the control bit of each register of the group is connected with the output of the corresponding clock driver, the inputs of the clock drivers are connected to the outputs of the clock generator catch, characterized in that, in order to increase reliability of control, it administered shift pulse generator. a comparator and an indication unit, wherein the output and the first input of the comparator are connected respectively to the input and the first output of the shear pulse generator, the second output of which is connected to the second input of the control discharge of the first register of the group, the output of the control discharge of each register g of the group is connected to the second input of the control the discharge of the next register, and the output of the control discharge of the last register of the group is connected to the second input of the comparator, the group of outputs of which is connected to the group of inputs of the display unit, the outputs of the control The bits of the group registers are connected to the group of inputs of the comparator.
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    同族专利:
    公开号 | 公开日
    BR7606344A|1977-05-31|
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    FI64474C|1983-11-10|
    NL187136C|1991-06-03|
    NL187136B|1991-01-02|
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    NL7610427A|1977-03-31|
    DK153605B|1988-08-01|
    ES451922A1|1977-09-01|
    JPS5243335A|1977-04-05|
    YU232476A|1983-04-27|
    EG13396A|1981-03-31|
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    CS251055B2|1987-06-11|
    DE2641700A1|1977-04-07|
    DE2641700C2|1987-10-29|
    HU174136B|1979-11-28|
    IT1072928B|1985-04-13|
    MY8100229A|1981-12-31|
    DK153605C|1988-12-19|
    DK436276A|1977-03-30|
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    CA1074020A|1980-03-18|
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    FR2326080A1|1977-04-22|
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    AR212340A1|1978-06-30|
    CH607460A5|1978-12-29|
    YU37408B|1984-08-31|
    GB1527167A|1978-10-04|
    FI762704A|1977-03-30|
    FR2326080B1|1982-12-03|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    SE197047C1|
    US3056108A|1959-06-30|1962-09-25|Internat Bushiness Machines Co|Error check circuit|
    US3176269A|1962-05-28|1965-03-30|Ibm|Ring counter checking circuit|
    DE1537379C3|1967-09-22|1980-07-03|Siemens Ag, 1000 Berlin Und 8000 Muenchen|Safety circuit for performing logical links for binary switching variables and their complementary switching variables|
    US3659088A|1970-08-06|1972-04-25|Cogar Corp|Method for indicating memory chip failure modes|
    US3805152A|1971-08-04|1974-04-16|Ibm|Recirculating testing methods and apparatus|
    US3815025A|1971-10-18|1974-06-04|Ibm|Large-scale integrated circuit testing structure|
    US3789205A|1972-09-28|1974-01-29|Ibm|Method of testing mosfet planar boards|
    US3761695A|1972-10-16|1973-09-25|Ibm|Method of level sensitive testing a functional logic system|
    US3961252A|1974-12-20|1976-06-01|International Business Machines Corporation|Testing embedded arrays|US4095045A|1977-01-19|1978-06-13|General Datacomm Industries, Inc.|Method and apparatus for signaling in a communication system|
    DE3317642C2|1982-05-21|1991-06-27|International Computers Ltd., London, Gb|
    FR2553559B1|1983-10-14|1988-10-14|Citroen Sa|CONTROLLING THE LOADING OF INTEGRATED CIRCUITS OF THE PARALLEL REGISTER TYPE HAVING A DISTINCT LOADING REGISTER OF THE OUTPUT STAGES|
    US4542509A|1983-10-31|1985-09-17|International Business Machines Corporation|Fault testing a clock distribution network|
    US4653054A|1985-04-12|1987-03-24|Itt Corporation|Redundant clock combiner|
    US4800564A|1986-09-29|1989-01-24|International Business Machines Corporation|High performance clock system error detection and fault isolation|
    EP0294505B1|1987-06-11|1993-03-03|International Business Machines Corporation|Clock generator system|
    DE3804969C1|1988-02-18|1989-09-14|Dr. Johannes Heidenhain Gmbh, 8225 Traunreut, De|
    US5077739A|1989-05-17|1991-12-31|Unisys Corporation|Method for isolating failures of clear signals in instruction processors|
    DE19923231C1|1999-05-20|2001-01-11|Beta Res Gmbh|Digital analysis of frequencies in smart cards|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    AUPC336475|1975-09-29|
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