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    • 专利摘要:
    18 ABSTRACT: The present invention relates to the technical field of solar cell manufacturing, and provides a surface/interface passivation layer for a crystalline silicon solar cell and a passivation method. In the invention, a front surface of a n+-type doped layer and a back surface of a p-type silicon substrate are passivated. A passivation film having a four-layer 5 laminated structure is prepared on the front surface of a n+ layer of a p-type silicon substrate by PECVD; and a passivation film having a four-layer laminated structure is prepared on the back surface of the p-type silicon substrate by PECVD and ALD. The structure sequence of the laminated passivation layer of the invention is crucial to the passivation effect, and there is a synergism between the laminates. An excellent anti- lO reflection effect is achieved after passivation, and the passivation effect is good. Thus the passivation method and passivation layer of the present invention has excellent application prospect in p-type PERC cells. 15 (Fig. l)
    公开号:NL2022817A
    申请号:NL2022817
    申请日:2019-03-27
    公开日:2019-05-01
    发明作者:Ding Jianning；Yuan Ningyi；Ye Feng
    申请人:Univ Jiangsu；Univ Changzhou；
    IPC主号:
    专利说明:

    FIELD
    The present invention relates to the technical field of solar cell manufacturing, particularly to a surface/interface passivation layer for a high-efficiency crystalline silicon solar cell and a passivation method, and more specifically to a surface/interface passivation method for a front surface and a back surface of a P-type crystalline silicon cell having a n+/p structure formed by front-side phosphorus diffusion.
    BACKGROUND
    Due to the surface/interface defects and surface dangling bonds, crystalline silicon solar cells suffer from serious recombination of photo-generated carriers at the surface/interface, resulting in a decrease in the solar cell efficiency. The effective minority carrier lifetime Tefr of a solar cell depends on the bulk lifetime rbuik, effective top surface lifetime TtSurface, and effective bottom surface lifetime rbsurface of the silicon chip and satisfies the relation formula: 1/Teff= l/rbuik+ l/rtsurface+ l/ibsurface. With the requirement of low cost, the solar cell chip is getting thinner and thinner. The thickness of the silicon chip is 160180 microns, and the effective surface lifetime of the silicon chip is much smaller than the bulk lifetime. Therefore, the influence of surface recombination on the effective minority carrier lifetime is very obvious. The higher the surface state density is, the greater the surface recombination rate will be. To increase the collection rate of photogenerated carriers, it is necessary to reduce the surface/interface state density, thereby reducing the surface/interface recombination.
    To improve the efficiency of the crystalline silicon cell, a good surface/interface passivation technique needs to be developed to reduce the rate of surface/interface recombination. There are many methods for surface passivation of crystalline silicon solar cells. For example, International Patent Application WO 2006/110048 (US20090056800A1) discloses a multilayer passivation film structure, obtained by, for example, depositing a hydrogenated amorphous silicon (a-Si:H) or hydrogenated silicon carbide (SiC:H) film on the surface of a silicon chip, and then depositing a silicon nitride (SiNx) film by PECVD. International Patent Applications WO
    2007/055484 discloses a laminated passivation film structure, including a layer of SiOxNy (10-50 nm thick) for passivation and a layer of SiNx (50-100 nm thick) for reducing the reflection. The Chinese Invention Patent Method of Passivating Crystalline Silicon Cell (201710304646.2) discloses that a silicon chip doped by diffusion is first thermally oxidized to form a S1O2 passivation layer; then a first SiNx passivation film is deposited, and sintered at a low temperature, to release the hydrogen in the passivation film; and a second SiNx passivation film is then deposited. The Chinese Invention Patent Laminated Composite Passivation Film for Front Surface of Monocrystalline Silicon Solar Cell (201110027415.4) discloses a laminated passivation film structure, obtained by sequentially growing a silicon oxide (SiO2) film, a hydrogenated amorphous silicon (aSi:H) film, and a silicon nitride (SiNx) film on a front surface of a monocrystalline silicon substrate of a solar cell. EP Patent Application Passivation layer structure of solar cell and fabricating method thereof (EP 2 077 584 A2) discloses a laminated passivation film structure on a surface of crystalline silicon, comprising a thermally oxidized SiCh/oxide layer (ZnO or AI2O3). EP Patent Application PASSIVATION FILM, COATING MATERIAL, SOLAR-CELL ELEMENT, AND SILICON SUBSTRATE WITH PASSIVATION FILM ATTACHED THERETO (EP 2 876 690 Al) discloses a laminated passivation film structure on a surface of crystalline silicon, comprising AI2O3 and niobium oxide. US Patent Application Passivation process for solar cell fabrication (US 8 168 462 B2) discloses that S1O2 is formed by plasma oxidation of a crystalline silicon substrate on the back surface of a silicon chip, and then a SiNx film is deposited. US Patent Method for blister-free passivation of a silicon surface (US 8 557 718 B2) discloses a laminated passivation film structure of AhCh/SiNx or SiOx. US Patent Method of manufacturing crystalline silicon solar cells (US 8 709 853 B2) discloses that a S1O2 layer is formed by thermal oxidation on a front and back surface of a silicon chip, and then a SiNx film is deposited by PECVD. US Patent Optical passivation film, method for manufacturing the same, and solar cell (US 20130125961 Al)) discloses that an optical passivation film Tij. xAlxOy is prepared by spraying. International Patent Application Passivation film stack for silicon-based solar cells (WO2013123225 Al) discloses a laminated passivation film structure of AI2O3/S1NX, wherein hydrogen content is reduced to avoid the occurrence of bubbles in the film. Chinese Invention Patent Surface treatment method for silicon chip in passivation process of crystalline silicon solar cell (201410611092.7) discloses that hydrofluoric acid/sulfuric acid/nitric acid mixed at a certain ratio is used as a primary and secondary treating fluid for the diffusion and passivation process during the battery production, and the passivation process is performed by using a AI2O3 single layer or a AhCh/SiNx double layer passivation film. International Patent Application Method, apparatus, and systems for passivation of solar cells and other semiconductor devices (WO 2015/039128 A2) discloses that SiOx/SiNx is deposited on a front surface of a crystalline silicon cell for passivation and reducing the reflection, and SiOx is deposited on a back surface for passivation. Chinese Invention Patent Manufacturing process of crystalline silicon solar cell (201610174023.3) discloses that a crystalline silicon cell is passivated by forming a laminated film of S1O2, AI2O3, and SiNx etc by atomic layer deposition and plasma atomic layer deposition on both the front and back surfaces. A SiCh/AhCh/SiNx laminated film is formed on both surfaces of the cell chip.
    Although some passivation techniques have been developed, various passivation films have certain limitations. For example, forming a dense silicon oxide film on the silicon surface by a high-temperature thermal oxidation process, the thermal oxidation passivation can not only passivate the substrate of the P-type crystalline silicon cell, but also the emitter of the P-type crystalline silicon cell. However, the hightemperature thermal oxidation process will affect the formed diffusion junction on one hand, which increases the difficulty in design of battery structure design. On the other hand, the high-temperature oxidation process also tends to cause lattice dislocation in the substrate, affecting the bulk minority carrier lifetime of the crystalline silicon substrate. The surface passivation of a crystalline silicon cell by a-SiNx:H prepared by low temperature plasma enhanced chemical vapor deposition (PECVD) is a commonly used passivation method in the industry. Since a-SiNx:H prepared by PECVD contains H atoms, and a-SiNx:H contains a certain amount of positive charges which can produce a field passivation effect, a-SiNx:H can make the surface of crystalline silicon cell passivated. However, the positive charge enriched in the a-SiNx:H dielectric layer causes parasitic shunting on the back surface when the p-type silicon substrate is passivated, affecting the cell efficiency. Another alternative material is intrinsic hydrogenated amorphous silicon (a-Si:H) prepared by low-temperature PECVD, but the amorphous silicon has the disadvantage that the subsequent heat treatment process has a significant influence on the passivation of amorphous silicon. The surface passivation of a crystalline silicon cell by AI2O3 prepared by atomic layer deposition (ALD) and PECVD is a new type passivation technique proposed in recent years. The AI2O3/S1 contact surface has a high fixed negative charge density (about 10i2-1013 cm'2), and exhibits significant field effect passivation characteristics by shielding the minority carriers (electrons) on the surface of p-type silicon. The disadvantage of ALD is that the growth rate is extremely low. Considering the cost, the ALD technology is suitable for the deposition of ultra-thin AI2O3.
    GENERAL STATEMENTS
    In order to make full use of the advantages of various passivation films and overcome their respective shortcomings, the low-cost manufacturing of high-efficiency crystalline silicon cells is realized by taking the asymmetric upper and lower structures of crystalline silicon cells (pn junction) into consideration, and a passivation technology comprising a buffer layer laminated on a host dielectric layer is provided in the invention. Taking a p-type crystalline silicon cell as an example, phosphorus diffusion is performed on a p-type substrate to form an n+/p junction. The incident sunlight is input into the p-type crystalline silicon cell through the n+ layer. For this reason, the surface of the n+ layer is referred to as the front surface, and the surface of the p-type layer under the p-type substrate is referred to as the back surface. A design and preparation method of laminated passivation film on the surface of the n+ layer and the back surface of the p-type layer of the crystalline silicon cell is provided in the invention. The surface of the n+ layer and the p-type layer is passivated by chemical passivation and field passivation, and good bulk passivation of crystalline silicon is achieved at the same time. Adjusting the thickness of the passivation film on the surface of the n+ layer can achieve reduced reflection of the incident light.
    For the above purpose, the invention provides the following technical solutions.
    In one aspect, the invention provides a surface/interface passivation layer for a high-efficiency crystalline silicon cell, the surface/interface passivation layer comprises a passivation layer provided on a front surface of a n+-type doped layer of a p-type crystalline silicon cell, and a passivation layer provided on a back surface of a p-type silicon substrate of the p-type crystalline silicon cell. The passivation layer on the front surface of the n+type doped layer has a four-layer laminated structure of a-SiOx:H (2 nm)/a-SiNx:H (2.18, nm)/a-SiNx:H (2.08, 30 nm)/a-SiOx:H (110 nm) in sequence, wherein the a-SiOx:H (2 nm) is attached to the n+-type doped layer. The passivation layer on the back surface of the p-type silicon substrate has a four-layer laminated structure of a-SiOx:H (2 nmyAhO , (15 nm)/a-SiOx:H (220 nm)/a-SiNx:H (2.08, 80 nm) in sequence, wherein the a-SiOx:H (2 nm) is attached to the back surface of the p-type silicon substrate.
    Preferably, the p-type crystalline silicon cell is a p-type PERC cell.
    In another aspect, the invention provides a passivation method for a highefficiency crystalline silicon cell, which comprises specifically the following passivation steps:
    (1) Passivation of a front surface of a n+-type doped layer, comprising:
    preparing hydrogenated amorphous silicon oxide (a-SiOx:H) by plasma enhanced chemical vapor deposition (PECVD), preparing two layers of hydrogenated amorphous silicon nitride (a-SiNx:H) with different refractive indices on a-SiOx:H by PECVD, and depositing a-SiOx:H by PECVD, to finally form a passivation film having a four-layer laminated structure of a-SiOx:H(2 nm)/a-SiNx:H(2.18,10 nm)/a-SiNx:H (2.08, 30 nm)/aSiOx: H (110 nm).
    The process conditions for preparing a-SiNx:H of high refractive index are more favorable for hydrogen passivation, however, the light absorption coefficient is high. In order to reduce the absorption, only 10-nm thickness of a-SiNx:H is deposited; then 30nm thickness of a-SiNx:H having a refractive index of 2.08 is deposited by PECVD, to further achieve the bulk passivation of crystalline silicon; and then 110-nm thickness of aSiOx:H is deposited by PECVD, to further exert a good light-limiting effect. Therefore, the a-SiOx:H7a-SiNx:H/a-SiOx:H structure has a good passivation and reflection reducing effect on the n+ layer of the crystalline silicon cell.
    (2) Passivation of a back surface of p-type silicon substrate, comprising preparing hydrogenated amorphous silicon oxide (a-SiOx:H) by plasma enhanced chemical vapor deposition (PECVD), preparing ultrathin AI2O3 on the a-SiOx:H by atomic layer deposition (ALD), preparing a-SiOx:H on the ultrathin AI2O3 by PECVD, and preparing a-SiNx:H by PECVD, to finally form a passivation film having a four-layer laminated structure of a-SiOx:H (2 nm) /AI2O3 (15 nm)/a-SiOx:H (220 nm)/a-SiNx:H (2.08, 80 nm).
    Preferably, the step of preparing a-SiOx:H by PECVD specifically includes: a silicon chip is cleaned and inserted into a graphite boat; an a-SiOx:H layer is deposited in a PECVD tube by introducing silane at a flow rate of 90 seem and nitrous oxide at a flow rate of 3.7-4.05 slm, wherein the deposition temperature is controlled to 450°C, the pressure is 700-1500 mTor, the power is 1700-2100 watts, and the deposition time is 151200 s; finally the silicon chip is removed from the boat after deposition.
    Preferably, the step of preparing ultrathin AI2O3 by ALD includes specifically: the silicon chip is cleaned and automatically transferred from a chip box to an ALD cavity; a Al Ox film is deposited by introducing TMA and H2O at a flow rate of 10 slm and 15 slm respectively, wherein the deposition temperature is controlled to 200°C, the deposition time is about 15 s; and the silicon chip is automatically transferred out of the cavity and into the chip box after deposition.
    Preferably, the step of preparing a-SiNx:H by PECVD includes specifically: a silicon chip is cleaned and inserted into a graphite boat; an a-SiNx:H layer is deposited in the PECVD tube by introducing silane at a flow rate of 500-650 seem and ammonia at a flow rate of 3.75-4.05 slm, wherein the deposition temperature is controlled to 450°C, the pressure is 1500-1600 mTor, the power is 1700 watts, and the deposition time is 350-1100 s; finally the silicon chip is removed from the boat after deposition.
    As can be seen from the above technical solutions, in the present application, the order of passivation and lamination is not disclosed in the prior art. Moreover, the structure sequence of the laminated passivation layer prepared by the present application is crucial to the passivation effect, and there is a synergism effect between the laminates. The specific effects are as follows:
    First, for the passivation of the n+ layer, the first layer of a-SiOx:H with a thickness of 2 nm is prepared by PECVD. During the preparation process, with the hydrogen plasma, secondary cleaning on the surface of the silicon chip is performed and weak Si-Si bonds are etched. The deposited hydrogenated silicon oxide saturates the dangling bonds on the surface of the silicon, thereby reducing the interface state density and providing excellent interface chemical-passivation effect. At the same time, in the process of depositing the film, the hydrogen atoms diffuse into the crystalline silicon, and passivate the defects in the crystalline silicon, thereby reducing the defects in the crystalline silicon. 10 nm-thick a-SiNx:H having a refractive index of 2.18 is then prepared by PECVD, which mainly serves for bulk passivation of crystalline silicon. However, the a-SiNx:H of high refractive index has a high light absorption coefficient, thus, in order to reduce the absorption, the thickness of «-SiNx:H is limited and thus only 10-nm thickness of a-SiNx:H is deposited; then 30 nm-thick a-SiOx:H having a refractive index of 2.08 is deposited by PECVD, to further achieve the bulk passivation of crystalline silicon. The two layers of silicon nitride are sandwiched between the two layers of silicon oxide. There is a certain amount of positive charges at the interface between silicon nitride and silicon oxide, which can provide field passivation for the surface of the n+ layer. Such a structure can better fix the positive charge contained in a-SiNx:H. Thus, the effect of the positive charges fixed at the interface on the field passivation of the n+ layer can be fully exerted. Therefore, the otSiOx:H/a-SiNx:H/a-SiOx:H structure can well passivate the n+ layer of the crystalline silicon cell. The thickness of silicon nitride and silicon oxide is chosen such that a good effect is provided in reducing the reflection of incident light.
    The four-layer lamination order of a-SiOx:H/A12O3/a-SiOx:H /a-SiNx:H on the surface of the p-layer has also an important impact on the passivation effect. For example, in Chinese Patent Application CN201220238684.5, the claims claim a crystalline silicon solar cell comprising a silicon chip (1), wherein an emitter on a light facing surface of the silicon chip (1) is provided with a silicon dioxide layer (2), an aluminum oxide passivation layer (3), and a α-SiN X:H anti-refl ection film (4) sequentially, and a silicon dioxide layer (5) and an aluminum oxide passivation layer (6) are sequentially provided on a back surface of the silicon chip (1). In this application, multiple coatings are applied to the front and back surface of the silicon chip, and the structure formed on the light facing surface is silicon dioxide layer/aluminum oxide passivation layer/α-SiN X:H, the structure and sequence of the laminates are different from that in the present application.
    The four-layer laminated passivation film on the surface of the p-type layer of the crystalline silicon cell in the present invention has a a-SiOx:H/A12O3/a-SiOx:H/aSiNx:H structure. a-SiOx:H is prepared by PECVD. During the preparation process, with the hydrogen plasma, secondary cleaning is performed on the surface of the silicon chip and weak Si-Si bonds are etched. The deposited silicon oxide saturates the dangling bonds on the surface of the silicon, thereby reducing the interface state density and providing excellent interface chemical-passivation effect. Ultrathin AI2O3 (with a thickness of less than 15 nm) is prepared by ALD, and then a-SiOx:H is prepared by PECVD, so that AI2O3 is switched between the two layers of silicon oxide, and a high concentration of fixed negative charges are formed. The negative charges provide field passivation for the surface of the p-type layer. Such a structure sequence can better fix the negative charges and thus have a good field passivation effect on the p layer. Finally, in the preparation of a-SiNx:H by PECVD, since the first three layers of films are thin, the H atom is easily diffused into the network structure of the crystalline silicon to saturate the dangling bonds, thus further achieving the bulk passivation of crystalline silicon. Moreover, the silicon nitride protects the ultra-thin AI2O3 in the subsequent metallization process. The largest difference between the passivation films on the n+ layer and the p-type layer is that the field passivation patterns are different, in which the positive charges acts on the n+ layer, and the negative charges acts on the p-type layer. The charges generated at the interface between silicon nitride and silicon oxide are positive charges, and the charges generated at the interface between aluminum oxide and silicon oxide are negative charges, so silicon nitride and aluminum oxide are respectively used in the passivation films of the n+ layer and the p-type layer.
    BRIEF DESCRIPTION OF THE DRAWINGS
    Features and advantages of some embodiments of the present invention, and the manner in which the same are accomplished, will become more readily apparent upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings, which illustrate preferred and exemplary embodiments and which are not necessarily drawn to scale, wherein:
    Fig. 1 shows a p-type crystalline silicon cell having a n+/P structure, and passivation film structures on a front and back surface thereof; and
    Fig. 2 shows the comparison of the surface reflectivity of Embodiment 1 and Comparative Embodiment 1 (1) after passivation.
    DETAILED DESCRIPTION
    In the following detailed description, numerous non-limiting specific details are given to assist in understanding this disclosure.
    The principles and characteristics of the invention will be described below with reference to accompanying drawings. The examples described here are merely to explain the invention and are not intended to limit a scope of the invention.
    1. Preparation of hydrogenated amorphous silicon oxide film a-SiOx:H by PECVD
    A silicon chip is cleaned and inserted into a graphite boat. An ot-SiOx:H layer is deposited in the PECVD tube by introducing silane at a flow rate of 90 seem and nitrous oxide at a flow rate of 3.7-4.05 slm, wherein the temperature is controlled to 450°C, the pressure is 700-1500 mTor, the power is 1700-2100 watts, and the time is 15-1200 s. The silicon chip is removed from the boat after the process is completed.
    2. Preparation of hydrogenated amorphous silicon nitride film a-SiNx:H by PECVD
    A silicon chip is cleaned and inserted into a graphite boat. An a-SiNx:H layer is deposited in the PECVD tube by introducing silane at a flow rate of 500-650 seem and ammonia at a flow rate of 3.75-4.05 slm, wherein the temperature is controlled to 450°C, the pressure is 1500-1600 mTor, the power is 1700 watts, and the time is 350-1100 s. The silicon chip is removed from the boat after the process is completed.
    3. Preparation of aluminum oxide Al Ox by ALD
    A silicon chip is cleaned and automatically transferred from a chip box to an ALD cavity, and a Al Ox film is deposited, in which the temperature is controlled to 200°C, TMA and H2O are introduced at a flow rate of 10 slm and 15 slm respectively, and the deposition time is about 15-20 s. The silicon chip is automatically transferred out of the cavity and into the chip box after deposition.
    Embodiment 1:
    Four-layer laminated passivation film a-SiOx:H/a-SiNx:H((2.18)/a-SiNx:H(2.08)/aSiOx:H on n+ layer
    A silicon chip was cleaned and inserted into a graphite boat. An a-SiOx:H layer was deposited in the PECVD tube by introducing silane and nitrous oxide, in which the flow rate of silane was 90 seem, the flow rate of nitrous oxide was 3.7 slm, the temperature was controlled to 450°C, the pressure was 700 mTor, the power was 2100 watts, and the time was 15 s. Nitrous oxide was stopped and the RF source was turned off. The temperature was controlled to 450°C, the flow rate of silane was increased to 500 seem, ammonia was introduced at a flow rate of 3.8 slm, the pressure was 1500 mTor, the RF source was turned on, the RF power was set to 1700 W, and the first layer of a-SiNx:H was deposited for 550 s. Then, the second layer of a-SiOx:H was grown in the PECVD tube. Ammonia was introduced at a flow rate of 4.05 slm, the pressure was 1500 mTor, the RF source was turned on, the RF power was set to 1700 W, and a-SiNx:H was deposited for 100s. The flow rate of ammonia was adjusted to 4.0 slm, and the second layer of a-SiNx:H was deposited for 300 s. The RF source was turned off and ammonia was stopped. The flow rate of silane was reduced to 90 seem. Nitrous oxide was introduced at a flow rate of 3.7 slm, and the pressure was 700 mTor. The RF source was turned on, the power was 2100 W, the time was 600 s, and the silicon chip was removed from the boat after the process was completed to form a four-layer laminated passivation film a-SiOx:H (2 nm)/a-SiNx:H (2.18, 10 nm)/aSiNx:H (2.08, 30 nm)/a-SiOx:H (110 nm).
    Comparative Embodiment 1 (1):
    Formation of two-layer laminated film a-SiNx:H/a-SiOx:H on n+ layer
    As compared with Embodiment 1, the same passivation method was used in Comparative Embodiment 1 (1), and A two-layer laminated film a-SiNx:H /a-SiOx:H was formed on the n+ layer.
    Fig. 2 compares the surface reflectivity of Embodiment 1 and Comparative Embodiment 1 (1) after passivation. It can be seen from the figure that laminated film on surface of Embodiment 1 has a good anti-reflection effect.
    Experimental results:
    Table 1. Comparison of the recombination rates of Embodiment 1 and Comparative
    It can be seen from Table 1 that, the recombination of the carriers on the surface in Embodiment 1 is significantly lower than that in the comparative Embodiment, indicating that the surface is well passivated.
    Embodiment 2:
    Four-layer laminated passivation film a-SiOx:H/Al2Oi/SiOx/a-.S7Nx:H on p-type layer
    The silicon chip was cleaned and inserted into a graphite boat. An a-SiOx:H layer was deposited in the PECVD tube by introducing silane and nitrous oxide, in which the flow rate of silane was 90 seem, the flow rate of nitrous oxide was 3.7 slm, the temperature was controlled to 450°C, the pressure was 700 mTor, the power was 2100 watts, and the time was 15 s. The silicon chip was removed from the boat after the process was completed. The silicon chip was automatically transferred from a chip box to an ALD cavity, and a AlOx film was deposited, in which the temperature was controlled to 200°C, TMA and EEO are introduced at a flow rate of 10 slm and 15 slm respectively, and the deposition time was about 15 s. The silicon chip was automatically transferred out of the cavity and into the chip box after deposition. The silicon chip was inserted into a graphite boat, and a second layer of a-SiOx:H was grown in the PECVD tube by introducing silane and nitrous oxide, in which the flow rate of silane was 90 seem, the flow rate of nitrous oxide was 3.7 slm, the temperature was controlled to 450°C, the pressure was 700 mTor, the power was 2100 watts, and the time was 1200 s. A α-5ΪΝχ:Η layer was grown in the PECVD tube by introducing silane and ammonia, in which the flow rate of silane was 650 seem, the flow rate of ammonia was 4.5 slm, the temperature was controlled to 450°C, the pressure was 1600 mTor, the power was 1700 W, and the time was 1100 s. The silicon chip was removed from the boat after the process was completed, to form a four-layer laminated passivation film a-SiOx:H (2 nmyAbOa (15 nm)/a-SiOx:H (220 nm)/a-SiNx:H (2.08,80 nm).
    Experimental results: After passivation with the four-layer laminated film of this embodiment, the recombination rate on the back surface is less than 10 cm/s. The smaller the surface recombination rate is, the better the passivation effect will be.
    Comparative Embodiment 2 (1): Four-layer laminated passivation film a-SiOx:H/a5/Nx:H/a-SiOx:H/A12O3 on a p-type layer
    As compared with Embodiment 2, the same passivation method was used in Comparative Embodiment 2 (1), and a four-layer laminated passivation film a-SiOx:H/«SÏNx:H /a-SiOx:H/AhO3 was formed.
    Experimental results: After passivation with the four-layer laminated film of
    Comparative Embodiment 2 (1), the recombination rate on the back surface is about 100 cm/s.
    Comparative Embodiment 2 (2): Three-layer laminated passivation film AhCh/aSiOx:H/«->S7Nx:H on p-type layer
    As Compared with Embodiment 2, the same passivation method was used in Comparative Embodiment 2 (2), and a three-layer laminated passivation film AhOv'aSiOx:H/(z-,S'zNx:H was formed on the p-type layer.
    Experimental results: After passivation with the three-layer laminated film of
    Comparative Embodiment 2 (2), the recombination rate on the back surface is about 50 cm/s.
    Table 2. Comparison of the recombination rates of Embodiment 2, Comparative Embodiments 2 (1) and 2 (2) after passivation.
    Embodiment 2ComparativeEmbodiment 2(1)| ComparativeEmbodiment 2(2)Recombination rate (cm/s)9.810050
    It can be seen from Table 2 that the recombination of the carriers on the surface in
    Embodiment 2 is significantly lower than that in the comparative Embodiments, indicating that the surface is well passivated.
    Embodiment 3: The passivation film structure for the n+-type layer obtained in Embodiment 1 and the passivation film structure for the p-type layer obtained in Embodiment 2 are used in a p-type PERC cell.
    Table 3: Application effects in p-type PERC cells in Embodiment 3
    HocAcFFEfff Hipp«ΛηρρCellarea(mV)(mA /cm2)(%)(%)(mV)(mA/ cm2)(cm2)Average683.840.4681.1622.45583.5738.45243.36
    Optimum684.440.5481.4922.61587.938.48
    In Comparative Embodiment 3 (1), the passivation film structure for the n+-type layer obtained in Embodiment 1 and the passivation film structure for the p-type layer obtained in Comparative Embodiment 2 (1) are used in a p-type PERC cell.
    In Comparative Embodiment 3 (2), the passivation film structure for the n+-type layer 5 obtained in Embodiment 1 and the passivation film structure for the p-type layer obtained in Comparative Embodiment 2 (2) are used in a p-type PERC cell.
    In Comparative Embodiment 3 (3), the passivation film structure for the n+-type layer obtained in Comparative Embodiment 1 (1) and the passivation film structure for the ptype layer obtained in Embodiment 2 are used in a p-type PERC cell.
    In Comparative Embodiment 3 (4), the passivation film structure for the n+-type layer obtained in comparative Embodiment 1(1) and the passivation film structure for the p-type layer obtained in Comparative Embodiment 2 (1) are used in a p-type PERC cell.
    Table 4. Comparison of the application effects in Embodiment 3 vs Comparative Embodiment 3 (1), Comparative Embodiment 3 (2), Comparative Embodiment 3 (3), and 15 Comparative Embodiment 3 (4)
    Open-circuit voltage foeShort-circuitcurrent Jsc Fill factorFFEfficiencyEff(mV)(mA/cm2)(%)(%)Embodiment 3684.440.5481.4922.61ComparativeEmbodiment 3(1)682.140.2781.1222.28ComparativeEmbodiment 3 (2)682.440.1381.2922.26ComparativeEmbodiment 3 (3)682.140.4281.2122.38ComparativeEmbodiment 3 (4)680.840.1980.9822.15
    Although the present invention has been described in connection with specific exemplary embodiments, it should be understood that various changes, substitutions, and alterations apparent to those skilled in the art can be made to the disclosed embodiments without departing from the spirit and scope of the invention as set forth in the appended claims.
    Exemplary embodiments may be summarized as follows:
    A. A surface/interface passivation layer for a high-efficiency crystalline silicon cell, comprising:
    a passivation layer disposed on a front surface of a n+-type doped layer of a p-type crystalline silicon cell, which has a four-layer laminated structure of a-SiOx:H (2 nm)/aSiNx:H (2.18, 10 nm)/a-SiNx:H (2.08, 30 nm)/a-SiOx:H (110 nm) in sequence; and a passivation layer disposed on a back surface of a p-type silicon substrate of the p-type crystalline silicon cell, which has a four-layer laminated structure of a-SiOx:H (2 nmj/AbOs (15 nm)/a-SiOx:H (220 nm)/a-SiNx:H (2.08, 80 nm) in sequence.
    B. The surface/interface passivation layer for a high-efficiency crystalline silicon solar cell according to embodiment A, wherein the p-type crystalline silicon cell is a p-type PERC cell.
    C. A passivation method for a high-efficiency crystalline silicon cell, comprising steps of:
    (1) passivation of a front surface of n+-type doped layer, comprising:
    preparing hydrogenated amorphous silicon oxide (a-SiOx:H) by plasma enhanced chemical vapor deposition (PECVD); and preparing two layers of hydrogenated amorphous silicon nitride (a-SiNx:H) with different refractive indices on the a-SiOx:H by PECVD;
    depositing a-SiOx:H by PECVD, to finally form a passivation film having a fourlayer laminated structure of a-SiOx:H (2 nm)/a-SiNx:H (2.18, 10 nm)/a-SiNx:H (2.08, 30 nm)/a-SiOx: H (110 nm);
    (2) passivation of a back surface of p-type silicon substrate, comprising preparing hydrogenated amorphous silicon oxide (a-SiOx:H) by plasma enhanced chemical vapor deposition (PECVD);
    preparing ultrathin AI2O3 on the a-SiOx:H by atomic layer deposition (ALD);
    preparing a-SiOx:H on the ultrathin AI2O3 by PECVD; and preparing a-SiNx:H by PECVD, to finally form a passivation film having a fourlayer laminated structure of a-SiOx:H (2 nm) /AI2O3 (15 nm)/a-SiOx:H (220 nm)/a15
    SiNx:H(2.08, 80 nm).
    D. The passivation method according to embodiment C, wherein the step of preparing aSiOx:H by PECVD comprises:
    cleaning and inserting a silicon chip into a graphite boat;
    depositing a layer of a-SiOx:H in a PECVD tube by introducing silane at a flow rate of 90 seem and nitrous oxide at a flow rate of 3.7-4.05 slm, wherein the deposition temperature is 450°C, the pressure is 700-1500 mTor, the power is 1700-2100 watts, and the deposition time is 15-1200 s; and removing the silicon chip after deposition.
    E. The passivation method according to embodiment C, wherein the step of preparing aSiNx:Hby PECVD comprises:
    cleaning and inserting a silicon chip into a graphite boat;
    depositing a layer of a-SiNx:H in a PECVD tube by introducing silane at a flow rate of 500-650 seem and ammonia at a flow rate of 3.75-4.05 slm, wherein the deposition temperature is 450°C, the pressure is 1500-1600 mTor, the power is 1700 watts, and the deposition time is 350-1100 s; and removing the silicon chip after deposition.
    F. The passivation method according to embodiment C, wherein the step of preparing ultrathin AI2O3 by ALD comprises:
    cleaning and automatically transferring a silicon chip from a chip box to an ALD cavity;
    depositing a Al Ox film by introducing TMA and H2O at a flow rate of 10 slm and 15 slm respectively, wherein the deposition temperature is 200°C, and the deposition time is about 15 s; and automatically transferring the silicon chip out of the ALD cavity and into a chip box after deposition.
    权利要求:
    Claims (2)
    [1]
    CONCLUSIONS:
    A surface / interface passivation layer for a high-yielding crystalline silicon cell, comprising:
    - a passivation layer on a front side of an n + -type doping layer of a p-type crystalline silicon cell, with a four-layer laminated structure in the order of aSiOx: H (2 nm) / a-SiNx: H (2.18, 10 nm) / a- SiNx: H (2.08, 30 nm) / α-SiOx: H (110 nm); and
    - a passivating layer on a backside of a p-type silicon substrate of the p-type crystalline silicon cell, with a four-layer laminated structure in the order of aSiOx: H (2 nm) / Al 2 O 3 (15 nm) / a-SiOx: H (220 nm) α-SiN x: H (2.08, 80 nm).
    The surface / interface passivation layer for a high-efficiency crystalline silicon solar cell according to claim 1, wherein the p-type crystalline silicon cell is a p-type PERC cell.
    3. A passivation method for a high-yielding crystalline silicon cell, comprising the steps of:
    (1) passivating a front side of an n + type doping layer, comprising:
    - preparing hydrogenated amorphous silica (α-SiOx: H) by plasma enhanced chemical vapor deposition (PECVD); and
    - preparing two layers of hydrogenated amorphous silicon nitride (α-SiNx: H) with different refractive indices on the α-SiOx: H by PECVD;
    - precipitation of α-SiOx: H by PECVD to form a passivation film with a four-layer laminated structure of α-SiOx: H (2.18, 10 nm) / α-SiNx: H (2.18, 10 nm) / αSiNx: H ( 2.08, 30 nm) / α-SiOx: H (110 nm);
    [2]
    (2) passivating a rear side of a p-type silicon substrate, comprising:
    - preparing hydrogenated amorphous silica (α-SiOx: H) by plasma enhanced chemical vapor deposition (PECVD);
    - preparing ultra-thin Al 2 O 3 on the α-SiOx: H by atomic layer position (ALD);
    - preparing a-SiOx: H on the ultra-thin Al2O3 by PECVD; and
    - preparing a-SiNx: H by PECVD, to form a passivation film with a four-layer laminated structure of a-SiOx: H (2 nm) / Al 2 O 3 (15 nm) / a-SiOx: H (220 nm) / a -SiNx: H (2.08, 80 nm).
    The passivation method according to claim 3, wherein the step of preparing α-SiOx: H by PECVD comprises:
    - cleaning and inserting a silicon chip into a graphite tub;
    - depositing a layer of α-SiOx: H in a PECVD tube by introducing silane with a flow rate of 90 sccm and nitrous oxide with a flow rate of 3.74.05 sim, the deposition temperature being 450 ° C, the pressure 700- Is 1500 mTor, the power is 1700-2100 watts and the deposition time is 15-1200 s; and
    - removing the silicon chip after the precipitation.
    The passivation method according to claim 3, wherein the step of preparing α-SiNx: H by PECVD comprises:
    - cleaning and inserting a silicon chip into a graphite tub;
    - depositing a layer of α-SiNx: H in a PECVD tube by introducing silane with a flow rate of 500-650 sccm and ammonia with a flow rate of 3,754.05 sim, where the deposition temperature is 450 ° C, the pressure Is 1500-1600 mTor, the power is 1700 watts and the deposition time is 350-1100 s; and
    - removing the silicon chip after the precipitation.
    The passivation method according to claim 3, wherein the step of preparing ultra-thin Al 2 O 3 by ALD comprises:
    - the cleaning and automatic transfer of a silicon chip from a chip box to an ALD space;
    - depositing an AlOx film by TMA and H2O with a flow rate of 10 sim and 15 sim, respectively, wherein the deposition temperature is 200 ° C and the deposition time is approximately 15 s; and
    - the automatic transfer of the silicon chip from the ALD space and into a chip box after precipitation.
    1/2 a-SiOx: H <x -SiNx: H (2) u-SiNx: H (1j a-SiOx: H
    H
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    同族专利:
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    CN109216473A|2019-01-15|
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    NL2022817B1|2019-10-03|
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