• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Provided is a semiconductor device 1 which includes: a semiconductor chip 3; and a lead 4 which includes an electrode connecting portion 41 electrically connected to the semiconductor chip 5 3 via solder 6, and a protruding portion 42 protruding toward an outside from a periphery of the electrode connecting portion 41 wherein the lead 4 has a solder material flow-out preventing groove forming region R2 which traverses from one end to the other end of the lead 4 along a width direction W of the lead 4 on a surface of the protruding portion 42 on a semiconductor chip 3 side. According to the semiconductor device of the present invention, even when a solder 10 between the semiconductor chip and the lead has a large wall thickness, it is possible to prevent a solder material from flowing out to an undesired place on the lead at the time of manufacturing the semiconductor device.
    公开号:NL2022617A
    申请号:NL2022617
    申请日:2019-02-21
    公开日:2019-09-06
    发明作者:Nakagawa Masao；Kuwano Ryoji；Shinotake Yohei
    申请人:Shindengen Electric Mfg；
    IPC主号:
    专利说明:

    DESCRIPTION
    Title of the Invention: SEMICONDUCTOR DEVICE
    Technical Field [0001]
    The present invention relates to a semiconductor device.
    Background Art [0002]
    There has been known a semiconductor device where a lead on which a groove is formed for preventing the flow-out of a solder material at the time of manufacturing the semiconductor device is joined to a semiconductor chip by soldering (see patent literature 1, for example).
    [0003]
    In a conventional semiconductor device 901 described in patent literature 1, as shown in Fig. 7(a) and Fig. 7(b), an annular solder material flow-out preventing groove 944 is formed on the outside of an electrode connecting surface 941a of an electrode connecting portion 941 of a lead 904 joined to a semiconductor chip 903 by soldering. The solder material flow-out preventing groove 944 prevents a solder material mounted on (applied by coating to) the center of the electrode connecting surface 941a from flowing out due to wettability of the solder material at the time of manufacturing the semiconductor device 901.
    [0004]
    The conventional semiconductor device 901 described in patent literature 1 is provided on the premise that, as show'n in Fig. 7(C), at the time of manufacturing the semiconductor device 901, a solder material is applied by coating to a center portion of the electrode connecting surface 941a (see Fig.7 (cl)), and the solder material is spread with wettability (see Fig.7 (c2)) so that the solder material covers a desired range (see Fig.7 (c3)). In the semiconductor device 901, a zone 943 which spreads while extending radially from the center for making wettability different between the inside and the outside of the zone is formed in a region inside the solder material flow'-oul preventing groove 944. With such a zone 943, it is possible to prevent the solder material applied by coating to the center portion of the electrode connecting surface 941a from spreading by wetting beyond the desired range.
    Citation List
    Patent Literature [0005]
    PTL 1: JP 2012-125786 A
    PTL2: JP 2017-199809 A
    Summary of Invention
    Technical Problem [0006]
    In general, there has been known that, to relax a stress (particularly a thermal stress) which acts on solder between a semiconductor chip and a lead, it is effective to increase a thickness of the solder to a fixed value or more (see patent literature 2, for example).
    [0007]
    However, the solder material flow-out preventing groove 944 formed in the conventional semiconductor device 901 described in patent literature 1 has a narrow groove width. Accordingly, the conventional semiconductor device 901 has a following drawback. That is, the flow-out of a solder material having a small thickness which spreads with wettability by being applied by coating to a center portion of the electrode connecting surface 941a can be prevented. However, in the case where it is necessary to form solder having a large thickness described in patent literature 2, when a large amount of solder material flows on a surface of the lead 904, it is difficult to prevent the solder material 941 from flowing-out to the outside of the solder material flow-out preventing groove 944.
    [0008]
    The present invention has been made to overcome the above-mentioned drawback, and it is an object of present invention to provide a semiconductor device capable of preventing a solder material from flowing out to an undesired place on a lead at the time of manufacturing a semiconductor device even when solder between a semiconductor chip and a lead is formed with a large thickness.
    Solution to Problem [0009] [1J A semiconductor device according to present invention includes: a semiconductor chip; and a lead including an electrode connecting portion electrically connected to the semiconductor chip via solder, and a protruding portion protruding toward an outside from the electrode connecting portion as viewed in a plan view, wherein the lead has a solder material flow-out preventing groove forming region which traverses from one end to the other end of the lead along a width direction of the lead on a surface of the protruding portion on a semiconductor chip side.
    [0010] [2] In the semiconductor device according to the present invention, it is preferable that a plurality of grooves be formed in the solder material flow-out preventing groove forming region.
    [0011] [3J In the semiconductor device according to the present invention, the respective grooves formed in the solder material flow-out preventing groove forming region may be arranged parallel to each other and may be inclined with respect to the width direction as viewed in a plan view.
    [0012] [4] In the semiconductor device according to the present invention, the respective grooves formed in the solder material flow-out preventing groove forming region may be arranged parallel to each other and may extend along the width direction.
    [0013] [5] In the semiconductor device according to the present invention, it is preferable that the lead further have a semiconductor chip fixing groove forming region where a plurality of grooves are formed over an entire surface of an electrode connecting surface of the electrode connecting portion to which the semiconductor chip is connected.
    [0014] [6] In the semiconductor device according to the present invention, it is preferable that the semiconductor chip fixing groove forming region have a first semiconductor chip fixing groove group which is a mass of grooves extending in a first direction and a second semiconductor chip fixing groove group which is a mass of grooves extending in a second direction which intersects with the first direction as the plurality of grooves.
    [0015] [7] In the semiconductor device according to the present invention, it is preferable that the lead further include an external connecting terminal for connection with an outside of the semiconductor device, and have an external connecting terminal joining portion which protrudes from the electrode connecting portion toward the external connecting terminal and a bulging portion which protrudes in a direction different from the external connecting terminal joining portion as the protruding portion, and the bulging portion protrude to an outside of a profile of the semiconductor chip and an outside of a profile of the substrate in a case where the semiconductor chip is mounted on the substrate as viewed in a plan view.
    [0016] [8] In the semiconductor device according to the present invention, it is preferable that the lead further include an external connecting terminal, and have an external connecting terminal joining portion which protrudes from the electrode connecting portion toward the external connecting terminal and a bulging portion which protrudes in a direction different from the external connecting terminal joining portion as the protruding portion, and the bulging portion protrudes to an outside of a substrate on which the semiconductor chip is mounted as viewed in a plan view.
    [0017] [9] In the semiconductor device according to the present invention, it is preferable that the lead have the solder material flow-out preventing groove forming region in the bulging portion.
    [0018] [10] In the semiconductor device according to the present invention, it is preferable that the lead further have a stress relaxing groove forming region which partially overlaps with the solder material flow-out preventing groove forming region as viewed in a plan view and in which a plurality of grooves tire formed on a surface of the protruding portion on a side opposite to a semiconductor chip side.
    Advantageous Effects of Invention [0019]
    According to the semiconductor device of the present invention, the lead has the solder material flow-out preventing groove forming region which traverses from one end to the other end of the lead along the width direction of the lead on the surface of the protruding portion on a semiconductor chip side. Accordingly, even when a solder material between the semiconductor chip and the lead is formed with a large wall thickness at the time of manufacturing the semiconductor device, it is possible to dam up a melted solder material with certainty in the solder material flow-out preventing groove forming region having a large width in a direction perpendicular to a width direction of the lead. Further, the solder material flow-out preventing groove forming region traverses from one end to the other end of the lead along the width direction of the lead and hence, it is possible to block a path along which the melted solder material flows on the surface of the lead. Accordingly, even in the case where solder between the semiconductor chip and the lead is formed with a large wall thickness, it is possible to prevent a solder material from flowing out to an undesired place on the lead at the time of manufacturing the semiconductor device.
    Brief Description of Drawings [0020]
    Fig. 1 is a schematic view for describing a semiconductor device 1 according to an embodiment. Fig. 1(a) is a top plan view of the semiconductor device 1 showing the inside of the semiconductor device 1 in a see-through manner. Fig. 1(b) is a cross-sectional view taken along a line A-A.
    Fig. 2 is a schematic view showing a state of the semiconductor device 1 according to the embodiment where resin sealing is not yet performed in steps of manufacturing the semiconductor device 1. Fig. 2(a) is a top plan view of an intermediate body IM of the semiconductor device 1. Fig. 2(b) is a side view of the intermediate body IM of the semiconductor device 1.
    Fig. 3 is a schematic view for describing an electrode connecting member 4g of a lead 4 of the semiconductor device 1 according to the embodiment. Fig. 3(a) is a bottom plan view of the electrode connecting member 4g. Fig. 3(b) is a cross-sectional view taken along a line B-B. Fig. 3(c) is an enlarged view of a portion C. Fig. 3(d) is an enlarged view of a portion D.
    Fig. 4 is a flowchart of a method of manufacturing a semiconductor device according to the embodiment.
    Fig. 5 is a schematic view for describing the method of manufacturing a semiconductor device according to the embodiment. Fig. 5(a) to (f) describe respective steps.
    Fig. 6 is a schematic view for describing modifications of a groove pattern in a solder material flow-out preventing groove forming region R2 of the semiconductor device 1 according to the embodiment. Fig. 6(a) shows a modification 1. Fig. 6(b) show's a modification 2. Fig. 6(c) shows a modification 3.
    Fig. 7 is a schematic view for describing a conventional semiconductor device 901. Fig. 7(a) is a top plan view of the conventional semiconductor device 901. Fig. 7(b) is cross-sectional view taken along a line Z-Z. Fig. 7(c) is a schematic view for describing spreading of a solder material in the conventional semiconductor device 901. In Fig. 7(c), a change with time of spreading of the solder material is shown sequentially in order of (cl) to (c3). In Fig. 7, symbol 906 indicates solder.
    Mode for Carrying out the Invention [0021]
    Hereinafter, a semiconductor device according to the present invention is described based on an embodiment shown in the drawings. The respective drawings are schematic views, and do not always strictly reflect actual sizes. With respect to “solder material” and “solder”, in this specification, the description is made using different names corresponding to the difference before and after hardening by reflowing. However, the same symbol is affixed to “solder material” and “solder” disposed in the same place.
    [0022] (1. Configuration of semiconductor device 1 according to embodiment)
    As shown in Fig. 1, a semiconductor device 1 according to the embodiment includes a substrate 2, a semiconductor chip 3, leads 4 (4a, 4b, and 4c), solders 5, 6, and a wire 7. These components are resin-sealed by a resin 8 except for external connecting terminals 4d, 4e, and 4f of the leads 4(4a, 4b, 4c) and a portion of a heat radiation metal plate 2d of the substrate 2.
    [0023]
    The substrate 2 is a substrate having a semiconductor chip mounting surface 2b. A suitable substrate (for example, a printed-circuit board) can be used as the substrate 2. In this embodiment, as the substrate 2, a direct copper bonding (DCB) substrate having: an insulating base member 2a; a circuit 2c formed on one surface of the insulating base member 2a and having the semiconductor chip mounting surface 2b: and a heat radiation metal plate 2d formed on the other surface of the insulating base member 2a is used. A portion of the heat radiation metal plate 2d is exposed from the resin 8.
    [0024]
    The semiconductor chip 3 is an IGBT having: a collector electrode 3a formed on one surface (a surface on a substrate 2 side); and an emitter electrode 3b (electrode) and a gate electrode 3c formed on the other surface (a surface on a side opposite to the surface on the substrate 2 side). The gate electrode 3c is formed at the position spaced apart from the emitter electrode 3b.
    [0025]
    The collector electrode 3a is joined to a connecting pad (of the circuit 2c) formed on the semiconductor chip mounting surface 2b of the substrate 2 via solder 5, and the collector electrode 3a is connected to the outside via the solder 5, the substrate 2 (circuit 2c), and the lead 4a (external connecting terminal 4d).
    The emitter electrode 3b is joined to an electrode connecting member 4g of the lead 4b via solder 6, and is connected to the outside via the solder 6 and the lead 4b (external connecting terminal 4e).
    [0026]
    The leads 4a, 4b, and 4c are flat-plate-like metal members. The leads 4a, 4b, and 4c are formed by cutting out portions of a lead frame. The leads 4a, 4b, and 4c respectively have a larger cross-sectional area than the wire so that a large electric current can flow through the leads 4a, 4b, and 4c.
    One end portion of the lead 4a is connected to the circuit 2c of the substrate 2 connected to the collector electrode 3a via the connecting pad formed on the semiconductor chip mounting surface 2b of the substrate 2, and the other end portion of the lead 4a forms an external connecting terminal 4d.
    An electrode connecting member 4g for connection with the emitter electrode 3b is formed on one end portion of the lead 4b, and the external connecting terminal 4e for connection with the outside is formed on the other end portion of the lead 4b. The electrode connecting member 4g of the lead 4b is described in detail after the entire configuration of the semiconductor device 1 is described.
    One end portion of the lead 4c is connected to the gate electrode 3c via the wire 7, and the other end portion of the lead 4c forms an external connecting terminal 4f.
    [0027]
    The solders 5, 6 are made of an alloy or metal having conductivity and adhesiveness. The solders 5, 6 are formed by melting the solder materials by heating and by solidifying the melted solder materials.
    The solder 5 joins the collector electrode 3a and the electrode pad formed on the semiconductor chip mounting surface 2b. The solder 5 is formed of a solder material in a paste form (so-called cream solder) which contains a flux. The solder 5 is disposed on the semiconductor chip mounting surface 2b of the substrate 2 by printing, and the substrate 2 and the semiconductor chip 3 are joined to each other by heating the solder 5 by reflowing. Unlike the solder 6, the solder 5 is not in a situation where a stress (for example, a thermal stress) which acts on the solder is to be relaxed. Accordingly, in view of a fact that the thicker the solder, the larger a conduction loss becomes, it is preferable that solder 5 be reasonably thin.
    The solder 6 joins the emitter electrode 3b and the electrode connecting member 4g to each other. A thickness of the solder 6 (solder thickness) is larger than a thickness of the solder 5 (the solder between the substrate 2 and the semiconductor chip 3). For example, the thickness of the solder 6 is 300 pm or more, and is 500 pm, for example.
    [0028]
    The wire 7 is a wire for wire bonding. A suitable resin can be used as the resin 8. [0029]
    Hereinafter, the description is made with respect to an intermediate body IM of the semiconductor device in a state shown in Fig. 2 where resin sealing is not yet performed in steps of manufacturing the semiconductor device 1. In the intermediate body IM of the semiconductor device, the respective leads 4a, 4b, and 4c form portions of a lead frame 9, and are connected to a frame-like peripheral portion 9a described later. Working such as bending is not applied to the external connecting terminals.
    [0030]
    The lead frame 9 is a rectangular metal-made thin plate. The lead frame 9 includes a frame-like peripheral portion 9a which forms a periphery, a lead forming portion 9b formed inside the peripheral portion 9a, and connecting portions 9c which connect the peripheral portion 9a and the lead forming portions 9b to each other. The leads 4a, 4b, and 4c are formed on the lead forming portions 9b. In manufacturing steps, the connecting portions 9c of the lead frame 9 are cut so that the leads 4a, 4b, and 4c formed on the lead forming portions 9b are cut away from the peripheral portion 9a.
    [0031] (2. Configuration of electrode connecting member 4g of lead 4 according to embodiment)
    As shown in Fig. 3(a) and (b), the electrode connecting member 4g of the lead 4 includes: an electrode connecting portion 41 electrically connected to the semiconductor chip 3 via the solder 6; and protruding portions 42 which protrude toward the outside from the electrode connecting portion 41 as viewed in a plan view.
    [0032]
    The electrode connecting portion 41 is connected to the semiconductor chip 3 on an electrode connecting surface 41 a on one side (a lower side in Fig. 3(b)) via the solder 6 having a large thickness. The electrode connecting surface 41a has a semiconductor chip fixing groove forming region R1 where a plurality of semiconductor chip fixing grooves 43 are formed on an entire surface of the electrode connecting surface 41a. The semiconductor chip fixing groove forming region R1 is described later.
    [0033]
    The lead 4 includes, as the protruding portions 42, an external connecting terminal joining portion 42a which protrudes from the electrode connecting portion 41 to the external connecting terminal 4e, and bulging portions 42b which protrude in a direction different from a direction that the external connecting terminal joining portion 42a protrudes (in Fig. 3(a), the external connecting terminal joining portion 42a protruding in a direction on a right side, and the bulging portions 42b protruding in directions on a left side).
    [0034]
    An extending end of the external connecting terminal joining portion 42a is connected to the external connecting terminal 4e (see Fig. 1(a)). The external connecting terminal joining portion 42a has a solder material flow-out preventing groove forming region R2 where a plurality of solder material flow'-out preventing grooves 44 are formed on a surface of the external connecting terminal joining portion 42a on a semiconductor chip 3 side (a surface connected with the electrode connecting surface 41a). The solder material flow-out preventing groove forming region R2 traverses from one end to the other end of the lead 4 along a width direction W of the lead 4 with a width (a width in a direction L perpendicular to the width direction W of the lead 4). Further, the external connecting terminal joining portion 42a has a stress relaxing groove forming region R3 on a surface of the lead 4 on a side opposite to a semiconductor chip 3 side. The stress relaxing groove forming region R3 partially overlaps with the solder material flow-out preventing groove forming region R2 as viewed in a plan view. Stress relaxing grooves 45 are formed in the stress relaxing groove forming region R3. The solder material flow'-out preventing groove forming region R2 and the stress relaxing groove forming region R3 are described later.
    [0035]
    As viewed in a plan view, the bulging portions 42b protrude to the outside of the semiconductor chip 3 and the outside of the substrate 2 on which the semiconductor chip 3 is mounted, and distal end portions of the bulging portions 42b form free distal end portions which are connected to nowhere. The bulging portions 42b protrudes within an inner range of the resin S (see Fig. 1(a)). The bulging portion 42b has a solder material flow'-out preventing groove forming region R2 where a plurality of solder material flow-out preventing grooves 44 are formed on a surface of the bulging portion 42b on a semiconductor chip 3 side (a surface connected to the electrode connecting surface 41a). The solder material flow-out preventing groove forming region R2 traverses from one end to the other end of the lead 4 along the width direction W of the lead 4 with a width (a width in a direction L perpendicular to the width direction W of the lead 4). The grooves formed in the solder material flow-out preventing groove forming region R2 of the bulging portion 42b and the grooves formed in the solder material flow-out preventing groove forming region R2 of the external connecting terminal joining portion 42a have substantially the same shape. [0036]
    The semiconductor chip fixing groove forming region R1 is a range where the semiconductor chip fixing grooves 43 which cover the electrode connecting surface 41a are formed on a surface of the electrode connecting portion 41 on a semiconductor chip 3 side. A plurality of semiconductor chip fixing grooves 43 are formed in the semiconductor chip fixing groove forming region R1. As shown in Fig. 3(b), the semiconductor chip fixing grooves 43 are grooves indented in a triangular (V-shaped) cross section. As shown in Fig. 3(a) and Fig. 3(c), the semiconductor chip fixing grooves 43 are grooves which extend in a straight line shape within the semiconductor chip fixing groove forming region R1. The respective semiconductor chip fixing grooves 43 are arranged at an equal pitch. In the semiconductor chip fixing groove forming region Rl, as the plurality of semiconductor chip fixing grooves 43, the semiconductor chip fixing grooves 43 which are arranged parallel to each other, extend in a first direction (a direction inclined obliquely in a leftward direction by 45° with respect to a vertical direction in Fig. 3(c)) and form a first semiconductor chip fixing groove group 43a, and the semiconductor chip fixing grooves 43 which are arranged parallel to each other, extend in a second direction (a direction inclined obliquely in a rightward direction by 45° with respect to the vertical direction in Fig. 3(c)) and form a second semiconductor chip fixing groove group 43b are formed. In this manner, with respect to the semiconductor chip fixing grooves 43 formed within the semiconductor chip fixing groove forming region Rl, the semiconductor chip fixing grooves 43 which form the first semiconductor chip fixing groove group 43a and the semiconductor chip fixing grooves 43 which form the second semiconductor chip fixing groove group 43b intersect with each other thus forming a mesh-like groove pattern within the semiconductor chip fixing groove forming region Rl. In the semiconductor device 1, the solder 6 enters the respective semiconductor chip fixing grooves 43 over the entire surface within the semiconductor chip fixing groove forming region Rl, and is firmly fixed to the semiconductor chip fixing grooves 43 in an anchoring manner.
    [0037]
    The solder material flow-out preventing groove forming region R2 is a range which extends over a full length of the lead 4 in a width direction W and in which the solder material flow-out preventing grooves 44 are formed on a surface of the protruding portion 42 (external connecting terminal joining portion 42a, bulging portions 42b) on a side opposite to the semiconductor chip 3 side. A plurality of solder material flow-out preventing grooves 44 are formed in the solder material flow-out preventing groove forming region R2. As shown in Fig. 3(b), the solder material flow-out preventing grooves 44 are grooves indented in a triangular (V-shaped) cross section. As shown in Fig. 3(a) and (d), the solder material flow-out preventing grooves 44 are grooves which extend in a straight line shape within the solder material flow-out preventing groove forming region R2. The respective solder material flow-out preventing grooves 44 are arranged at an equal pitch. In the solder material flow-out preventing groove forming region R2, as the plurality of solder material flow-out preventing grooves 44, the solder material flow-out preventing grooves 44 which are arranged parallel to each other, extend in a first direction (a direction inclined obliquely in a leftward direction by 45° with respect to a vertical direction in Fig. 3(d)) and form a first solder material flow-out preventing groove group 44a, and the solder material flow-out preventing grooves 44 which are arranged parallel to each other, extend (in a direction inclined obliquely in a rightward direction by 45° with respect to the vertical direction in Fig. 3(d)) and form the first solder material flow-out preventing groove group 44b are formed. In this manner, with respect to the solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2, the solder material flow-out preventing grooves 44 which form the first solder material flow-out preventing groove group 44a and the solder material flow-out preventing grooves 44 which form the second solder material flow-out preventing groove group 44b intersect with each other. Accordingly, the solder material flow-out preventing grooves 44 form a groove pattern having a width where rectangular zones are arranged in the width direction W of the lead 4 (a width in a direction perpendicular to the width direction W of the lead 4) within the solder material flow-out preventing groove forming region R2.
    [0038]
    The stress relaxing groove forming region R3 is a range which extends over a full length in a width direction W of the lead 4 and in which stress relaxing grooves 45 are formed on a surface of the external connecting terminal joining portion 42a on a side opposite to the semiconductor chip 3 side. A plurality of stress relaxing grooves 45 are formed in the stress relaxing groove forming region R3. As shown in Fig. 3(b), the stress relaxing groove 45 is a groove indented in a triangular (V-shaped) cross section. In the stress relaxing groove forming region R3, a groove pattern formed of the stress relaxing grooves 45 can be formed in the same manner as the groove pattern formed within the solder material flow-out preventing groove forming region R2. In this case, it is preferable that the stress relaxing grooves 45 be formed in a displaced manner relative to the solder material flow-out preventing grooves 44 such that the stress relaxing grooves 45 do not overlap with the solder material flow-out preventing grooves 44 as viewed in a plan view for suppressing a change in a thickness of the lead 4.
    [0039] (3. Method of manufacturing semiconductor device 1 according to embodiment)
    As shown in Fig. 4 and Fig. 5, the method of manufacturing the semiconductor device 1 according to the embodiment includes, in the following order, a substrate arranging step SI, a solder material printing step S2, a semiconductor chip mounting step S3, a solder material mounting step S4, a lead frame arranging step S5, a solder joining step S6, a wire connecting step S7, a resin sealing step S8, and a lead working step S9.
    [0040] (1) Substrate arranging step SI
    In the substrate arranging step S1, the substrate 2 on which the semiconductor chip 3 is scheduled to be mounted is arranged on a receiving platform J1 arranged horizontally in a state where the semiconductor chip mounting surface 2b faces upward, (see Fig. 5(a)).
    [0041] (2) Solder material printing step S2
    In the solder material printing step S2, the solder material 5 in a paste form (so-called cream solder) is printed on the semiconductor chip mounting surface 2b which forms tin upper surface of the substrate 2(see Fig. 5(b)).
    In the embodiment, the solder material 5 is printed on the semiconductor chip mounting surface 2b. However, the solder material may be supplied in a suitable method such as supplying the solder material by a dispenser, supplying the solder material in the form of a wire solder fed by a solder feeder or the like, or supplying the solder material by making a melted solder material flow onto the semiconductor chip mounting surface 2b.
    [0042] (3) Semiconductor chip mounting step S3 hi the semiconductor chip mounting step S3, the semiconductor chip 3 is mounted on the semiconductor chip mounting surface 2b which forms the upper surface of the substrate 2 so as to bring a state where the semiconductor chip mounting surface 2b and the collector electrode 3a of the semiconductor chip 3 opposedly face each other with the solder material 5 sandwiched therebetween (see Fig. 1(b), Fig. 5(c)).
    [0043] (4) Solder material mounting step S4
    In the solder material mounting step S4, the solder material 6 is mounted on the emitter electrode 3b of the semiconductor chip 3 (see Fig. 1(b), Fig. 5(d)). The solder material 6 is mounted with a thickness sufficiently large for joining the emitter electrode 3b and the electrode connecting member 4g of the lead frame 9 which is mounted in the next step to each other.
    As the solder material 6, a solder material in a paste form (so-called cream solder), a solder material in a solid form (so-called plate solder) or a combination of these two solder materials can be used. Although various method are considered as a method of supplying a solder material in a paste form, it is preferable to supply a solder material in a paste form by a dispenser such that an amount of solder can be finely adjusted and a solder material can be supplied to an accurate place.
    [0044] (5) Lead frame arranging step S5
    In the lead frame arranging step S5, the lead frame 9 is arranged such that the electrode connecting member 4g of the lead 4b is made to overlap with the solder material 6 mounted on the semiconductor chip 3 from above (see Fig. 5(e)). At this stage of operation, a state is brought about where the lead 4b within the lead frame 9 is arranged at a predetermined planar position and a height position, and the solder material 6 is interposed between the emitter electrode 3b and the electrode connecting member 4g. Further, at this stage of operation, it is preferable that portions of the lead 4b such as the bulging portions 42b be disposed on a receiving jig J2 in the vicinity of the electrode connecting member 4g (in the vicinity of the substrate 2 and the semiconductor chip 3) so that the lead frame 9 be supported on the receiving platform JI in a state where a distance between the semiconductor chip 3 and the electrode connecting member 4g is held at a fixed value (see Fig. 5(f)). Still further, at this stage of operation, it is preferable that a wide range such as a peripheral portion 9a be arranged on a receiving j ig J 3 so that the lead frame 9 be supported by the receiving platform J1 in a stable state (see Fig. 5(f)).
    [0045] (6) Solder joining step (reflow step) S6
    In the solder joining step S6, while maintaining the state where the constitutional members of the semiconductor device 1 are arranged at predetermined positions by the receiving platform JI, The substrate 2, the semiconductor chip 3, and the lead frame 9 are joined to each other by soldering by heating the solder materials 5, 6 (see Fig. 5(f)). To be more specific, the constitutional members of the semiconductor device 1 held by the receiving platform J1 are put into a reflow furnace (not shown in the drawing) and are heated. The solder materials 5, 6 are melted and, thereafter, the solder materials 5, 6 are solidified so as to form solders (5, 6). Accordingly, the semiconductor chip mounting surface 2b of the substrate 2 and the collector electrode 3a of the semiconductor chip 3 are joined to each other via the solder 5, and the emitter electrode 3b of the semiconductor chip 3 and the electrode connecting member 4g of the lead 4b are joined to each other via the solder 6.
    [0046] (7) Wire connecting step S7, resin sealing step S8, and lead working step S9
    In the intermediate body IM of the semiconductor device formed by solder joining (the intermediate body IM being in a state where wire connection is not yet performed), in the wire connecting step S7 (not shown in the drawing), the gate electrodes 3c and the leads 4c are connected to each other using the wires 7. A suitable wire can be used as the wire 7. In the next resin sealing step S8 (not shown in the drawing), the intermediate body IM to which the wire connecting step S7 is applied is resin-sealed by the resin 8 except for the external connecting terminals 4d, 4e, and 4f of the leads 4a, 4b, and 4c and the metal plate 2d for heat radiation. Next, in the lead working step S9 (not shown in the drawing), the leads 4a, 4b, and 4c are cut away from the lead frame 9, and working such as bending is applied to predetermined portions.
    The semiconductor device 1 according to the embodiment is manufactured in accordance with the above-mentioned steps.
    [0047] (3. Advantageous effects according to embodiment)
    According to the semiconductor device 1 of the embodiment, the leads 4a, 4b, and 4c respectively have the solder material flow-out preventing groove forming region R2 which traverses from one end of the leads 4a, 4b, and 4c to the other end along the width direction of the leads 4a, 4b, and 4c on the surface of the protruding portions 42 on a semiconductor chip 20 side. Accordingly, even when the solder material 6 between the semiconductor chip 3 and the lead 4 is formed with a large wall thickness at the time of manufacturing the semiconductor device 1, it is possible to dam up a melted solder material 6 with certainty in the solder material flow-out preventing groove forming region R2 having a large width in the direction L perpendicular to the width direction W of the lead 4. Further, the solder material flow-out preventing groove forming region R2 traverses from one end of the lead 4 to the other end along the width direction W of the lead 4 and hence, it is possible to block a path along which the melted solder material 6 flows on the surface of the lead 4. Accordingly, even in the case where the solder 6 between the semiconductor chip 3 and the lead 4 is formed with a large wall thickness, it is possible to prevent the solder material 6 from flowing out to an undesired place on the lead 4 at the time of manufacturing the semiconductor device 1.
    [0048]
    According to the semiconductor device 1 of the embodiment, the plurality of solder material flow-out preventing grooves 44 are formed in the solder material flow-out preventing groove forming region R2. Accordingly, the solder material 6 flown into the solder material flow-out preventing groove forming region R2 enters the solder material flow-out preventing grooves 44 formed in the solder material flow-out preventing groove forming region R2 and hence, the solder material 6 minimally goes beyond the solder material flow-out preventing grooves 44.
    In this embodiment 1, the flow-out of the solder material can be prevented over the entire solder material flow-out preventing groove forming region R2 and hence, it is possible to prevent the melted solder 6 from flowing out along the surface of the lead 4 in a wide range with certainty. In the respective solder material flow-out preventing grooves 44, an internal pressure becomes low due to a capillary phenomenon. Accordingly, even when a certain amount of solder material 6 overflows from the solder material flow-out preventing groove 44, it is possible to retain the solder material 6 on the solder material flow-out preventing groove 44. Accordingly, it is possible to prevent not only the flow-out of the solder material which enters the solder material flow-out preventing groove 44 but also the flow-out of the solder material 6 around the solder material flow-out preventing groove 44.
    [0049]
    According to the semiconductor device 1 of the embodiment, the lead 4 has the semiconductor chip fixing groove forming region R1 where the plurality of semiconductor chip fixing grooves 43 are formed over the entire electrode connecting surface 41a of the electrode connecting portion 41 to which the semiconductor chip 3 is connected. Accordingly, the solder 6 is fixed in an anchoring manner and hence, a joining strength between the semiconductor chip 3 and the lead 4 can be enhanced.
    [0050]
    According to the semiconductor device 1 of the embodiment, the semiconductor chip fixing groove forming region R1 has the first semiconductor chip fixing groove group 43a which is a mass of grooves extending in the first direction and the second semiconductor chip fixing groove group 43b which is a mass of grooves extending in the second direction which intersects with the first direction as the plurality of semiconductor chip fixing grooves 43. Accordingly, the semiconductor chip 3 and the lead 4 are minimally displaced against forces from a plurality of directions and hence, a joining strength between the semiconductor chip 3 and the lead 4 can be further enhanced.
    [0051]
    According to the semiconductor device 1 of the embodiment, the lead 4 further includes the external connecting terminal 4e for connection with an outside of the semiconductor device 1, the lead 4 has the external connecting terminal joining portion 42a which protrudes from the electrode connecting portion 41 toward the external connecting terminal 4e and the bulging portions 42b which protrude in a direction different from the external connecting terminal joining portion 42a as the protruding portions 42. The bulging portion 42b protrudes to an outside of a profile of the semiconductor chip 3 and an outside of the substrate 2 on which the semiconductor chip 3 is mounted as viewed in a plan view. With such a configuration, the bulging portions 42b can be supported at the time of manufacturing the semiconductor device 1 (see Fig. 5(f)). Accordingly, a gap having a fixed distance can be formed between the semiconductor chip 3 and the lead 4 and hence, the solder 6 disposed between the semiconductor chip 3 and the lead 4 can be formed in a state where the solder 6 maintains a desired thickness. For example, it is also possible to increase a thickness of the solder 6 between the semiconductor chip 3 and the lead 4.
    [0052]
    According to the semiconductor device 1 of the embodiment, the lead 4 has the solder material flow-out preventing groove forming region R2 in the bulging portion 42b and hence, the solder material 6 does not flow out to a distal end side of the bulging portion 42b. Accordingly, it is possible to reduce a possibility that when the bulging portion 42b is supported from below at the time of manufacturing, the lead 4 is disposed in an inclined manner.
    [0053]
    According to the semiconductor device 1 of the embodiment, the lead 4 further has the stress relaxing groove forming region R3 which partially overlaps with the solder material flow-out preventing groove forming region R2 and in which a plurality of grooves are formed as viewed in a plan view on a surface of the external connecting terminal joining portion 42a on a side opposite to the semiconductor chip 3 side. With such a configuration, a deformable portion is formed on the lead 4. Accordingly, even when a stress (particularly a thermal stress) is generated, the stress is absorbed in the vicinity of the solder material flow-out preventing groove forming region R2 and hence, it is possible to suppress the propagation of stress to the solder via the lead 4 whereby reliability of the semiconductor device 1 can be enhanced.
    [0054] [Modification]
    Next, modifications 1 to 3 of a groove pattern of the solder material flow-out preventing groove forming region R2 are described. Portions having substantially the same functions as the corresponding portions of the solder material flow-out preventing groove forming region R2 shown in Fig. 2 are described using the same symbols.
    [0055]
    As shown in Fig. 6(a), the groove pattern according to the modification 1 is formed of a plurality of solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2. The solder material flow-out preventing grooves 44 are grooves which extend in a straight line shape within the solder material flow'-out preventing groove forming region R2, and extend with an inclination (in a direction inclined obliquely in a direction at an angle of 45° with respect to a vertical direction in Fig. 6(a))(inclined in a width direction). The solder material flow-out preventing grooves 44 are arranged parallel to each other at an equal pitch in a width direction W of the lead 4. In this manner, the solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2 form the groove pattern having a width where oblique straight lines overlap with each other (a width in a direction L perpendicular to the width direction W of the lead 4) within the solder material flow-out preventing groove forming region R2.
    [0056]
    As shown in Fig. 6(b), the groove pattern according to the modification 2 is formed of a plurality of solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2. The solder material flow-out preventing grooves 44 are grooves which extend in a width direction of the lead 4 (a vertical direction in Fig. 6(b)) within the solder material flow-out preventing groove forming region R2. The solder material flow-out preventing grooves 44 extend over the full width of the lead 4. The solder material flow-out preventing grooves 44 are arranged parallel to each other at an equal pitch in a direction perpendicular to the width direction W of the lead 4. In this manner, the solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2 form the groove pattern having a width where straight lines which traverse from one end to the other end along the width direction W of the lead 4 overlap with each other (the width in the direction L perpendicular to the width direction W of the lead 4) within the solder material flow-out preventing groove forming region R2.
    [0057]
    As shown in Fig. 6(c), the groove pattern according to the modification 3 is formed of a plurality of solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2. The solder material flow-out preventing grooves 44 are grooves which extend intermittently in a width direction of the lead 4 (a vertical direction in Fig. 6(c)) within the solder material flow-out preventing groove forming region R2. The solder material flow-out preventing grooves 44 are arranged parallel to each other in a staggered manner in a direction L perpendicular to the width direction W of the lead 4. In this manner, the solder material flow-out preventing grooves 44 formed within the solder material flow-out preventing groove forming region R2 form a groove pattern having a width where straight lines which extend intermittently in the width direction W of the lead 4 overlap with each other (a width in the direction L perpendicular to the width direction W of the lead 4) within the solder material flow-out preventing groove forming region R2.
    [0058]
    Even in the groove patterns according to the modifications 1 to 3, the solder material flow-out preventing grooves 44 are inclined with respect to the width direction W of the lead 4 or are arranged in a staggered manner in the direction L perpendicular to the width direction W of the lead 4 as viewed in a plan view and hence, it is possible to form the solder material flow-out preventing groove forming region R2 having the width (the width in the direction L perpendicular to the width direction W of the lead 4). The solder material flow-out preventing groove forming region R2 formed in this manner can more easily prevent the propagation of melted solder 6 on a surface of the lead 4.
    [0059]
    Although the present invention has been described heretofore based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment. Various modifications can be carried out in various modes without departing from the gist of the present invention, and the following modifications are also conceivable, for example. [0060] (1) The numbers, the shapes, the positions, the sizes and the like of the constitutional elements described in the above-mentioned embodiment are provided for an exemplifying purpose, and can be modified within a range where the advantageous effects of the present invention are not jeopardized. [0061] (2) In the above-mentioned embodiment, an IGBT is used as the semiconductor chip 3. However, the present invention is not limited to such a semiconductor chip. The semiconductor chip 3 may be any other semiconductor elements each having three terminals (for example, a MOSFET). The semiconductor chip 3 may be a semiconductor element having two terminals (for example, a diode). The semiconductor chip 3 may be a semiconductor element having four or more terminals (for example, a thyristor may be used as a semiconductor element having four terminals).
    [0062] (3) In the above-mentioned embodiment, the semiconductor device having one semiconductor chip is exemplified as the semiconductor device of the present invention. However, the present invention is not limited to such a semiconductor device. For example, a semiconductor device may have two semiconductor chips, or may have three or more semiconductor chips.
    [0063] (4) In the above-mentioned embodiment, a so-called vertical-type semiconductor device where a collector electrode is disposed on one surface of a semiconductor chip, and an emitter electrode and a gate electrode are disposed on the other surface of the semiconductor chip is used as the semiconductor device of the present invention. However, the present invention is not limited to such a semiconductor device. For example, a so-called lateral-type semiconductor device which has all electrodes on a surface of a semiconductor chip on a side opposite to a surface on a substrate side may be used as the semiconductor device of the present invention.
    [0064] (5) In the above-mentioned embodiment, the description has been made with respect to the configuration where the external connecting terminal joining portion 42a and the bulging portions 42b are formed on the same plane with respect to the electrode connecting portion 41. However, the present invention is not limited to such a configuration. For example, the external connecting terminal joining portion 42a or the bulging portions 42b may be bent at a middle portion thereof thus forming an inclined portion or a step portion with respect to the electrode connecting portion 41. In this case, a solder material flow-out preventing groove forming region R2 or a stress relaxing groove forming region R3 may be formed in the inclined portion or the stepped portion, [0065] (6) In the above-mentioned embodiment, cross sections of the respective grooves consisting of the semiconductor chip fixing grooves 43, the solder material flow-out preventing grooves 44, and the stress relaxing grooves 45 are formed in a triangular groove shape ( V shape). However, the cross sections of these grooves are not limited to a triangular groove shape. For example, the cross sections of the respective grooves may be formed in a rectangular groove shape or a semicircular groove shape. From a viewpoint of an effect of holding a melted solder material by a negative pressure generated by a capillary phenomenon, it is preferable to use a groove having an edge on a bottom surface compared to a groove having a gentle bottom surface.
    [0066] (7) In the above-mentioned embodiment, the grooves consisting of the semiconductor chip fixing grooves 43, the solder material flow-out preventing grooves 44, and the stress relaxing grooves 45 extend in a straight line shape. However, the present invention is not limited to such a configuration. For example, the grooves may extend in a wave shape. Further, a plurality of annular grooves are continuously formed such that the annular grooves extend in one direction.
    [0067] (8) In the above-mentioned embodiment, the plurality of grooves which form the semiconductor chip fixing grooves 43, the solder material flow-out preventing grooves 44, or the stress relaxing grooves 45 form the specific groove pattern where the grooves are continuously formed at a predetermined pitch. However, the present invention is not limited to such a configuration. For example, a groove pattern where such grooves are arranged at random pitches may be adopted or a plurality of groove patterns may be adopted.
    [0068] (9) In the above-mentioned embodiment, the stress relaxing groove forming region R3 is formed on the external connecting terminal joining portion 42a of the protruding portion 42. However, a stress relaxing groove forming region R3 may be formed in the bulging portion 42b.
    Reference Signs Fist [0069]
    1: semiconductor device
    2: substrate
    3: semiconductor chip
    4(4a, 4b, 4c): lead
    4d, 4e, 4f: external connecting terminal
    6: solder, solder material
    41: electrode connecting portion
    41a: electrode connecting surface
    42: protruding portion
    42a: external connecting terminal joining portion
    42b: bulging portion
    43: semiconductor chip fixing groove
    43a: groove of first semiconductor chip fixing groove group
    43b: groove of second semiconductor chip fixing groove group
    44: solder material flow-out preventing groove
    45: stress relaxing groove
    Rl: semiconductor chip fixing groove forming region
    R2: solder material flow-out preventing groove forming region
    R3: stress relaxing groove forming region
    W: width direction of lead
    L: direction perpendicular to width direction of lead
    权利要求:
    Claims (10)
    [1]
    Conclusions
    A semiconductor device comprising:
    a semiconductor chip, and a wiring comprising an electrode connection part electrically connected to the semiconductor chip via soldering, and a protruding part protruding towards an outside from the electrode connection part as viewed from a top view, the wiring further comprising a external connection terminal (English: "connecting terminal"), and has an external connection terminal connection part (English: "external connecting terminal joining portion") protruding from the electrode connection part to the external connection terminal and a protruding part protruding in a direction different from the external connection terminal connecting part as the protruding part, and the protruding part protrudes to an outside of the semiconductor chip and a distal end part of the protruding part is not connected to anything as viewed from a plan view.
    [2]
    The semiconductor device according to claim 1, wherein the protruding part protrudes to an outside of a substrate on which the semiconductor chip is mounted as viewed from a top view.
    [3]
    3. A semiconductor device as claimed in claim 1 or 2, wherein the wiring has a solder material outflow prevention grooves forming region, which protrudes from one end to another end of the wiring along a width direction of the wiring on a surface of the projection on a semiconductor chip side.
    [4]
    The semiconductor device according to any of claims 1 to 3, wherein a plurality of grooves are formed in the forming area for solder material outflow prevention grooves.
    [5]
    The semiconductor device according to claim 4, wherein respective grooves formed in the formation area for solder material outflow prevention grooves are arranged parallel to each other and are inclined with respect to the width direction as viewed from a top view.
    [6]
    The semiconductor device as claimed in claim 4, wherein respective grooves formed in the formation area for solder material outflow prevention grooves are arranged parallel to each other and extend along the width direction.
    [7]
    The semiconductor device according to any one of claims 1 to 6, wherein the wiring further has a semiconductor chip fixing groove forming region formation area where a plurality of grooves are formed over an entire surface of an electrode connection surface of the electrode connection part to which the semiconductor chip is connected.
    [8]
    The semiconductor device according to claim 7, wherein the semiconductor chip attachment groove forming region has a first semiconductor chip attachment grooves group that is a set of grooves extending in a first direction and a second semiconductor chip attachment grooves group that is a collection of grooves located extending in a second direction that traverses the first direction as the plurality of grooves.
    [9]
    The semiconductor device according to any of claims 1 to 8, wherein the wiring has the formation area for solder material outflow prevention grooves in the protruding part.
    [10]
    The semiconductor device according to any of claims 1 to 9, wherein the wiring further comprises a stress relaxation groove forming region formation area that partially overlaps with the solder material outflow prevention formation area as viewed from a plan view and wherein a plurality of grooves are formed on a surface of the projection on a side opposite a semiconductor chip side.
    1/7
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    同族专利:
    公开号 | 公开日
    JP6619119B1|2019-12-11|
    WO2019167218A1|2019-09-06|
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    NL2022617B1|2020-02-10|
    JPWO2019167218A1|2020-04-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JP2012125786A|2010-12-14|2012-07-05|Denso Corp|Semiconductor device|
    DE102014104819A1|2014-03-26|2015-10-01|Heraeus Deutschland GmbH & Co. KG|Carrier and / or clip for semiconductor elements, semiconductor device and method of manufacture|
    EP3002782A1|2014-09-25|2016-04-06|Renesas Electronics Corporation|Semiconductor device and manufacturing method thereof|
    US9496208B1|2016-02-25|2016-11-15|Texas Instruments Incorporated|Semiconductor device having compliant and crack-arresting interconnect structure|
    JP2017199809A|2016-04-27|2017-11-02|三菱電機株式会社|Power semiconductor device|
    JPS5525391U|1978-08-08|1980-02-19|
    JPH0218955A|1988-07-07|1990-01-23|Mitsui High Tec Inc|Lead frame for semiconductor device|
    JPH04199557A|1990-11-28|1992-07-20|Mitsubishi Electric Corp|Lead frame for semiconductor device|
    JP4281050B2|2003-03-31|2009-06-17|株式会社デンソー|Semiconductor device|
    JP6305302B2|2014-10-02|2018-04-04|三菱電機株式会社|Semiconductor device and manufacturing method thereof|
    US10181445B2|2014-12-29|2019-01-15|Mitsubishi Electric Corporation|Power module|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    PCT/JP2018/007731|WO2019167218A1|2018-03-01|2018-03-01|Semiconductor device|
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