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    • 专利摘要:
    The invention relates to a method of generating and authenticating guaranteed unique identifier codes (CID) as may be used for identifying and authenticating assets comprising an 5 integrated circuit, the method comprising; generating guaranteed unique identifiers (AID) in a centralized code registration system (3); storing the generated identifiers (AID) within a data storage (31a-31c); associating each identifier (AID) with an unique identification (CID) to be used for identifying an integrated circuit, by applying a bijective algorithm; authenticating an identification code (CID) by inversely calculating an identificatier (AID) from an 10 identification code (CID)based on said algorithm. [+FIG. 1] 1044044
    公开号:NL1044044A
    申请号:NL1044044
    申请日:2021-05-28
    公开日:2021-12-01
    发明作者:Werner Hooijmans Pieter；Anthonius Henricus Juffermans Casparus；Mathias Doumen Jeroen
    申请人:Sandgrain B V；
    IPC主号:
    专利说明:

    [0001] [0001] The present invention relates to a method for handling identification codes of integrated circuits in a centralized code registration system, a method of manufacturing an integrated circuit for use with a centralized code registration system, a centralized code registration system, an integrated circuit for use with a centralized code registration system, and use of an integrated circuit with a centralized code registration system.BACKGROUND ART
    [0002] [0002] Over the last three decades, integrated circuit (IC)-based identification and security- based technologies and associated devices have reached a broad set of applications. Well- known examples are public transport ticketing, smart card conditional access systems for TV subscriptions, SIM cards in mobile phones, electronic passports, banking or credit cards, and labeling for tracking and managing logistic flows and transport. Volumes associated with these applications run in the billions of ICs per year. However, there are potentially many more applications that could use these technologies, that could further multiply these volumes by several orders of magnitude, so indeed hundreds of billions or trillions of IC’s. So far this is not happening for two fundamental reasons: security and cost.
    [0003] [0003] A main problem in the world of identification and security is hacking. Existing identification and security applications are typically built around so-called secure microcontrollers. Microcontroller units (MCU) are required for functions like authentication or security key generation, and storing of the relevant data in such a way that it is not accessible for intruders. Because MCUs typically operate under an operating system and a specific program, e.g. firmware program, to execute the required functions, they are typically a combined hardware (HW) and software (SW) solution.
    [0004] [0004] Known systems have as a major drawback that they can be hacked. This in practice means reverse engineering the function of the device by analyzing its HW and/or SW behavior, resulting in the discovery of e.g. a secret (cryptographic) key as typically required in these known systems and stored in a memory. In a worst-case scenario, the memory content of the device is altered, e.g. by increasing the amount of credits on a transit card or changing the balance on a bank card. Although suppliers of these ICs and systems implement
    [0005] [0005] The other problem with existing security solutions is related to cost. With high- volume applications of IC related security solutions, an obvious requirement is to have the IC cost as low as possible. Today’s ICs typically cost a few dollar cents, which multiplies by a factor four for the final assembled module or package sales price. Elements that increase the IC cost are the MCU infrastructure and the programmable on-chip memories. Typical elements that increase the IC cost are: - Secure MCUs are expensive, either as in-house development or as purchased IP, e.g. as ARMTM Secure Cores; - MCUs are complex functions, and although the core is relatively small in advanced technology, it requires all kind of peripheral functionality to make it work properly: communication busses, memories (usually a combination of multiple specific memories, like RAM, ROM, Flash), start-on and advanced power management circuitry. So, the total function is much bigger, and requires serious design effort; - The simplest identification products don’t require re-programmable memories or keys. But even so, during manufacturing of the IC the code needs somehow be written in its memory. In most cases thus is done using One Time Programmable Read Only Memories (OTP-ROM), but these IP blocks are big, and require high voltage supply, making them large and thus expensive; - More complex identification and security ICs have programmable key or data storage, which requires re-programmable Non-Volatile Memory (NVM), often also referred to as flash memory. But flash memories are expensive technology features, requiring — depending upon the size of the baseline CMOS node — 10 to 12 additional mask layers in production. This can be a cost adder of typically 35 to 30% compared to non-flash baseline technology wafer cost; - Identification and security ICs have a complex Back End (BE) process in the assembly and packaging fab, since every ICs requires pre-programming with its secure SW and — in case of non-programmable ICs — the embedded keys or identifiers.
    [0006] [0006] With high volumes of IC’s there is a need for a cost effective yet secure solution for applying identification codes to the IC’s. Moreover, the identification codes should be verifiable.
    [0007] [0007] It is remarked that in general many methods of device, alternatively denoted asset authentication exist, and that in most if not all cases the solution in practice appears to be either complicated to execute, still be susceptible to some extend to some sort of spoofing and/or relatively expensive in view of typical use in end nod applications. Examples in this respect include patent publications US2016006735, US2012137137 and EP2506176A, with the first mentioned relating to a system of asserting the proper registration of chips (IC) during a mounting process of these chips in circuit boards as received in boxed lots, using a USB based, so-called JTAG scan controller instrument. The system thereto further uses a network and a central registration system applying hidden seeds and a signature algorithm before the thus finished boards are re-distributed. The system is however not generally applicable as an asset authenticating means. Amongst others this system requires active participation from the original IC fabricator. US20120137137 provides a system of storing a unique device key and safely conveying the same to a chip. In this system it is possible to renew the key and store the renewed key into the device, therewith intrinsically implying a vulnerability of such device to external mutation. The publication does not mention providing the device with a public identifier. European publication EP2506176A is associated with securely provisioning, storing and transmitting providing a cryptographic key into a flexible memory of an IC. In general the known prior art has the disadvantage that they depart from a common, i.e. identical integrated circuit with flexible memory that is individualized in a later stage. The manner of conduct not only raises costs of the system, but also introduces additional security risks into the system. The present invention at least seeks to alleviate if not eliminate at least part of the draw backs in any of these known systems.SUMMARY OF THE INVENTION
    [0008] [0008] The present invention aims to provide a centralized solution for managing and verifying identification codes of integrated circuits (IC’s). The present invention is particularly useful with, but not limited to, large number of IC’s each having a unique identification.
    [0009] [0009] The present invention enables identification and security solutions that are much cheaper at the high-volume customer or user end of the chain, and shift complex security functionality away from those end nodes.
    [0010] [0010] According to one aspect of the invention, a method is proposed for handling identification codes (also called asset identifiers) of integrated circuits, preferably in a centralized code registration system. The method can comprise storing the identification codes in a first data storage. The method can further comprise storing one or more operator keys associated with an operator code in a second data storage. Herein, storing means the action of putting data in a data storage or having data stored in a data storage available for use. The second data storage can be separate from the first data storage. The identification codes can be associated with integrated circuits. Each integrated circuit can comprise an identifier (also called a chip identifier) and the operator code. An identification code of an integrated circuit can be obtainable from a mathematical operation on the identifier using an operator key from the second data storage, wherein the operator key can be associated with the operator code. The method can comprise calculating identifiers for identification of integrated circuits using a mathematical operation on identification codes, therein using said one or more operator code associated operator keys. Also, each calculated identifier and the operator code is associated with an integrated circuit, such that each integrated circuit comprises a calculated identifier and the operator code, and an identification code of an integrated circuit may be obtainable from a mathematical operation on the identifier using the operator code associated operator key.
    [0011] [0011] With a method according to the present invention, it is made at least virtually impossible to become knowledgeable about what has been registered in the first data storage about an integrated circuit based on its identification code, thereby rendering it difficult if not impossible to link stored information to a particular integrated circuit. Additionally the method and system according to the invention, favourably renders it virtually impossible to predict valid identification codes.
    [0012] [0012] In further elaboration, the method of the invention may comprise that the operator keys associated with one or more operator codes are stored in a second data storage, wherein the second data storage is separate from the first data storage. In addition or alternatively, the method may be further elaborated upon by having said calculating of an identifier (CID) and said obtaining of an identification code (AID) from an integrated circuit associated identifier (CID) handled in a centralized code registration system (3a). With such a further measure according to the present invention, different types of data can be secured in appropriate manners. For example key material and algorithm can be kept isolated in a highly secured
    [0013] [0013] According to an aspect of the invention a centralized code registration system is proposed. The centralized code registration system can comprise a first data storage configured to store the identification codes. The centralized code registration system can further comprise a second data storage configured to store operator keys associated with an operator code. The second data storage can be separate from the first data storage. The identification codes can be associated with integrated circuits. Each integrated circuit can comprise an identifier and the operator code. An identification code of an integrated circuit can be obtainable from a mathematical operation on the identifier using an operator key from the second data storage.
    [0014] [0014] In the first data storage the identification codes of each of the integrated circuits are stored. In each of the integrated circuits an identifier is stored. In the centralized code registration system, the identifiers of the integrated circuits can be linked to the identification codes stored in the first data storage using the mathematical operation, which is depending on the operator key stored in the second data storage. The identifier may be readable to anyone, i.e. not requiring any security means to prevent the identifier from being read from the integrated circuit. Although security measures are possible, the identification codes may be stored in the first data storage without a need for securing the identification codes from being hacked, i.e. read unauthorized. The second data storage is typically a highly secured data storage to prevent the operator keys from being accessible unauthorized. Without the operator key an identifier of an integrated circuit cannot be linked to an identification code stored in the first data storage, thereby creating a secured centralized solution for managing and verifying identification codes of integrated circuits.
    [0015] [0015] A chip identifier may represent an anonymized version of an asset identifier,
    [0016] [0016] The mathematical operation is preferably performed in a secured part of the centralized code registration system to prevent the link between an identifier and an identification code being exposable to hackers. The mathematical operation may be performed in a same secured computer environment where the second data storage is a part of.
    [0017] [0017] In an embodiment the mathematical operation may be implemented as or make use of a look-up table. The chip identifier may e.g. be stored in a look-up table and/or obtained
    [0018] [0018] The operator keys are associated with an operator code. Hereto the operator code may be stored together with the operator keys in the second data storage. Alternatively, the operator code may be stored in a separate data storage and associated with the operator keys using known technologies, such as using database keys or database links. The operator code may be stored in a data storage of the centralized code registration system or in a database external to the centralized code registration system.
    [0019] [0019] The first data storage, the second data storage and/or the separate data storage are typically based on computer databases.
    [0020] [0020] The following are embodiments of the method for handling identification codes and the centralized code registration system.
    [0021] [0021] In an embodiment the centralized code registration system can be configured to obtain the operator key from the second data storage based on the operator code and perform the mathematical operation on the identifier using the operator key as a cryptographic key. The mathematical operation is e.g. an AES based decryption operation.
    [0022] [0022] This advantageously enables identification codes to be reused for different operator codes, resulting in different identifiers in the integrated circuits if the operator key is different for different operator codes. This enables e.g. different batches of integrated circuits to be assigned to different clients, different product groups or any other differentiation, while having assigned the same identification codes to the integrated circuits.
    [0023] [0023] In an embodiment the second data storage is a secure data storage. A security protocol can be used for accessing the second data storage. Preferably the security protocol comprising an encrypted data communication with the second data storage and/or the operator key being stored in the second data storage in an encrypted format requiring decryption before use in the mathematical operation. With the mathematical operation executed in, what is to be denominated a vault, and the latter equipped with computing means, at least with computing means as are implied by the use of using a data storage in general, and by the use of a database in particular, the invention in a new and favourable manner utilizes otherwise known and even standard available components, including all of hardware security module and type of calculation.
    [0024] [0024] In an embodiment the identifier and the operator code can be hard coded in a read- only memory of the integrated circuit. The identifier and the operator code can be stored in two separate read-only memories. Alternatively, the identifier and the operator code can be stored in the same read-only memory, possibly as a single binary value. It may be taken for granted that hard coded in the context of integrated circuits implies an immutable read only memory in an integrated circuit. More in particular in the present context, the hard coding preferably also includes that the coding of an integrated circuit with an identifier is performed as part of the circuit manufacturing, i.e. that a foundry or part thereof such as a mid end or back end thereof may be provisioned with identifiers, causing the chips to be produced uniquely coded. Since the system of the invention relies on exchange of information with a database system, a thus uniquely coded chip may therein be activated upon request by a customer or operator of the integrated circuit, e.g. upon taking the chip into use for identifying an asset, which may be of any, preferably electronically connectable type including so called PCB.
    [0025] [0025] In an embodiment the centralized code registration system can be configured to verify the identification code obtained from the mathematical operation against the identification codes stored in the first data storage. Thus, it may be established if the identifier of the integrated circuit is valid.
    [0026] [0026] In an embodiment a verifying device can request the identifier from the integrated circuit via an end node device. The end node device can read the identifier and the operator code from the integrated circuit and transmit the identifier and the operator code to the centralized code registration system. The centralized code registration system can obtain the identification code from the identifier by performing the mathematical operation on the identifier based on the operator code. The centralized code registration system can verify the obtained identification code against the stored identification codes to obtain and output a verification result.
    [0027] [0027] In an embodiment the verification result can be indicative for a match of the obtained identification code in the stored identification codes.
    [0028] [0028] In an embodiment the verification result can be at least partly based on contextual data, the contextual data preferably including one or more of a number of verifying requests made in a predefined time interval, a total number of verifying requests made, a time of a
    [0029] [0029] In an embodiment he verification result can be transmitted from the centralized code registration system to the verifying device and/or the end node device.
    [0030] [0030] In an embodiment the identifier can be transmitted to the centralized code registration system via the verifying device.
    [0031] [0031] In an embodiment the centralized code registration system can register the identification code as being invalid in case of a negative verification result, resulting in future verification results for this identification code to be negative by default.
    [0032] [0032] In an embodiment the integrated circuit can comprise a first read-only register comprising the identifier, a second read-only register comprising the operator code, and an interface for reading the identifier and the operator code from the first and second read-only registers and outputting the identifier and operator code. It is possible that the first read-only register and the second read-only register are the same.
    [0033] [0033] In an embodiment the functionality of the integrated circuit can be limited to providing the identifier and the operator code upon request. This allows the integrated circuit to be relatively simple, not requiring an MCU. The integrated circuit may be a part of another integrated circuit, possibly an MCU.
    [0034] [0034] In an embodiment the identification code can be activated in the first data storage upon implementation, e.g. upon validation of a lithographic writing operation of the identifier in the integrated circuit.
    [0035] [0035] In an embodiment the identification code can be unique and therefore used only once amongst a plurality of integrated circuits. In this embodiment an identification code may be reused for different operator codes, while being unique for one operator code.
    [0036] [0036] In an embodiment the centralized code registration system can be implemented as a cloud service.
    [0037] [0037] In an embodiment the first data storage and the second data storage can be implemented as separated cloud services. This measure of the present invention favorably renders privacy by design and raises the level of security in the system in that it enables the two databases to be situated also physically at different places, and at least to provide these with different security and access measures. It is also a prerequisite to arrive at yet a further measure of the invention, i.e. to accomodate the second database in a so-called vault system.
    [0038] [0038] According to an aspect of the invention a method of manufacturing an integrated circuit is proposed. The integrated circuit is for use in a method for handling identification codes as described above. The method can comprise generating an identification code in a centralized registration system. The identification code is preferably a bit-code of predefined length and associated to an operator code. The method can further comprise storing, in a first storage of the centralized code registration system, the identification code. The method can further comprise optionally storing, in a second data storage of the centralized code registration system, an operator key associated with the operator code. The second data storage can be separate from the first data storage. The method can further comprise generating an identifier using a mathematical operation on the identification code using the operator key. The method can further comprise providing the identifier and the operator code to an IC manufacturing facility. The identifier and the operator code can be hard-coded in the integrated circuit.
    [0039] [0039] The identifier and the operator code may be hard-coded in a single read-only memory. The identifier and the operator code may be hard-coded in two separate read-only memories.
    [0040] [0040] According to an aspect of the invention an integrated circuit is proposed comprising an identifier and an operator code hard-coded in the integrated circuit. The identifier is preferably a bit-code of predefined length. The integrated circuit is for use with a centralized code registration system as described above.
    [0041] [0041] In an embodiment the integrated circuit can comprise a first read-only register storing the identifier. A second read-only register can comprise the operator code. The integrated circuit can comprise an interface for reading the identifier and the operator code from the first and second read-only registers and outputting the identifier and the operator code.
    [0042] [0042] In an embodiment the integrated circuit can comprise an SPI (Serial Peripheral Interface) and control logic for obtaining the identifier from the first read-only register on a request received via the control logic. The integrated circuit can further comprise one or more voltage inputs. The integrated circuit can further comprise one or more signal inputs. The integrated circuit can further comprise a signal output for outputting the identifier.
    [0043] [0043] In an embodiment the integrated circuit can be one of: miniature SO8-packaged, SSOP8-packaged, TSSOP8-packaged or 8WLCSP-packaged for board-level applications; RF-ID compatible; integrated in a multi-chip package; integrated as IP block in a larger IC.
    [0044] [0044] According to an aspect of the invention a use of an integrated circuit as described above is proposed, for use with a centralized code registration system as described above.
    [0045] [0045] There is no security vulnerability at end node devices through the simple use of the identifier stored in the IC. Cost can be reduced since authentication means are performed centralized. No authentication measures are needed at the end node device,
    [0046] [0046] The invention is scalable over orders of magnitude, from tens to billions of nodes.
    [0047] [0047] Clients of the centralized code registration system can choose at which level they want to uniquely code their products. E.g. high turn-over goods (beer bottles or cans, food) could be coded by production batches with codes that have a time-limited validity. This is yet another scalability factor of the present invention.
    [0048] [0048] The identifiers linkable to the identification codes may be used as a connected electronic bar code. But whereas todays printed bar codes are identical for all instantiations of the same product, the identifiers in the ICs are electronic and can, if chosen so, be different at individual product level. The usage of the identifiers in the ICs may be tracked through a cloud connection, allowing for “big data” analysis and possible interaction with the end node device to take security measures.
    [0049] [0049] The centralized code registration system may be distributed among multiple servers or multiple networked computers while functioning as a centralized system.
    [0050] [0050] The system enables owners/users to set up a secure data information system on the use of their products.
    [0051] [0051] It may be evident that the present invention in fact, in an industrially new manner sets forth a method of generating and authenticating guaranteed unique identifier codes as may be used for identifying and authenticating assets comprising an integrated
    [0052] [0052] Aspects and embodiments of the invention are further described in the following description and in the claims.BRIEF DESCRIPTION OF THE DRAWINGS
    [0053] [0053] Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:
    [0054] [0054] FIG. 1 shows an exemplary data storage configuration in a centralized code registration system according to an aspect of the invention;
    [0055] [0055] FIG. 2 shows another exemplary data storage configuration in a centralized code registration system according to an aspect of the invention;
    [0056] [0056] FIG. 3 shows another exemplary data storage configuration in a centralized code registration system according to an aspect of the invention;
    [0057] [0057] FIG. 4 shows and abstract representation of an exemplary IC according to an aspect of the invention;
    [0058] [0058] FIG. 5 shows and exemplary IC according to an aspect of the invention;
    [0059] [0059] FIG. 6 shows an exemplary flow chart of a method of manufacturing an integrated circuit according to an aspect of the invention;
    [0060] [0060] FIG. 7 shows an exemplary flow chart of a method of handling identification codes of integrated circuits according to an aspect of the invention; and
    [0061] [0061] FIG. 8 shows an exemplary architecture of a system wherein the invention may be applied.
    [0062] [0062] The figures are intended for illustrative purposes only, and do not serve as restriction of the scope or the protection as laid down by the claims.
    [0064] [0064] A mathematical operation performed in the centralized code registration system 3 may generate an identifier of an IC from an identification code AID using an operator key OK, and vice versa. Identifiers are stored in the ICs and may thus be verified against identification codes AIDs stored in the first data storage 31. Herein, the mathematical operation may be a look-up table operation.
    [0065] [0065] The operator key OK may be associated with an operator code OC. This allows identification codes AIDs to be reused for different operator codes, by applying different operator keys depending on the operator code.
    [0066] [0066] The first data storage 31 need not be highly secured. In fact, the identification codes AIDs cannot be linked to an IC, i.e. to a chip identifier CID of the IC, as long as the mathematical operation and/or the operator keys OKs are secured. The second data storage 32 and the mathematical operation are preferably secured, e.g. using cryptographic data storage, secured communication protocols and/or secure execution environments.
    [0067] [0067] The centralized code registration system 3 may include an authentication service, enabling an authentication request for an IC to be received and processed. The identifier of an IC may then be received by the authentication service and verified against the stored identification codes AIDs, using the mathematical operation to obtain the identification code of the identifier.
    [0068] [0068] The centralized code registration system 3 may include a code generation service, enabling identification codes and identifiers to be generated and prepared for implementing in ICs. The latter may include the generation of GDSII files for use by an IC manufacturing foundry, where the identifier may be written into a read only memory of the IC.
    [0069] [0069] Thus, metadata related to a chip identifier CID may be separated from the chip identifier CID. An operator may see a chip identifier CID, without knowing to which asset record, i.e. asset identifier AID this chip identifier CID belongs. The two can preferably only
    [0070] [0070] A centralized code registration system 3a may store identification codes AIDs for different operator codes OCs. An example hereof is shown in FIG. 2, where data storage 31a, data storage 31b and data storage 3 1c are each similar to first data storage 31 and each store identification codes AIDs for different operator codes OCs. In the example of FIG. 2 the operator codes OCs are stored associated with the operator keys OKs in the second data storage 32a.
    [0071] [0071] The operator codes OCs may be stored in a separate database 33, such as shown in FIG. 3. The operator codes OCs in the separate database 33 and the operator keys OKs stored in second data storage 32b may be associated using known database structures, e.g. using database links or any other data structure. The separate database 33 may be part of or external to a centralized code registration system 3b.
    [0072] [0072] FIG. 4 is an abstract representation of an IC, wherein an operator code OC and an identifier CID have been stored in a memory, typically a read-only memory. The identifier CID is preferably unique amongst all ICs for a same operator code OC, but it is possible to
    [0074] [0074] It will be understood that the IC 4 is not limited to having SPI-based interfaces. Other non-limiting examples of interfaces that may be used in the IC 4 are serial interface like I2C or 128, 3-wire, 1-wire, USB or a classical 13,56MHz RF-ID contactless interface.
    [0075] [0075] In FIG. 6 a flow chart is shown of an exemplary method performed in a centralized code registration server 3, 3a, 3b for generating identification codes AIDs and implementing the corresponding identifiers CIDs in the ICs. The steps in the left column of FIG. 6 may be performed in a less secure part of the centralized code registration system 3. The steps in the right column of FIG. 6 are preferably performed in a secured part of the centralized code registration system 3.
    [0076] [0076] In step 100 one or more identification codes AIDs are generated which, using the computing means associated with controlling a storage 31a-31c¢ is performed in a deterministic manner, i.e. guaranteeing the uniqueness of an AID as generated. This step 100 typically is the first time that the identification codes AIDs are generated for a specific operator code OC. Hence the system of the invention guarantees that AID values are at least unique within a set to be associated with an operator code OC. In step 101 the identification codes AIDs are stored in the first data storage 31. The identification codes AIDs may be used
    [0077] [0077] For the generated identification code AID an identifier to be stored in the IC is to be generated. Hereto the identifier is requested and in step 104 the operator key OK for the operator code OC is obtained from a data storage, which as indicated here and according to preference is the indicated second data storage 32. One or more operator keys OKs for the operator code OC may have been generated and stored in step 102. The operator keys OKs may be used later when verifying the authenticity of ICs based on the identifier of the IC, which is depicted by the roman II (see also FIG. 7).
    [0078] [0078] In step 107 a mathematical operation e may be performed on the identification code AID to obtain the identifier CID. This is depicted as (AID)=ID. The mathematical operation may use the operator key OK, for example as a cryptographic encryption key in an AES- based cryptographic mathematical operation.
    [0079] [0079] The thus obtained identifier CID and the operator code OC may be provided to an IC manufacturing foundry. Hereto the CIDs for the AIDs may be received. This receipt may be at another place than the place of request, e.g. a secure box at a lithographic machine writing a chip. There may be an interruption in the linking process by request to and operation of a second database in the right-hand side column.
    [0080] [0080] For example, a GDSII file may be generated based on the identifier CID and the operator code OC, which GDSII file may be provided to the foundry in step 108. In step 106 the GDSII file, or any other data file enabling the foundry to create the IC, may be used to write the identifier CID and the operator code OC to a memory portion of a wafer forming a part of an IC 4.
    [0081] [0081] The identifier CID and operator code IC stored in the IC 4 may be used later when verifying the authenticity of ICs, which is depicted by the roman III (see also FIG. 7).
    [0082] [0082] In an embodiment, to generate a per-chip unique - e.g. 128-bit - identifier CID an intermediate encoding may be used. First, every operator that intends to encode ICs may receive a unique and secret operator key OK, e.g. a 128-bits or any other bit length key. The operator key OK is preferably kept in a secure location such as the second data storage 32, for example in a central software vault processing center (e.g. HSM) of the centralized code registration system 3. All computations that require encoding or decoding with this operator key OK preferably only take place within this central vault. If now a series of n ICs require
    [0083] [0083] Although stealing (essentially copying) of such a series of CIDs doesn’t give any advantage to a hacker, it would be annoying and therefore the transmission of the » identifiers CIDs from the vault to the factory may be secured using e.g. standard AES encryption techniques.
    [0084] [0084] Instead of every IC being coded individually, an operator may e.g. decide to code groups of ICs with the same CID per batch, per production day, per production location, etcetera. Of course, this reduces the identification level to such a group, but for fast turnover products (fresh food, beer bottles) this might be more than enough.
    [0085] [0085] Once produced the ICs carrying their - possibly unique - identifier CID may be physically attached to a device they are expected to identify. This can be a tag, a bank note, another IC in a multi-chip package, a PCB board, module or complete device or machine, all to be decided by the operator. At any moment the identifier CID of such a device can be read, using the interface provided by the IC.
    [0086] [0086] In FIG. 7 a flow chart is shown of an exemplary method performed in a centralized code registration server 3, 3a, 3b for handling identification codes AIDs of ICs 4. The steps in the left column of FIG. 7 may be performed in a less secure part of the centralized code registration system 3. The steps in the right column of FIG. 7 are preferably performed in a secured part of the centralized code registration system 3.
    [0087] [0087] An identifier CID and operator code OC may be received from an IC in the centralized code registration server 3, e.g. via the authentication service shown in FIG. 1. The identifier CID may be verified by checking the identifier CID against the stored identification codes AIDs in the first data storage 31. Hereto a request of the validity of the identifier CID for the received operator code OC may be transmitted to a secured part of the centralized code registration system 3.
    [0088] [0088] In step 104 the operator key OK associated with the operator code OC may be retrieved from the second data storage 32. In step 103 a mathematical operation €! may be performed on the identifier CID to obtain the identification code AID. This is depicted as AID=e'!(CID). The mathematical operation may use the operator key OK, for example as a cryptographic decryption key in an AES-based cryptographic mathematical operation.
    [0089] [0089] In step 105 the thus obtained identification code AID may be verified against the stored identification codes AIDs to determine its authenticity. Indirect, the authenticity of the identifier CID may thus be verified. The result of the verification may be output as a verification result IV.
    [0090] [0090] FIG. 8 shows an exemplary authentication system 1 wherein the centralized code registration system 3 may be used. The authentication system 1 may include one or more end node devices 2 each containing an IC 4 embedded with an identifier CID and an operator code OC. The authentication system 1 may further include a verifying device 5 for requesting the identifier CID and the operator code OC from the end node device 2 and ultimately from the IC 4. The authentication system 1 includes the centralized code registration system 3, such as shown in FIG. 1.
    [0091] [0091] The IC 4 is typically linked to an asset. The asset is e.g. an electronic device like a peripheral device, an industrial device or a medical device, or any taggable good like packing material or consumer goods. The assets have in common that they are identifiable by a combination of the identifier CID and the operator code OC. It is possible that the end node device itself is the asset.
    [0092] [0092] Querying of an IC 4 for its identifier may result in sending the identifier CID and the operator code OC to the centralized code registration system 3, and the centralized code registration system 3 providing a verification result indicative of an authentication result. The identifier CID and the operator code OC are typically transmitted to the centralized code registration system 3 after a request from the verifying device 5. The identifier CID and the operator code OC may be transmitted from an end node device 2 to the centralized code registration system 3 via the verifying device 5 and/or via any other intermediate communication device (not shown). The centralized code registration system 3 may then verify the identifier CID against stored identification codes AIDs to obtain a verification result. The verification result may be communicated to the verifying device 5, the end node device 2 or any other computer system.
    [0093] [0093] In case an identifier CID and an operator code OC are used in a non-authorized combination, the centralized registration system 3 may return a negative verification result indicative of a failed authentication. Alternatively or additionally, in case of a negative verification result the centralized registration system 3 may block the identification code from any future use, resulting in future verification results for this identification code to be negative by default.
    [0094] [0094] An identifier CID may be generated before or during the production process of ICs
    [0095] [0095] The ICs 4 are preferably manufactured in a cost-efficient manner, typically involving a lithography back-end processes followed by a so-called mid-end lithographic process step. In the back-end process the dies on a wafer 5 may be prepared to a common design, e.g. in a CMOS based, front end lithographic operation typically applying masked lithographic equipment. The front-end operation may be used to write the operator code OC to the wafer, as the same operator code OC is typically used multiple times. In the subsequent mid-end process step, a wafer based maskless lithographic operation may manipulate a predefined CMOS based IC for encoding each die of a wafer with the identifier CID — possibly a unique identifier - generated by the code generation service. The operator code OC may be written in the mid-end processing step instead of the front-end processing.
    [0096] [0096] The implementation of the identifier CID in the mid-end lithographic process step advantageously allows commonly known and cost-effective front-end processes to remain unmodified. The mid-end lithographic process step may be integrated as a maskless lithography operation, which is found to be very suitable for uniquely encoding IC based electronic devices. In such a set-up maximum advantage may be taken from cost reduction as has over the past decades been effected in so called front-end chap manufacturing fab's or so- called foundries.
    [0097] [0097] Advantageously, in the authentication system 1 according to the present invention, most or all security may be transferred to the centralized code registration system 3, which is preferably implemented in the cloud. Every application system, e.g. retail, may have its own
    [0098] [0098] The centralized code registration system 3 may take the context of verification requests into account in processing the current verification request. Examples hereof are a number of requests made in a predefined time interval, the total number of requests made, time of the request, location of the request, and etcetera. Contextual information may be transmitted as contextual data from the verifying device 5 to the centralized code registration system 3 and/or generated in the centralized code registration system 3. Part or all of the contextual data may be generated in the end node device 2, 2a-2d.
    [0099] [0099] Hackers may want to try to replicate or falsify end node devices 2 or ICs 4. Duplication of an end node 2 with IC 4 in an authentication system 1 no longer makes any sense, because this may immediately be detected, and the identification code AID and thereby the IC 4 be blocked for use. Although identifiers CIDs can in principle be public - there is nothing to hide - they may be encrypted during communication with the centralized code registration system 3. In other words, hacking an end node 2 or IC 4 does not make any sense, all security processing takes place in the centralized code registration system 3. The IC 4 thus acts as a hardware anchor (e.g. to attach the code to a physical device) in an otherwise centralized secure system 3. So, although the end nodes 2 and ICs 4 could be hacked (e.g.
    copied), the system 1 remains secure.
    |
    -20- Clauses
    1. A method for handling identification codes (AIDs) of integrated circuits (4), the method comprising: storing (101) the identification codes (AIDs) in one or more first data storages (31a- 310); storing (102) one or more operator keys (OKs) associated with an operator code (OC) in one of a first and a second data storage (31, 32), calculating identifiers (CIDs) for identification of integrated circuits (4) using a mathematical operation on identification codes (AIDs), therein using said one or more operator code (OC) associated operator keys (OKs), wherein each calculated identifier (CID) and the operator code (OC) is associated with an integrated circuit (4), such that each integrated circuit (4) comprises a calculated identifier (CID) and the operator code (OC), wherein an identification code (AID) of an integrated circuit (4) is obtainable from a mathematical operation (103) on the identifier (CID) using the operator code (OC) associated operator key (OK).
    2. The method according to clause 1, wherein the operator keys associated with one or more operator codes are stored in a second data storage (32), wherein the second data storage (32) is separate from the first data storage (31).
    3. The method according to clause 1 or clause 2, wherein said calculating of an identifier (CID) and said obtaining of an identification code (AID) from an integrated circuit associated identifier (CID) are handled in a centralized code registration system (3a).
    4. The method according to clause 2 or 3, wherein the code registration system (3) is configured to obtain (104) the operator key (OK) from the second data storage (32) based on the operator code (OC) and perform the mathematical operation (103) on the identifier (CID) using the operator key (OK) as a cryptographic key.
    -21-
    5. The method according to any of preceding clauses 2 to clause 4, wherein the second data storage (32) is a secure data storage, and wherein the method further comprises using a security protocol for accessing the second data storage, preferably the security protocol comprising an encrypted data communication with the second data storage (32) and/or the operator key (OK) being stored in the second data storage (32) in an encrypted format requiring decryption before use in the mathematical operation (103).
    6. The method according to any one of the preceding clauses, wherein the identifier (CID) and the operator code (OC) are preferably immutably hard coded in a read-only memory (41, 42) of the integrated circuit (4).
    7. The method according to any one of the preceding clauses, wherein the centralized code registration system (3) is configured to verify (105) the identification code (AID) obtained from the mathematical operation (103) against the identification codes (AIDs) stored in the first data storage (31).
    8. The method according to any one of the preceding clauses, further comprising: requesting, by a verifying device (5), the identifier (CID) from the integrated circuit (4) via an end node device (2); reading, by the end node device (2), the identifier (CID) and the operator code (OC) from the integrated circuit (4) and transmitting the identifier (CID) and the operator code (OC) to the centralized code registration system (3); obtaining, by the centralized code registration system (3), the identification code (AID) from the identifier (CID) by performing the mathematical operation (103) on the identifier (CID) based on the operator code (OC); and verifying (105), in the centralized code registration system (3), the obtained identification code (AID) against the stored identification codes (AIDs) to obtain and output a verification result (IV).
    9. The method according to the preceding clause, wherein the verification result (IV) is indicative for a match of the obtained identification code (AID) in the stored identification codes (AIDs).
    -22-
    10. The method according to any one of the clauses 8-9, wherein the verification result (IV) is at least partly based on contextual data, the contextual data preferably including one or more of a number of verifying requests made in a predefined time interval, a total number of verifying requests made, a time of a verifying request, a geographical location of the integrated circuit, a geographical location from where a verifying request is made.
    11. The method according to any one of the clauses 8-10, further comprising transmitting the verification result (IV) from the centralized code registration system (3) to the verifying device (5) and/or the end node device (2).
    12. The method according to any one of the clauses 8-11, comprising transmitting the identifier (CID) to the centralized code registration system (3) via the verifying device (5).
    13. The method according to any one of the clauses 8-12, further comprising registering, in the centralized code registration system (3), the identification code as being invalid in case of a negative verification result, resulting in future verification results for this identification code to be negative by default.
    14. The method according to any one of the preceding clauses, wherein the integrated circuit (4) comprises a first read-only register (41) comprising the identifier (CID), a second read-only register (42) comprising the operator code (OC), and an interface (MISO, RFID) for reading the identifier (CID) and the operator code (OC) from the first (41) and second (42) read-only registers and outputting the identifier (CID) and operator code (OC).
    15. The method according to any one of the preceding clauses, wherein the functionality of the integrated circuit (4) is limited to providing the identifier (CID) and the operator code (OC) upon request.
    16. The method according to any one of the preceding clauses, wherein the identification code (AID) has been activated in the first data storage (31) upon implementation, e.g. upon
    -23- validation of a lithographic writing operation of the identifier (CID) in the integrated circuit (4).
    17. The method according to any one of the preceding clauses, wherein the identification code (AID) is provided unique, e.g. by using an enumeration algorithm, and therefore used only once amongst a plurality of integrated circuits (4).
    18. The method according to any one of the preceding clauses, wherein the first data storage (31) and the second data storage (32) are implemented as separated cloud services.
    19. A method of manufacturing an integrated circuit (4), the integrated circuit (4) for use in a method according to any one of the clauses 1-18, the method comprising: generating (100) an identification code (AID) for an operator code (OC) in wherein the identification code (AID) is a bit-code of predefined length; storing (101), in a first storage (31) of the code registration system (3), the identification code (AID); storing (102), in a data storage (32) of the code registration system (3), an operator key (OK) associated with the operator code (OC); generating a chip identifier (CID) using a mathematical operation (107) on the identification code (AID) using the operator key (OK); and providing the identifier (CID) and the operator code (OC) to an IC manufacturing facility, where the identifier (CID) and the operator code (OC) are hard-coded in the integrated circuit (4).
    20. A method of manufacturing according to clause 19, in which the storage (32) of the code registration system (3) and the associated operator key (OK) is a second storage (32), separate from the first storage (31).
    21. A method of manufacturing according to clause 19 or 20, in which the registration system is a centralized registration system (3).
    -24-
    22. A centralized code registration system (3), comprising: a first data storage (31) configured to store the identification codes (AIDs); and a second data storage (32) configured to store operator keys (OKs) associated with an operator code (OK), wherein the second data storage (32) is separate from the first data storage (31), wherein the identification codes (AIDs) are associated with integrated circuits (4), wherein each integrated circuit (4) comprises an identifier (CID) and the operator code (OC), and wherein an identification code (AID) of an integrated circuit (4) is obtainable from a mathematical operation (103) on the identifier (CID) using an operator key (OK) from the second data storage (32).
    23. The centralized code registration system according to clause 19, arranged to perform the method according to any one of the clauses 1-17.
    24. An integrated circuit (4) comprising an identifier (CID) and an operator code (OC) hard-coded in the integrated circuit (4), wherein the identifier (CID) is a bit-code of predefined length, the integrated circuit (4) for use with the centralized code registration system (3) according to any one of the clauses 19-20.
    25. The integrated circuit (4) according to clause 24, wherein the integrated circuit (4) comprises a first read-only register (41) comprising the identifier (CID), a second read-only register (42) comprising the operator code (OC), and an interface (MISO, RFID) for reading the identifier (CID) and the operator code (OC) from the first (41) and second (42) read-only registers and outputting the identifier (CID) and the operator code (OC).
    26. The integrated circuit (4) according to any one of the clauses 24-25, comprising: an SPI (Serial Peripheral Interface) and control logic for obtaining the identifier (CID) from the first read-only register (41) on a request received via the control logic; one or more voltage inputs (VDDD, VSSD, VDDIO, VSSIO); one or more signal inputs (MOSI, SCLK, CSN); and a signal output (MISO, RFID) for outputting the identifier (CID).
    -25-
    27. The integrated circuit (4) according to any one of the clauses 24-26, wherein the integrated circuit (4) is one of: miniature SO8-packaged, SSOP8-packaged, TSSOP8-packaged or SWLCSP- packaged for board-level applications; RF-ID compatible; integrated in a multi-chip package; integrated as IP block in a larger IC.
    28. Use of an integrated circuit (4) according to any one of the clauses 24-27 with the centralized code registration system (3) according to any one of the clauses 19-20.
    29. A method of generating and authenticating guaranteed unique identifier codes (CID) as may be used for identifying and authenticating assets comprising an integrated circuit, the method comprising generating guaranteed unique identifiers (AID) in a centralized code registration system (3); storing the generated identifiers (AID) within a data storage (31a-31c); associating each identifier (AID) with an unique identification (CID) to be used for identifying an integrated circuit, by applying a bijective algorithm; authenticating an identification code (CID) by inversely calculating an identificatier (AID) from an identification code (CID)based on said algorithm.
    30. A system comprising a centralized system provided with a computer based algorithm for executing the method according to clause 29.
    权利要求:
    Claims (1)
    [1]
    -26-
    CONCLUSIONS
    A method for handling identification codes (AIDs) of integrated circuits (4), the method comprising: storing (101) the identification codes (AIDs) in a first data store (31); storing (102) one or more operator keys (OKs) associated with an operator code (OC) associated in one of a first and a second data store (31, 32), calculating identifiers (CIDs) for identification of integrated circuits (4) using a mathematical operation of identification codes (AIDs), using said one or more operator codes (OC) associated with the operator keys (OKs), each computed identifier (CID) and the operator code (OC ) is associated with an integrated circuit (4) such that each integrated circuit (4) includes a computed identifier (CID) and the operator code (OC), wherein an identification code (AID) of an integrated circuit (4) is obtainable from a mathematical operation (103) on the identifier (CID) using an operator key (OK) associated with an operator code (OC).
    The method of claim 1, wherein the operator keys associated with one or more operator codes are stored in a second data store (32), the second data store (32) being separate from the first data store (31).
    A method according to claim 1 or claim 2, wherein said calculating an identifier (CID) and said obtaining an identification code (AID) of an identifier associated with an integrated circuit are handled in a centralized code registration system (3).
    A method according to claim 2 or 3, wherein the centralized code recording system (3) is configured to obtain the operator key (OK) from the second data store (32) based on the operator code (OC) (104) and to perform the mathematical operation
    -27- (103) on the identifier (CID) using the operator key (OK) as a cryptographic key.
    The method of any one of claims 2 to 4, wherein the second data store (32) is a secure data store, and wherein the method further comprises using a security protocol to access the second data store, the security protocol preferably being an encrypted data communication with the second data store (32) and/or the operator key (OK) in the second data store (32) is stored in an encrypted format requiring decryption prior to use in the math operation (103).
    A method according to any one of the preceding claims, wherein the identifier (CID) and the operator code (OC) are hard-coded in a read-only memory (41, 42) of the integrated circuit (4).
    A method according to any one of the preceding claims, wherein the centralized code recording system (3) is configured to verify (105) the identification code (AID) obtained from the mathematical operation (103) against the identification codes ( 1 ) stored in the first data store (31). AIDS).
    A method according to any preceding claim, further comprising: requesting, by a verification device (5), the identifier (CID) from the integrated circuit (4) via an end node device (2); the terminal node device (2) reading the identifier (CID) and the operator code (OC) from the integrated circuit (4) and transmitting the identifier (CID) and the operator code (OC) to the centralized code recording system (3 ); obtaining, by the centralized code registration system (3), the identification code (AID) of the identifier (CID) by performing the mathematical operation (103) on the identifier (CID) based on the operator code (OC); and
    -28- verifying (105), in the centralized code registration system (3), the obtained identification code (AID) against the stored identification codes (AIDs) to obtain and output a verification result (IV).
    A method according to the preceding claim, wherein the verification result (IV) is indicative of a match of the obtained identification code (AID) in the stored identification codes (AIDs).
    A method according to any one of claims 6-7, wherein the verification result (IV) is based at least in part on contextual data, wherein the contextual data preferably comprises one or more of a number of verification requests made in a predefined time interval, a total number of verification requests made, a time of a verification request, a geographic location of the integrated circuit, a geographic location from which a verification request was made.
    A method according to any one of claims 8-10, further comprising transmitting the verification result (IV) from the centralized code recording system (3) to the verification device (5) and/or the end node device (2).
    A method according to any one of claims 8-11, comprising sending the identifier (CID) to the centralized code recording system (3) via the verification device (5).
    A method according to any one of claims 8 to 12, further comprising registering, in the centralized code registration system (3), the identification code as invalid in case of a negative verification result, resulting in future verification results for this identification code being negative by default. are.
    A method according to any one of the preceding claims, wherein the integrated circuit (4) comprises a first read-only register (41) comprising the identifier (CID), a second read-only register (42) comprising the operator code (OC) and an interface
    29. (MISO, RFID) to read the identifier (CID) and operator code (OC) from the first (41) and second (42) read-only registers and output the identifier (CID) and operator code ( OC), includes.
    A method according to any one of the preceding claims, wherein the functionality of the integrated circuit (4) is limited to providing the identifier (CID) and the operator code (OC) on request.
    A method according to any one of the preceding claims, wherein the identification code (AID) is activated in the first data store (31) during implementation, e.g. upon validation of a lithographic write operation of the identifier (CID) in the integrated circuit (4).
    A method according to any one of the preceding claims, wherein the identification code (AID) is unique and therefore used only once within a plurality of integrated circuits (4).
    A method according to any one of the preceding claims, wherein the centralized code registration system (3) is implemented as a cloud service.
    A method according to any one of the preceding claims, wherein the first data store (31) and the second data store (32) are implemented as separate cloud services.
    A method of manufacturing an integrated circuit (4), wherein the integrated circuit (4) is used in a method according to any one of claims 1-18, the method comprising: generating (100) an identification code (AID) for an operator code (OC), wherein the identification code (AID) is a bit code of predefined length; storing (101) the identification code (AID) in a first storage (31) of the code registration system (3);
    -30- storing (102) in a data store (32) of the code recording system (3), an operator key (OK) associated with the operator code (OC); generating a chip identifier (CID) using a mathematical operation (107) on the identification code (AID) using the operator key (OK); and making the identifier (CID) and the operator code (OC) available to an IC manufacturing facility, where the identifier (CID) and the operator code (OC) are hard-coded in the integrated circuit (4).
    A manufacturing method according to claim 19, wherein the storage of the code recording system (3) and the associated operator key (OK) is a second data store (32), separate from the first data store (31).
    A manufacturing method according to claim 19 or 20, wherein the registration system is a centralized registration system (3).
    A centralized code recording system (3), comprising: a first data store (31) configured to store the identification codes (AIDs); and a second data store (32) configured to store operator keys (OKs) associated with an operator code (OK), the second data store (32) being separate from the first data store (31), the identification codes (AIDs) associated are with integrated circuits (4) wherein each integrated circuit (4) comprises an identifier (CID) and the operator code (OC) and wherein an identification code (AID) of an integrated circuit (4) is obtained from a mathematical operation (103) on the identifier (CID) using an operator key (OK) from the second data store (32).
    A centralized code registration system according to claim 22, arranged for performing the method according to any one of claims 1-19.
    -31-
    An integrated circuit (4) comprising an identifier (CID) and operator code (OC) hard-coded in the integrated circuit (4), the identifier (CID) being a bit code of predefined length, the integrated circuit (4) using with the centralized code registration system (3) according to any one of claims 22-23.
    An integrated circuit (4) according to claim 24, wherein the integrated circuit (4) comprises a first read-only register (41) containing the identifier (CID), a second read-only register (42) containing the operator code (OC ) and an interface (MISO, RFID) for reading the identifier (CID) and the operator code (OC) from the first (41) and second (42) read-only registers and outputting the identifier (CID) and includes the operator code (OC).
    An integrated circuit (4) according to any one of claims 24-25, comprising: an SPI (Serial Peripheral Interface) and control logic for obtaining the identifier (CID) from the first read-only register (41) on a via the control logic request received; one or more voltage inputs (VDDD, VSSD, VDDIO, VSSIO); one or more signal inputs (MOSI, SCLK, CSN); and a signal output (MISO, RFID) for outputting the identifier (CID).
    An integrated circuit (4) according to any one of claims 21 to 23, wherein the integrated circuit (4) is one of: miniature SO8 packaged, SSOP8 packaged, TSSOP8 packaged or 8WLCSP packaged for board-level applications; RF-ID compatible; integrated in a multichip package; integrated as an IP block in a larger IC.
    Use of an integrated circuit (4) according to any one of claims 24-27, with the centralized code recording system (3) according to any one of claims 19-20.
    -32-
    A method of generating and authenticating guaranteed unique identifiers (CID) such as may be used to identify and authenticate assets comprising an integrated circuit, the method comprising generating guaranteed unique identifiers (AID) in a centralized code record system (3); storing the generated identification codes (AID) in a data store (31a-31c); associating each identification code (AID) with a unique identifier (CID) for use in identifying an integrated circuit, by applying a bijective algorithm; authenticating an identifier (CID) by inversely calculating an identification code (AID) from an identifier (CID) based on said algorithm.
    A system comprising a centralized system provided with a computer based algorithm for performing the method of claim 29.
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    同族专利:
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US202063030944P| true| 2020-05-28|2020-05-28|
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