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    • 专利摘要:
    An output buffer control apparatus of a source driver for driving a liquid crystal display device is disclosed. In the output buffer control device of the source driver for driving the liquid crystal display according to the present invention, first, the share switching control in which the counter part is inverted by a predetermined number of cycles of the main clock (SCLK) 5 in response to a predetermined input signal. A signal 3 and an output switching control signal are generated. Accordingly, the share switching control unit receives the share switching control signal 3 and converts the shared switching control signal 3 into a signal having an increased current driving capability so as to drive switching of the share voltage output pass gate connected to the source line of the liquid crystal panel. The image switching controller has a current driving capability to drive switching of an image signal output pass gate connected to a source line of the liquid crystal panel in response to an output switching control signal (inverter input terminal signal for outputting four signals) and a predetermined input signal. This increased signal is generated and output. Therefore, there is an effect that can improve the block defect phenomenon of the LCD panel due to the variation of the output time between the source driver caused by the nonuniformity of the device characteristics that can appear in the semiconductor manufacturing process of the LCD source driver.
    公开号:KR20040050531A
    申请号:KR1020020078384
    申请日:2002-12-10
    公开日:2004-06-16
    发明作者:김도윤；성시왕；최창휘；이승정
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    Output buffer control device for driving a liquid crystal display device
    [11] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to an output buffer control device of an LCD source driver.
    [12] In general, LCDs are driven by a gate driver for supplying a scan signal to a gate line and a source driver for supplying an image signal to a data line, thereby switching thin film transistors (TFTs) of respective pixels constituting the lower plate of the liquid crystal panel and thereby. The video signal supply is repeated periodically.
    [13] 1 is a view for explaining driving of a general liquid crystal display.
    [14] Referring to FIG. 1, a liquid crystal display typically includes three liquid crystals composed of red green blue (RGB) as one pixel, and its luminance is changed according to a voltage applied to each liquid crystal. It depends on the resolution of the display device. For example, in the case of an XGA-class liquid crystal display device, the number of liquid crystals is "1024 * 3 (width) x 768 (length)", and the number alone is 2,360K. Therefore, 3,072 lines of source output (DL) are required to drive the liquid crystal, and 768 gate lines (GL) are required. Therefore, when n and m are numbers determined according to the resolution of the liquid crystal display device, the source driver unit 110 constituting the liquid crystal display device uses the m source drivers having n outputs to form the liquid crystal panel 130. ) Will be driven.
    [15] 2 is a circuit diagram illustrating an output buffer of a source driver of a general liquid crystal display device.
    [16] Referring to FIG. 2, the output buffer of the source driver generally includes an operational amplifier 220 that receives the video signal output from the digital to analog converter (DAC) 210 to perform current amplification or the like, and stabilize the video signal. In this case, the video signal is outputted to the data line CL of the liquid crystal panel through a switching element composed of pass gates 230 and 240. At this time, the output of each source driver drives each data line connected vertically. The load indicated by CL is a total load connected to the driven data line. In order to drive a liquid crystal constituting an LCD having an arbitrary resolution, The current driving capability must be very large so that each amplifier 220 can sufficiently charge the load connected to the data line. That is, if the current I necessary to charge the load sufficiently in a certain time (t) and raise it to a constant voltage (V) is expressed by the equation,
    [17]
    [18] Becomes Here, the size of CL varies according to the resolution of the liquid crystal display and the applied panel, and thus the current consumed also varies. As such, the source driver typically uses a charge sharing method in order to minimize the current consumed in driving the liquid crystal display and reduce the burden on the output buffer of the source driver. Unlike when the source driver output buffer drives the data line immediately without passing through charge sharing when the pass gate driving signal of the source driver output buffer is generated, the charge sharing method uses a share voltage at the end of the output buffer. Aside from the output pass gate 230 and the image signal output pass gate 240, the share voltage output pass gate 230 is turned on by the share voltage output pass gate 230 driving signals SWS and SWSB. When the image signal output pass gate 240 is turned on by the video signal output pass gate 240 driving signals SWO and SWOB, the predetermined share voltage is supplied to all data lines. The video signal from the amplifier 220 is supplied to the data line to drive the liquid crystal of each panel. For example, in order to display color, a part of the voltage to be applied to the liquid crystal is precharged through the pass voltage 230 for the share voltage output, and the remaining part of the voltage is used to pass the pass gate 240 for the image signal output. Supplied through. Such a method is mostly employed in a large panel driving source driver to reduce the current supply capability burden of the amplifier 220. In this case, the share voltage output pass gate 230 driving signal and the image signal output pass gate 240 driving signal are generated inside the source driver.
    [19] 3 is a circuit diagram illustrating a block for generating a pass gate 230 and 240 control signal of a conventional source driver output buffer, and FIG. 4 is a diagram illustrating control of pass gates 230 and 240 of a source driver output buffer shown in FIG. Is a timing diagram.
    [20] 3 and 4, in the conventional source driver for receiving the output enable signal OEN and the share enable signal SEN from a printed circuit board (PCB) module controlling the source driver, an image signal is output. The pass gate 240 driving signal SWO is disabled at the rising of the output enable signal OEN, and the pass gate for the share voltage output during the T1 period from the falling edge of the output enable signal OEN. The driving signal SWS is enabled to cause precharging. In addition, after the T2 time, the driving signal for the pass gate 240 for outputting the image signal is enabled to output the image signal of the amplifier 220 to charge the pixels connected to each channel with a constant image voltage. You will have an output (OS) waveform. At this time, from the falling edge of the output enable signal OEN, a current I is supplied to a capacitor C having a constant magnitude in order to make T1, which is a period in which the share voltage is output, and T2, which is a margin period in consideration of the deviation thereof. The voltages V1 and V2 must be generated, which triggers on the final outputs (SWS, SWO) when they are larger or smaller than the reference voltage indicated by Vref.
    [21] That is, the voltages V1 and V2 and the times T1 and T2 are
    [22]
    [23]
    [24] It can be expressed as, and it can be seen that the current is a variable to adjust the width of T1 and T2. In this way, the correlation between the share voltage output period T1 of the source driver output buffer and the margin period T2 becomes as shown in the graph shown in FIG.
    [25] As described above, as can be seen in the formulas of voltages V1 and V2 and times T1 and T2, the device characteristic nonuniformity caused by various problems in the manufacturing process of the source driver is: current (I), capacitor (C), reference voltage. (Vref) and the like are made variable so that they appear as defects in luminance characteristics of the liquid crystal panel.
    [26] That is, FIG. 6 is a waveform diagram illustrating output voltages measured by the liquid crystal display device in which the source driver shown in FIG. 3 is mounted. FIG. 7 is a view for describing a defect phenomenon of the liquid crystal display device in which the source driver shown in FIG. 3 is mounted. Drawing.
    [27] 6 and 7, the output between the source drivers by the conventional source drivers does not output the share voltage at the same time, and therefore the output time of the video signal is not constant. That is, as shown in Fig. 6, when the output buffer control device of the source driver shown in Fig. 3 is mounted, an output time deviation of 300 nsec or more occurs between output times between the source drivers.
    [28] As such, a deviation occurs between output times between the source drivers, thereby preventing the source driver from sufficiently charging the image signal in the data line, thereby causing a block defect in which luminance varies for each predetermined block on the liquid crystal panel. cause a phenomenon.
    [29] Accordingly, an aspect of the present invention is to provide an output buffer control apparatus of a source driver capable of improving the block defect phenomenon of an LCD panel.
    [1] BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
    [2] 1 is a view for explaining driving of a general liquid crystal display.
    [3] 2 is a circuit diagram illustrating an output buffer of a source driver of a general liquid crystal display device.
    [4] 3 is a circuit diagram illustrating a block for generating a pass gate control signal of a conventional source driver output buffer.
    [5] FIG. 4 is a timing diagram illustrating pass gate control of the source driver output buffer illustrated in FIG. 3.
    [6] FIG. 5 is a graph illustrating a correlation between the share voltage output period and the video signal interruption period of the source driver output buffer shown in FIG. 3.
    [7] FIG. 6 is an output voltage waveform diagram measured by the liquid crystal display device in which the source driver illustrated in FIG. 3 is mounted.
    [8] FIG. 7 is a diagram for describing a defect phenomenon of the liquid crystal display device in which the source driver illustrated in FIG. 3 is mounted.
    [9] 8 is a circuit diagram of an output buffer control apparatus of a source driver for driving a liquid crystal display according to the present invention.
    [10] 9A and 9B are timing diagrams for describing switching control of the output buffer control apparatus of the source driver shown in FIG. 8.
    [30] The output buffer control device of the source driver for driving the liquid crystal display according to the present invention for achieving the above technical problem, share switching control in which the logic state is inverted by a predetermined number of main clock periods corresponding to the first predetermined input signal. A counter unit for generating a signal and an output switching control signal; A share switching control unit receiving the share switching control signal and converting the shared switching control signal into a signal having an increased current driving capability so as to drive switching of the pass voltage output pass gate connected to the source line of the liquid crystal panel; And an image for generating and outputting a signal having an increased current driving capability to drive switching of an image signal output pass gate connected to a source line of a liquid crystal panel in response to the output switching control signal and a predetermined second input signal. And a switching controller.
    [31] The predetermined first input signal is a share enable signal for controlling generation of the share switching control signal and an output enable signal for controlling generation of the output switching control signal, and in particular, the share in The enable signal is in a first logic state, and the counter unit activates the share switching control signal and the output switching control signal when the output enable signal is activated to the second logic state.
    [32] The predetermined second input signal may be an output enable signal for controlling generation of the output switching control signal. In particular, the output switching control signal and the predetermined second input signal may have the same logic state. It is characterized by.
    [33] In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.
    [34] Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. Like reference numerals in the drawings denote like elements.
    [35] 8 is a circuit diagram of an output buffer control apparatus of a source driver for driving a liquid crystal display according to the present invention.
    [36] Referring to FIG. 8, an output buffer control apparatus of a source driver for driving a liquid crystal display according to the present invention includes a counter unit 100, a share switching control unit 200, and an image switching control unit 300.
    [37] The counter 100 generates a share switching control signal and an output switching control signal in which logic states are inverted by a predetermined number of main clock SCLK (or system clock) cycles in response to the predetermined first input signal.
    [38] The share switching control unit 200 receives the share switching control signal and converts the shared switching control signal into a signal having an increased current driving capability so as to drive switching of the share voltage output pass gate connected to the source line of the liquid crystal panel.
    [39] The image switching controller 300 is a signal whose current driving capability is increased to drive switching of an image signal output pass gate connected to a source line of a liquid crystal panel in response to the output switching control signal and a predetermined second input signal. Generate and print
    [40] Here, when the predetermined first input signal of the counter unit 100 is a share enable signal for controlling generation of the share switching control signal and an output enable signal for controlling generation of the output switching control signal, The counter unit 100 generates the share switching control signal and the output switching control signal. The share enable signal is in a first logic state, and when the output enable signal is activated in a second logic state, that is, the share enable signal is in a high state, and the output enable signal is At the falling edge, the counter unit 100 activates the share switching control signal and the output switching control signal. Here, the logic states may be interchanged, and the logic circuit may be easily implemented at this time.
    [41] In addition, when the predetermined second input signal of the image switching controller 300 is an output enable signal for controlling the generation of the output switching control signal, the image switching controller 300 drives the pass gate for outputting the image signal. Generate and output a signal. In addition, when the output switching control signal and the predetermined second input signal have the same logic state, that is, when all of them are in a low state, the image switching control unit 300 generates and outputs a pass gate driving signal for outputting the image signal. Done. Here, the logic states may be interchanged, and the logic circuit may be easily implemented at this time.
    [42] 9A and 9B are timing diagrams for describing the switching control of the source driver output buffer shown in FIG. 8 in more detail. Here, FIG. 9A illustrates a timing diagram in the share enable mode, and FIG. 9B illustrates a timing diagram in the share disable mode. The share enable mode assumes that the share enable signal 6 goes high in digital logic, and the share disable mode assumes that the share enable signal 6 goes low. Assume that At this time, the output enable signal OEN and the share enable signal SEN 6 are received from the PCB module controlling the source driver.
    [43] Referring to FIG. 9A, a pass gate driving signal SWO for outputting an image signal is disabled at a rising of an output enable signal OEN 1, and an output enable signal OEN 1. The share voltage output pass gate drive signal SWS is enabled during the T1 period (sharing width) from the falling edge of the pre-charging edge. In addition, after the T2 time, the pass gate driving signal SWO for image signal output is enabled to output the image signal of the amplifier 220 to the data line to drive pixels connected to each channel at a constant image voltage.
    [44] That is, in the share enable mode, the share enable signal (SEN) 6 is in a high state, and at this time, the output enable signal (OEN) 1 has a certain period of time. Upon entering the input, the counter unit 100 counts any number n of the main clock (SCLK) 5 at the falling edge of the output enable signal (OEN) 1 to form a logic state during the T1 period. Generates the share switching control signal 3 inverted. In addition, the counter unit 100 outputs the logic state inverted during the period T2 by counting any number m of the main clock SCLK 5 at the falling edge of the output enable signal OEN 1. A switching control signal (inverter input terminal signal for outputting four signals) is generated. Here, n and m, which are arbitrary numbers of the main clock (SCLK) 5, are determined in consideration of the design of the liquid crystal panel, so that the share voltage (or precharge voltage) is sufficiently charged in the data line during the T1 period. The T2 period is determined to give a considerable margin in consideration of the deviation of the T1 section of the entire liquid crystal panel. The counter 100 counts a predetermined number of cycles of the main clock (SCLK) 5 so as to satisfy T1 and T2 determined as described above.
    [45] Therefore, the share switching control signal 3 generated as described above is input to the share switching control unit 200, and accordingly, the share switching control unit configured of a circuit such as a predetermined inverter to improve the current driving capability ( 200 converts and outputs a signal SWS having an increased current driving capability to drive switching of a pass gate for share voltage output connected to a source line of the liquid crystal panel. In addition, the output switching control signal (inverter input terminal signal for outputting 4 signals) generated as described above and the output enable signal 1 in a low state are input to the image switching controller 300, and both are inverted. The image switching control unit 300 is input to an AND logic circuit, and thus, a signal SWO having an increased current driving capability so as to drive switching of an image signal output pass gate connected to a source line of a liquid crystal panel. Is generated in the high state and output.
    [46] Referring to FIG. 9B, a share disable mode in which the share enable signal 6 is in a low state, wherein the output enable signal OEN 1 has a constant period and is input to the counter unit 100. Even if it enters, the counter unit 100 maintains the share switching control signal 3 and the output switching control signal (inverter input terminal signal outputting four signals) to a low state so that there is no precharging interval. Accordingly, a current drive capable of driving switching of a pass gate for outputting an image signal connected directly to the source line of the liquid crystal panel at the falling edge of the output enable signal 1 without counting the main clock (SCLK) 5 as described above. Only signal SWS with increased capability is to be output high.
    [47] Table 1 shows the experimental results of the output buffer control device output of the source driver for driving the liquid crystal display according to the present invention configured as described above.
    [48] [Table 2] shows the frequency of the main clock (SCLK) (5) according to the resolution and frame frequency of the liquid crystal display device, as shown in the [Table 1] source due to device characteristic nonuniformity in the manufacturing process It can be seen that the sharing width deviation between the drivers is lowered below the main clock (SCLK) 5 skew.
    [49] TABLE 1
    [50]
    [51] TABLE 2
    [52]
    [53] As described above, in the output buffer control apparatus of the source driver for driving the liquid crystal display according to the present invention, the counter unit 100 first starts a predetermined number of cycles of the main clock (SCLK) 5 in response to a predetermined input signal. The share switching control signal 3 and the output switching control signal (inverter input terminal signal outputting four signals) are generated. Accordingly, the share switching controller 200 receives the share switching control signal 3 as a signal having an increased current driving capability so as to drive switching of the share voltage output pass gate connected to the source line of the liquid crystal panel. Change the output. The image switching controller 300 may drive switching of an image signal output pass gate connected to a source line of a liquid crystal panel in response to the output switching control signal (inverter input terminal signal for outputting four signals) and a predetermined input signal. It generates and outputs a signal with increased current drive capability.
    [54] The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
    [55] As described above, the output buffer control device of the source driver for driving the liquid crystal display according to the present invention is a variation of the output time between the source drivers due to the nonuniformity of device characteristics that may appear in the semiconductor manufacturing process of the LCD source driver. Due to this, it is possible to improve the block defect of the LCD panel.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] A counter unit for generating a share switching control signal and an output switching control signal in which logic states are inverted by a predetermined number of main clock cycles in correspondence with the first predetermined input signal;
    A share switching control unit receiving the share switching control signal and converting the shared switching control signal into a signal having an increased current driving capability so as to drive switching of the pass voltage output pass gate connected to the source line of the liquid crystal panel; And
    Image switching for generating and outputting a signal having an increased current driving capability to drive switching of an image signal output pass gate connected to a source line of a liquid crystal panel in response to the output switching control signal and a predetermined second input signal. An output buffer control device for a source driver for driving a liquid crystal display device, characterized in that it comprises a control unit.
    [2" claim-type="Currently amended] The method of claim 1, wherein the predetermined first input signal,
    And a share enable signal for controlling generation of the share switching control signal and an output enable signal for controlling generation of the output switching control signal.
    [3" claim-type="Currently amended] 3. The method of claim 2, wherein the share enable signal is in a first logic state, and the counter unit activates the share switching control signal and the output switching control signal when the output enable signal is activated to a second logic state. And an output buffer control device for a source driver for driving a liquid crystal display device.
    [4" claim-type="Currently amended] The method of claim 1, wherein the predetermined second input signal,
    And an output enable signal for controlling generation of the output switching control signal.
    [5" claim-type="Currently amended] The apparatus of claim 1, wherein the output switching control signal and the predetermined second input signal have the same logic state.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-12-10|Application filed by 삼성전자주식회사
    2002-12-10|Priority to KR1020020078384A
    2004-06-16|Publication of KR20040050531A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020078384A|KR20040050531A|2002-12-10|2002-12-10|Output buffer control apparatus of source driver driving the liquid-crystal display|
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