 Semiconductor package and manufacturing method of the same
专利摘要:
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to improve adhesion between a semiconductor chip and a substrate by using a laser, and to minimize thermal damage of a material constituting the semiconductor package, and a method of manufacturing the same. It is about. According to an aspect of the present invention, there is provided a method of fabricating a semiconductor package, the method including: (a) preparing a semiconductor chip having bumps formed on at least one surface thereof; (b) preparing a substrate having an inner lead connected to the bump on at least one surface thereof; (c) applying an adhesive on the inner lead formed substrate; (d) securing the semiconductor chip to a bonding head; (e) fixing the adhesive-coated substrate to a bonding stage; (f) mutually aligning positions of the semiconductor chip fixed to the bonding head and the substrate fixed to the bonding stage; And (g) bonding the bump and the inner lead using a laser. 公开号:KR20040045388A 申请号:KR1020030084212 申请日:2003-11-25 公开日:2004-06-01 发明作者:이영호；정하천；김홍식；임현태 申请人:삼성테크윈 주식회사； IPC主号:
专利说明:
Semiconductor package and manufacturing method of the same [14] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to improve adhesion between a semiconductor chip and a substrate by using a laser, and to minimize thermal damage of materials constituting the semiconductor package. And to a method for producing the same. [15] In particular, the present invention provides a COF semiconductor package in which a semiconductor chip for driving a liquid crystal display (LCD) panel is bonded to an inner lead of a chip on flex (COF) substrate in a flip chip structure. Applicable to, it can be used in LCD panels employed in notebook computers, monitors, televisions, or mobile communication equipment. [16] In general, in the method of manufacturing a semiconductor package, a film type package is used as a method for connecting a driving integrated circuit. A film type package connected to a panel for a display device such as a liquid crystal display panel (LCD) is used for tape automated. Bonding) or COF (Chip On Flex) method is used. [17] The tape carrier package providing the film package of this type is composed of a carrier tape and a circuit portion on which a semiconductor chip is mounted. The carrier tape consists of a substrate of a base film using polyimide. An inner lead, which is an electrode for connecting with a semiconductor chip, and an outer lead, which is an electrode for connecting with an LCD glass and a printed circuit board, are formed. [18] Methods of attaching and connecting bumps of conventional semiconductor chips to electrodes formed on a substrate are disclosed in US Pat. No. 5,928,458 and US Pat. No. 6,365,435. The content described in the specification of the US patent is to be included in the specification of the present invention, a detailed description thereof will be omitted. [19] 1A to 1E schematically illustrate each step of a method of manufacturing a semiconductor package in which a conventional semiconductor chip is mounted on a film substrate in a flip chip structure. [20] Referring to the drawings, a method of manufacturing a semiconductor package using gold stud bumps using a wire bonder facility is shown. [21] Conventional semiconductor package manufacturing method is to bond the bump formed on the semiconductor chip to the inner lead electrode formed on the substrate, and to form an underfill layer by filling a predetermined sealing material between the semiconductor chip and the substrate bonded to each other, Encapsulation is formed by enclosing the semiconductor chip with a sealing material. [22] First, the predetermined circuit pattern 12 is formed in one surface on the film-form board | substrate 11 (FIG. 1A). In addition, one surface of the semiconductor chip 13 serves as an electrode of the semiconductor chip, and a bump 14 connected to a circuit pattern formed on the substrate is formed (FIG. 1B). [23] Next, the semiconductor chip 13 on which the bumps 14 are formed is fixed to the bonding head 15, and the substrate 11 on which the circuit pattern 12 is formed is fixed to the bonding station 16. The positions of the bonding head 15 to which the 13 is fixed and the bonding station 16 to which the substrate 11 is fixed are aligned with each other (FIG. 1C). At this time, the substrate 11 and the bonding head 15 may be heated. [24] After lowering the bonding head 15 to contact the bump 14 formed on the semiconductor chip on the circuit pattern 12 formed on the substrate, the pressure is applied to the semiconductor chip 13 from the bonding head 15. Then, heat is applied to each other for a predetermined time period (FIG. 1D). [25] Next, an underfill layer 17 is formed between the bump and the substrate including the bonding portion between the bump 14 and the circuit pattern 12 on the substrate with a predetermined sealing material using a binder injector 19. (FIG. 1E). [26] However, in the method of manufacturing a semiconductor package as described above, heat is applied to the entire chip while applying pressure to the semiconductor chip for a predetermined time, so that each material constituting the COF package is exposed to high temperature (280 to 300 degrees Celsius) for several seconds. Thermal damage can remain in the semiconductor package. [27] In addition, there is a need for an additional process of forming an underfill or encapsulation using a predetermined sealant, which leads to complicated manufacturing processes and high manufacturing costs. [28] In addition, since the substrate and the semiconductor chip have different thermal strains, there is a problem in that the substrate and the semiconductor chip are not bonded at the correct position when the semiconductor chip and the substrate are bonded. [29] The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor package and a method of manufacturing the same, which improves adhesion between the semiconductor chip and the substrate and minimizes thermal damage of materials constituting the semiconductor package. [30] It is still another object of the present invention to provide a semiconductor package having a structure capable of applying heat to a precise contact portion between a semiconductor chip and a substrate regardless of the size of the semiconductor chip and a method of manufacturing the same. [1] 1A to 1E schematically illustrate each step of a method of manufacturing a semiconductor package in which a conventional semiconductor chip is mounted in a flip chip structure on a film type substrate. [2] 2 is a block diagram schematically illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [3] 3A to 3E are diagrams schematically illustrating respective steps of a method of manufacturing a semiconductor package in which a semiconductor chip is mounted in a flip chip structure on a film type substrate as a preferred embodiment of the present invention. [4] FIG. 4 is a view schematically illustrating a semiconductor package according to the method of manufacturing the semiconductor package of FIG. 2. [5] FIG. 5 is a diagram schematically illustrating that the semiconductor package of FIG. 4 is connected to an LCD device. [6] <Description of Symbols for Major Parts of Drawings> [7] 3: semiconductor package 31: substrate [8] 32: inner lead 322: tin plating layer [9] 33: semiconductor chip 34: bump [10] 341: nickel plated layer 342: gold plated layer [11] 35: bonding head 36: bonding stage [12] 37: adhesive 38: laser means [13] 40: underfill layer 50: bonding means [31] In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention, [32] A method of manufacturing a semiconductor package for mounting a semiconductor chip in a flip chip structure on a substrate, [33] (a) preparing a semiconductor chip having bumps formed on at least one surface thereof; [34] (b) preparing a substrate having an inner lead connected to the bump on at least one surface thereof; [35] (c) applying an adhesive on the inner lead formed substrate; [36] (d) securing the semiconductor chip to a bonding head; [37] (e) fixing the adhesive-coated substrate to a bonding stage; [38] (f) mutually aligning positions of the semiconductor chip fixed to the bonding head and the substrate fixed to the bonding stage; And [39] (g) bonding the bump and the inner lead by using a laser. [40] The bump may include a nickel plating layer formed on the at least one surface of the semiconductor chip by electroless plating nickel at a thickness of 5 μm or more, and a gold plating layer formed on the nickel plating layer by electroless plating gold at a thickness of 0.05 μm or more. It is preferable. [41] It is also preferable that the adhesive is a non-conductive adhesive having heat curability. [42] In addition, the step (g), it is preferable that the step of applying a pressure in the direction of the substrate to the semiconductor chip. [43] In this case, the pitch between the bumps may be formed to 60㎛ or less. [44] On the other hand, it is preferable that the inner lead comprises a circuit pattern of copper formed on one surface of the substrate and a tin plating layer formed by electroless plating tin on the circuit pattern. In this case, the tin plating layer has a thickness of 0.15 μm or more. It is more preferable that it is formed to have. [45] Meanwhile, a through hole through which a laser beam passes is formed in the bonding head, and focuses the laser beam passing through the semiconductor chip through the through hole at an interface between the bump and the inner lead and heats the bonding stage. In addition, it is preferable to bond and fix the semiconductor chip on the substrate. In this case, the bonding head includes a lens for focusing the laser beam on an interface portion of an inner lead corresponding to the bump and the semiconductor chip. Preferably, the lens has a focusing structure in which a focused position is changed according to the size of the semiconductor chip, and the laser beam has a wavelength of about 1064 nm. [46] A semiconductor package according to another aspect of the present invention, [47] A semiconductor chip having a plurality of bumps formed on at least one surface thereof with a nickel plating layer formed by nickel plating with a predetermined thickness and a gold plating layer formed by gold plating with a predetermined thickness on the nickel plating layer; [48] A substrate on which at least one surface has an inner lead including a circuit pattern of copper and a tin plating layer formed on the circuit pattern with a predetermined thickness; [49] Bonding means formed by joining a gold plating layer of the semiconductor chip bump and a tin plating layer contact portion of the inner lead by a process reaction by heat applied by a laser means; And [50] And a non-conductive adhesive for sealing between the semiconductor chip and the substrate. [51] The nickel plating layer, the gold plating layer, and the tin plating layer are each formed by electroless plating. [52] In this case, the bump includes a nickel plating layer formed by electroless plating nickel at a thickness of 5 μm or more on at least one surface of the semiconductor chip, and a gold plating layer formed by electroless plating gold having a thickness of 0.05 μm or more on the nickel plating layer. It is desirable to be done. [53] In addition, the pitch between the bumps is preferably formed to 60㎛ or less. [54] In this case, it is preferable that the underfill layer is made of a non-conductive adhesive having heat curability. [55] In addition, the bonding means is preferably bonded by heat generated when the laser beam transmitted through the semiconductor chip is focused on the contact portion between the tin plating layer and the gold plating layer. [56] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. [57] 2 is a block diagram schematically illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [58] Referring to the drawings, a method of manufacturing a semiconductor package for mounting a semiconductor chip in a flip chip structure on a substrate may include preparing a semiconductor chip 201, preparing a substrate 202, applying an adhesive 203, and fixing a semiconductor chip 204. ), A substrate fixing step 205, a position alignment step 206, and a laser bonding step 207. [59] In the semiconductor chip preparation step 201, a semiconductor chip is prepared and a plurality of bumps are formed on one surface thereof to be electrically connected to the substrate. In the substrate preparation step 202, an inner lead is prepared by preparing a substrate by a predetermined process and electrically connected to bumps formed on the semiconductor chip. [60] In addition, in the adhesive applying step 203, an adhesive is applied on the substrate on which the inner lead is formed. In the semiconductor chip fixing step 204, the semiconductor chip having bumps formed on at least one surface thereof is fixed to a bonding head. In the substrate fixing step 205, the substrate to which the adhesive is applied is fixed to the bonding stage. [61] In addition, in the position alignment step 206, the positions of the semiconductor chip fixed to the bonding head and the substrate fixed to the bonding stage are mutually aligned. In the laser bonding step 207, the bump formed on the semiconductor chip and the inner lead formed on the substrate are bonded to each other using a laser. [62] At this time, before the adhesive is applied on the substrate on which the inner lead is formed in the adhesive applying step 203, the method includes moving the substrate on which the inner lead is formed to a position where an adhesive applicator for applying the adhesive is installed. desirable. [63] In addition, before fixing the substrate to which the adhesive is applied to the bonding stage in the substrate fixing step 205, it is preferable to include the step of moving the substrate to which the adhesive stage is installed. [64] A plurality of bumps are formed on the semiconductor chip according to a circuit configuration of the semiconductor chip, and the bumps are preferably formed by electroless plating of nickel and gold on the semiconductor chip in order. The bump may include a nickel plating layer formed by electroless plating nickel at a thickness of 5 μm or more on at least one surface of the semiconductor chip, and a gold plating layer formed by electroless plating gold having a thickness of 0.05 μm or more on the nickel plating layer. It is preferable that, due to this, it is possible to realize a fine pitch on the manufacturing process, the distance (hereinafter, the pitch) between the bumps can be formed to 60㎛ or less. [65] The inner lead is preferably formed by an electroless plating method, and a circuit pattern of copper formed on one surface of the substrate and tin is electroless plated to a thickness of 0.15 μm or more, more preferably 0.4 μm or more on the circuit pattern. It is preferable to comprise the formed tin plating layer. [66] It is preferable that the gold plating layer of the bumps and the tin plating layer of the inner lead be heated at mutual bonding sites by using a laser to mutually react reaction bonding to connect the semiconductor chip on the substrate. [67] In addition, the adhesive is made of a non-conductive adhesive having a heat curable, the semiconductor chip and the substrate is electrically connected to the bump and the inner lead formed in each, and the connection between the bump and the inner lead by the adhesive It is insulated from the outside, and the semiconductor chip is physically fixed and sealed on the substrate. [68] At this time, since the laser beam scanned during the bonding of the bump and the inner lead can be focused to the junction of the bump and the inner lead as much as possible, it is easy to generate a compound by a process reaction at the joining surface and thus the interface between Adhesion can be improved, and heat transfer to the adhesive to cure, thereby minimizing the possibility of thermal damage remaining in the materials constituting the COF package. [69] In this case, the method of manufacturing the semiconductor package is not only performed according to the above-described order, and the order of each step of the method of manufacturing the semiconductor package may be changed within a range capable of achieving the object of the present invention according to a specific embodiment. There will be. [70] 3A to 3E are diagrams schematically illustrating respective steps of a method of manufacturing a semiconductor package in which a semiconductor chip is mounted in a flip chip structure on a film type substrate as a specific embodiment of the present invention. [71] 3A illustrates that bumps 34 are formed on one surface of the semiconductor chip 33 in the semiconductor chip preparation step 201, and the semiconductor chip 33 manufactured by a predetermined semiconductor chip manufacturing process is prepared. One surface thereof is provided with a bump 34 for electrically connecting with the substrate 31. [72] A plurality of bumps 34 are formed on the semiconductor chip 33 according to the circuit configuration of the semiconductor chip 33. The bumps 34 are formed by sequentially electroless plating nickel and gold on the semiconductor chip 33. desirable. In this case, the bump 34 is a nickel plating layer 341 formed by electroless plating nickel on one surface of the semiconductor chip with a thickness of 5 μm or more, and formed by electroless plating gold on the nickel plating layer with a thickness of 0.05 μm or more. It is preferable to comprise the gold plating layer 342. [73] The gold plating layer 342 is formed on the nickel plating layer 341 and serves to prevent oxidation of the nickel plating layer, and the outermost layer of the inner lead 32 is bonded to the inner lead 32 on the substrate. Process reaction bonding is achieved. [74] Nickel / gold bumps by electroless plating according to the present invention are preferably formed through a process of aluminum etching, zinc etching, nickel plating, and gold plating. [75] 3B illustrates that the inner lead 32 is formed on one surface of the substrate 31 in the substrate preparing step 202. The substrate 31 is prepared by a predetermined process, and the semiconductor chip is disposed on the semiconductor chip. An inner lead 32 is electrically connected to the bump 34 to be formed. [76] In this case, the inner lead 32 is a copper circuit pattern 321 formed on one surface of the substrate, and a tin plating layer formed by electroless plating tin on the circuit pattern to a thickness of 0.15 μm or more, preferably 0.4 μm or more ( 322 is preferably provided. [77] The tin plating layer 322 serves to prevent oxidation of the circuit pattern 321 of copper. The tin plating layer 322 is subjected to process reaction bonding with the gold plating layer 342 of the bump, and the semiconductor chip 33 is attached to the substrate 31. ) To the top. [78] The inner lead 32 formed on the substrate is bonded to the bump 34 serving as an input / output terminal of the semiconductor chip in order to connect the semiconductor chip 33 to an external circuit so that the semiconductor chip performs a predetermined function. It is formed at a position on the substrate 31 that can be. [79] 3C shows that the adhesive is applied onto the substrate 31 on which the inner lead is formed in the adhesive applying step 203. The adhesive is applied so that the inner lead 32 is sufficiently applied using a predetermined adhesive injector 39. 37 is injected onto the substrate 31. [80] The adhesive 37 preferably has a thermosetting property so that the adhesive 37 may be cured by heat generated during laser irradiation. [81] In addition, although the adhesive 37 is a paste type in the present embodiment, a film type adhesive may be applied depending on the embodiment in which the adhesive 37 is used. [82] 3D illustrates that the semiconductor chip 33 having bumps 34 formed on at least one surface in the semiconductor chip fixing step 204 is fixed to the bonding head 35, and the adhesive on at least one surface in the substrate fixing step 205. Is applied to the bonding stage 36 and the semiconductor chip 33 and the bonding stage 36 fixed to the bonding head 35 in the alignment step 206. The position of the board | substrate 31 is shown mutually aligned. [83] In the semiconductor chip fixing step 204, the semiconductor chip 33 is fixed to the bonding head 35, and the bonding head 35 fixes the semiconductor chip 33 by using an adsorption means such as a vacuum device. . [84] An adsorption hole 351 is formed in the bonding head 35 through the bonding head, and a vacuum is formed in the adsorption hole 351. Therefore, the bonding head 35 fixes the semiconductor chip 33 by bringing the lower surface of the bonding head 35 into close contact with the upper surface of the semiconductor chip 33. [85] The bonding head 35 is moved to position the lower surface of the bonding head 35 on the upper surface of the semiconductor chip 33, to form a vacuum in the suction hole 351 of the bonding head 35, and to apply the vacuum. The upper surface of the semiconductor chip 33 is attracted to the lower surface of the bonding head 35 by the adsorption force, thereby fixing the semiconductor chip 33. [86] In the method of fixing the semiconductor chip 33 on the substrate 31 by a conventional hot pressing method, a plurality of small vacuum suction holes are formed in the bonding head 35, and the bonding heads are formed through the plurality of suction holes. A vacuum is formed on the lower surface of 35 to adsorb the semiconductor chip 33. [87] However, in the exemplary embodiment of the present invention, the suction hole 351 is formed in the bonding head 35 so that the laser passing through the lens can pass through the semiconductor chip without being disturbed by other obstacles. In this case, the suction hole 351 is formed to a size that the semiconductor chip can be supported on the bonding head 35 during the process. Therefore, if the semiconductor chip 33 can be supported by the bonding head 35, the suction hole 351 may be formed to a size such that the laser can be irradiated to the entire bump 34. [88] In the substrate fixing step 205, the substrate 31 coated with the adhesive on at least one surface thereof is fixed to the bonding stage 36, wherein the substrate is formed by adsorption means such as a vacuum device formed on the bonding stage 36. It is fixed to the bonding stage 36. [89] At least one adsorption hole 361 is formed in the bonding stage 36 to penetrate the bonding stage, and a vacuum is formed in the adsorption holes, so that the substrate 31 is formed on the upper surface of the bonding stage 36. ) And the lower surface of the substrate is fixed to the bonding stage. [90] In this case, in order to fix the substrate to which the adhesive is applied to the bonding stage in the substrate fixing step 205, it is preferable to include moving the substrate to which the adhesive stage is installed. [91] In the position aligning step 206, the positions of the semiconductor chip 33 fixed to the bonding head 35 and the substrate 31 fixed to the bonding stage 36 are aligned with each other. (31) Correctly position the bumps to be bonded to each other on the inner lead. [92] At this time, a fiducial mark is applied to a predetermined position of the semiconductor chip adsorbed by the bonding head 35, and the mutual recognition between the bumps of the semiconductor chip is performed by recognizing the mutually distorted degree through position recognition equipment such as vision. Positions of at least one of the bonding head 35 or the bonding stage 36 are aligned to match the position of the inner lead 32 on the substrate. [93] FIG. 3E illustrates bonding and fixing the semiconductor chip 33 onto the substrate 31 using a laser in the laser bonding step 207, wherein the semiconductor chip 33 is used by laser means 38. Heat is applied to the lower surface and the inner lead 32 joint portion of the substrate 31 to be bonded to each other, and at the same time, the underfill layer 40 is formed using the heat. [94] At this time, the laser focuses the laser beam formed by the laser means 38 through the lens 381 to scan the laser beam on the semiconductor chip 33. The laser beam is scanned through the adsorption hole 351 formed in the bonding head, and is bonded to the gold plating layer 342 of the bump formed on the bottom surface of the semiconductor chip and the tin plating layer 322 of the inner lead formed on the upper surface of the substrate. The laser beam is focused to apply heat to the junction. [95] In the laser bonding step 207, the semiconductor chip 33 fixed to the bonding head 35 is placed on the substrate 31 fixed to the bonding stage 36, and the laser means is fixed by the above method. An inner lead formed on the upper surface of the bump and the gold plating layer 342 of the bump formed on the lower surface of the semiconductor chip while applying heat to all the joint portions of the gold plating layer 342 and the tin plating layer 322 through the 38. Pressure is applied on the semiconductor chip 33 so that the tin plating layers 322 contact each other. In this case, the lens 381 may have a focusing structure capable of focusing the laser with the entire bump, corresponding to the focused position that changes according to the size of the semiconductor chip 33, which is because of this, the size of the semiconductor chip. Irrespective of the misalignment caused by the difference in thermal strain between the substrate 31 and the semiconductor chip 33, heat can be applied only at the exact junction between the gold plating layer 342 and the tin plating layer 322 regardless of the heat transfer rate. (2) does not occur, and the bump 34 and the inner lead 32 adhere well. [96] In this case, although the laser means 38 is not shown, a laser generating device, a driving device for moving the bonding head 35 provided with the lens 381 up, down, left and right, a position sensing sensor, etc. It can be provided. [97] As described above, in order to fix the semiconductor chip 33 on the substrate 31 by the laser means 38, the laser beam is focused on the bonding portion through the lens 381 and heat is applied thereto. In this case, the laser beam used has a wavelength that can transmit the semiconductor chip. In particular, the laser beam uses a special wavelength of about 1064 nm through which a silicon (Si) -based semiconductor chip can be transmitted. In this case, the laser beam exhibits a chip transmittance of about 40%. [98] Heat is generated by the laser means 38, and fluidity is generated in the adhesive 37 interposed between the semiconductor chip 33 and the substrate 31 by the heat. The lower surface of the semiconductor chip 33 is evenly filled by enclosing and sealing the adhesive surfaces of the gold plating layer 342 and the tin plating layer 322 while being pushed out of the lower surface. [99] In the present invention, the gold plated layer 342 of the bumps and the tin plated layer 322 of the inner lead is increased as much as possible from the existing thickness or manufacturable level, thereby increasing the adhesion between the two metals to induce process compounds to produce fine pitch between the bumps. Adopt possible bonding mechanisms. [100] At this time, in the conventional semiconductor package has a pitch of about 100㎛, according to the present invention, as described above, the bump 34 can be formed at a fine pitch of 60㎛ or less level, thereby, A semiconductor package can be obtained. [101] In order to obtain the semiconductor package of the fine pattern, the bump 34 is a nickel plating layer 341 formed by electroless plating nickel at a thickness of at least 5 μm on at least one surface of the semiconductor chip, and 0.05 μm of gold on the nickel plating layer. It is preferable to comprise the gold plating layer 342 formed by electroless plating with the above thickness. [102] In addition, the inner lead 32 is formed of a copper circuit pattern 321 formed on one surface of the substrate and tin formed by electroless plating tin on the circuit pattern with a thickness of 0.15 μm or more, preferably 0.4 μm or more. It is preferable that the plating layer 322 is provided. [103] In the laser system according to the present embodiment, an additional bonding head cooling device is not required by using the heat transfer method by energy transform. In addition, while bonding the bump and the inner lead using the laser, a constant pressure may be applied to the semiconductor chip 33 and a constant temperature may be applied to the bonding stage 36. That is, a relatively low pressure of 10 to 15 gf per bump is applied between the semiconductor chip 33 and the substrate 31, and the bonding stage 36 is used as a heater block at a temperature of 60 to 100 ° C. It is possible to apply the heat of, thereby smoothly joining the bump and the inner lead. [104] At this time, the size of the suction hole 351 is formed so that the laser beam passes through the entire bonding head 35 as described above, so that the laser beam is applied to all the bumps formed on the lower surface of the semiconductor chip 33. Can be injected at the same time. [105] 4 is a schematic view of a semiconductor package according to the method of manufacturing the semiconductor package of FIG. 2. [106] Referring to the drawings, the semiconductor package 3 according to another aspect of the present invention comprises a substrate 31, a semiconductor chip 33, a bonding means 50, and an underfill layer 40, which is a non-conductive adhesive. . In this case, the semiconductor chip 33 is connected to an external circuit to perform a predetermined function, and the substrate 31 is mounted on the semiconductor chip 33 and connected to an external circuit (not shown), and the underfill layer 40 is interposed between the semiconductor chip 33 and the substrate 31 to fix and seal the semiconductor chip 33 on the substrate 31. [107] In addition, it is preferable that an outer portion (not shown) is formed on the substrate 31 in order to connect with an external circuit in which the semiconductor chip 33 is used. [108] A plurality of bumps 34 serving as connection terminals for connecting to the substrate 31 are formed on the semiconductor chip 33, and the bumps include a nickel plating layer 341 and a gold plating layer 342. . In addition, the distance between the bumps, that is, the pitch may be formed to 60㎛ or less. [109] In this case, the nickel plating layer 341 is formed by plating nickel at a predetermined thickness on at least one surface of the semiconductor chip 33. In addition, the gold plating layer 342 is formed by gold plating a predetermined thickness on the nickel plating layer 341, and serves to prevent oxidation of the nickel plating layer 341. [110] An inner lead 32 connected to the semiconductor chip 33 and the bump 34 is formed on the substrate 31. The inner lead 32 forms a circuit pattern 321 and a tin plating layer 322. It is made. [111] In this case, the circuit pattern 321 is preferably formed of copper as a circuit pattern formed on the substrate 31 to implement the function of the semiconductor chip 33 by connecting the semiconductor chip 33 with an external circuit. In addition, the tin plating layer 322 is formed by tin plating on the circuit pattern 321 and serves to prevent oxidation of the circuit pattern 321 of copper. [112] In addition, the nickel plating layer 341, the gold plating layer 342, and the tin plating layer 322 are preferably formed by electroless plating. [113] The bump may include a nickel plating layer formed by electroless plating nickel at a thickness of 5 μm or more on at least one surface of the semiconductor chip, and a gold plating layer formed by electroless plating gold having a thickness of 0.05 μm or more on the nickel plating layer. It is preferable. [114] The connection between the semiconductor chip 33 and the substrate 31 is by the coupling between the gold plating layer 342 and the tin plating layer 322. In the present invention, the gold plating layer ( 342 and the tin plating layer 322 are applied by applying heat to each other to be bonded by a process reaction bond. That is, the bonding means 50 is preferably bonded by heat generated when the laser beam transmitted through the semiconductor chip is focused on the contact portion between the tin plating layer 322 and the gold plating layer 342. [115] The underfill layer 40 is formed to be interposed between the semiconductor chip and the substrate to seal the mutual coupling portion, and is preferably made of a non-conductive adhesive having heat curability. In addition, in the case of the present invention, the underfill layer 40 is not subjected to a separate underfill forming process, and a pre-coated adhesive is used during the process reaction bonding of the gold plating layer 342 and the tin plating layer 322. When the gold plating layer 342 and the tin plating layer 322 are bonded together by the heat source. [116] FIG. 5 is a diagram schematically illustrating that the semiconductor package of FIG. 4 is connected to an LCD device. [117] Referring to the drawings, the semiconductor package 3 is connected to the liquid crystal display (LCD) device 5 by the outer bonding 42. The semiconductor package 3 is formed by connecting the semiconductor chip 33 by an inner lead bonding 41 on a flexible film-type substrate 31. In addition, a glass layer 51 and an LCD substrate 52 are formed in the LCD device 5, and the semiconductor chips 33 are connected to each other. [118] At this time, outer ends are formed at both ends of the substrate 31 and are connected to the LCD device through the outer leads, wherein the substrate 31 is a glass layer 51 and the LCD substrate 52 of the LCD device. A predetermined connection terminal (not shown) formed in each of the and an outer bonding 42 is connected to the LCD device 5. [119] In the semiconductor package and a method of manufacturing the same according to the present invention, the bumps formed on the semiconductor chips and the inner leads formed on the substrate are plated by an electroless plating method, so that the equipment is simple and the steps of the manufacturing process are reduced. Can be reduced, and fine pitch in the manufacturing process can be realized. [120] In addition, since the underfill layer is formed at the same time as the bump and the inner lead are bonded after applying the non-conductive adhesive on the substrate on which the inner lead is formed, there is no need to further form the underfill layer, thus simplifying the construction of the equipment and manufacturing process. Reduced production costs can be reduced. [121] In addition, the bump and the inner lead are bonded by using a laser, and the scanned laser beam can be focused to the junction of the bump and the inner lead to the maximum, and the compound is easily generated to improve the adhesion between the interfaces. As a result, local heat transfer to the package allows bonding and curing to minimize the possibility of thermal damage remaining in the materials that make up the COF package. [122] Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.
权利要求:
Claims (17) [1" claim-type="Currently amended] A method of manufacturing a semiconductor package for mounting a semiconductor chip in a flip chip structure on a substrate, (a) preparing a semiconductor chip having bumps formed of nickel and gold plating on at least one surface by an electroless plating method; (b) preparing a substrate having an inner lead connected to the bump on at least one surface thereof; (c) applying an adhesive on the inner lead formed substrate; (d) securing the semiconductor chip to a bonding head; (e) fixing the adhesive-coated substrate to a bonding stage; (f) mutually aligning positions of the semiconductor chip fixed to the bonding head and the substrate fixed to the bonding stage; And (g) bonding the bump and the inner lead using a laser. [2" claim-type="Currently amended] The method of claim 1, The bumps are formed on at least one surface of the semiconductor chip with a nickel plating layer formed by electroless plating with a thickness of 5 µm or more, and a gold plating layer formed by electroless plating gold with a thickness of 0.05 µm or more on the nickel plating layer. A method of manufacturing a semiconductor package. [3" claim-type="Currently amended] The method of claim 1, The adhesive is a method of manufacturing a semiconductor package, characterized in that the non-conductive adhesive having a thermosetting. [4" claim-type="Currently amended] The method of claim 1, The pitch of the bumps is a manufacturing method of a semiconductor package, characterized in that formed in less than 60㎛. [5" claim-type="Currently amended] The method of claim 1, The method of manufacturing a semiconductor package according to the step (g) includes applying a pressure to the semiconductor chip in the direction of the substrate. [6" claim-type="Currently amended] The method of claim 1, And a tin plating layer formed by electroless plating tin on the circuit pattern, wherein the inner lead is formed on one surface of the substrate. [7" claim-type="Currently amended] The method of claim 6, The tin plating layer is a manufacturing method of a semiconductor package, characterized in that formed to have a thickness of 0.15㎛ or more. [8" claim-type="Currently amended] The method of claim 1, A through hole through which a laser beam passes is formed in the bonding head, and the laser beam penetrating the semiconductor chip through the through hole is focused on an interface between the bump and the inner lead and heat is applied to the bonding stage. And manufacturing and bonding the semiconductor chip onto the substrate. [9" claim-type="Currently amended] The method of claim 8, The lens has a focusing structure in which the focusing position is changed in accordance with the size of the semiconductor chip manufacturing method of the semiconductor package. [10" claim-type="Currently amended] The method of claim 9, The bonding head is provided with a lens for focusing the laser beam on the interface portion of the inner lead corresponding to the bump and the semiconductor chip. [11" claim-type="Currently amended] The method according to any one of claims 8 to 10, And said laser beam has a wavelength of about 1064 nm. [12" claim-type="Currently amended] A semiconductor chip having a plurality of bumps formed on at least one surface thereof with a nickel plating layer formed by nickel plating with a predetermined thickness and a gold plating layer formed by gold plating with a predetermined thickness on the nickel plating layer; A substrate on which at least one surface has an inner lead including a circuit pattern of copper and a tin plating layer formed on the circuit pattern with a predetermined thickness; Bonding means formed by joining a gold plating layer of the semiconductor chip bump and a tin plating layer contact portion of the inner lead by a process reaction by heat applied by a laser means; And a non-conductive adhesive for sealing between the semiconductor chip and the substrate. [13" claim-type="Currently amended] The method of claim 12, And the nickel plating layer, the gold plating layer, and the tin plating layer are each formed by electroless plating. [14" claim-type="Currently amended] The method of claim 13, The bump includes a nickel plating layer formed by electroless plating nickel at a thickness of 5 μm or more on at least one surface of the semiconductor chip, and a gold plating layer formed by electroless plating gold having a thickness of 0.05 μm or more on the nickel plating layer. Semiconductor package. [15" claim-type="Currently amended] The method of claim 13, The pitch of the bumps is a semiconductor package, characterized in that formed in less than 60㎛. [16" claim-type="Currently amended] The method of claim 12, The nonconductive adhesive is a semiconductor package, characterized in that made of a non-conductive adhesive having a heat curable. [17" claim-type="Currently amended] The method of claim 12, The bonding means is a semiconductor package characterized in that the bonding by the heat generated when the laser beam transmitted through the semiconductor chip is focused on the contact portion of the tin plating layer and the gold plating layer.
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同族专利:
公开号 | 公开日 KR101012701B1|2011-02-09|
引用文献:
公开号 | 申请日 | 公开日 | 申请人 | 专利标题
法律状态:
2002-11-25|Priority to KR1020020073485 2002-11-25|Priority to KR20020073485 2002-11-25|Priority to KR20020073474 2002-11-25|Priority to KR1020020073474 2003-11-25|Application filed by 삼성테크윈 주식회사 2004-06-01|Publication of KR20040045388A 2011-02-09|Application granted 2011-02-09|Publication of KR101012701B1
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