• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A circuit converting data input/output format during a parallel bit test and its method are provided to generate various data patterns even when the number of data input pins is lower than the number of memory cells bound to one column selection line. CONSTITUTION: The first transmission circuit(31) is enabled when the first test mode signal is enabled, and transmits data to m memory cells by receiving n data input from n data input ports. The second transmission circuit(32) is enabled when the second test mode signal is enabled, and transmits data to the m memory cells by receiving n data input from the n data input ports. Data transmitted to a number of adjacent memory cells among the m memory cells are inputted from different input ports among the n data input ports.
    公开号:KR20040043994A
    申请号:KR1020020072477
    申请日:2002-11-20
    公开日:2004-05-27
    发明作者:류진호；신충선；주용규
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    Circuit and method for transforming data input / output format in parallel bit test {Circuit and method for transforming data input output format in parallel bit test}
    [5] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a circuit and a method for converting a data input / output format during a parallel bit test (PBT).
    [6] The parallel bit test (PBT) writes and reads data in parallel to memory cells in a semiconductor memory device to check whether the memory cells and the write / read path fail. By reducing the number of data input / output pins (DQ) in parallel bit testing, you can test a large number of memory devices at the same time. For example, if the number of monitoring pins that can be used in the test equipment is 16, two X8 mode memory devices, four X4 mode memory devices, or eight X2 mode memory devices can be tested.
    [7] Therefore, when testing the parallel bit, it is advantageous to test by reducing the number of data input / output pins (DQ) in terms of test time and cost. In general, an input / output format conversion circuit is used to reduce the number of data input / output pins (DQ) in parallel bit testing.
    [8] 1 is a diagram illustrating an X4 data input / output format, and FIG. 2 is a diagram illustrating a conventional input / output format conversion circuit for converting a data input / output format from an X4 mode to an X2 mode during a parallel bit test. As shown in FIG. 1, when the number of memory cells MC0-MC5 bound to one column select line CSL is equal to the number of data input pins DIN0-DIN3, there is no problem in the test. That is, the data patterns in all cases can be written and read out into four memory cells MC0-MC5 by using four data input pins DIN0-DIN3.
    [9] However, in the circuit shown in FIG. 2, two memory cells are connected to one data input pin by the input / output format conversion circuit 20. That is, two memory cells MC0 and MC1 are connected to one data input pin DIN0 and two memory cells MC4 and MC5 are connected to one data input pin DIN1. As a result, the number of data input pins DIN0 and DIN1 is smaller than the number of memory cells MC0-MC5 bound to one column selection line CSL.
    [10] In this case, data patterns that can be written in the memory cells MC0-MC5 are limited. Table 1 below shows the types of data patterns that can be written in the memory cells MC0-MC5 in the circuit shown in FIG.
    [11] Memory cell Data pattern MC0 0 0 One One MC1 0 0 One One MC4 0 One 0 One MC5 0 One 0 One
    [12] However, when using a data pattern as shown in Table 1, a defect between two adjacent input / output lines, for example, a defect between an input / output line connected to the memory cell MC0 and an input / output line connected to the memory cell MC1 or a memory cell ( The defect between the input / output line connected to the MC4) and the input / output line connected to the memory cell MC5 cannot be checked.
    [13] The reason for this is that the conventional data input / output format conversion circuit 20 shown in FIG. 2 can write different data into two memory cells MC0 and MC1 or two memory cells MC4 and MC5. This is because it is impossible to form (0,1,0,1) or (1,0,1,0).
    [14] Accordingly, an object of the present invention is to provide a data input / output format conversion circuit capable of generating various data patterns even when the number of data input pins is smaller than the number of memory cells bound to one column selection line.
    [15] Another object of the present invention is to provide a data input / output format converting method capable of generating various data patterns even when the number of data input pins is smaller than the number of memory cells bound to one column selection line.
    [1] BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
    [2] 1 is a diagram illustrating an X4 data input / output format.
    [3] 2 is a diagram illustrating a conventional input / output format conversion circuit for converting a data input / output format from an X4 mode to an X2 mode during a parallel bit test.
    [4] 3 is a diagram illustrating a data input / output format conversion circuit according to an embodiment of the present invention.
    [16] The data input / output format conversion circuit according to the present invention for achieving the above technical problem is activated when the first test mode signal is enabled, accepts n data inputs from n (n is a natural number) data input terminals, and m a first transmission circuit for transmitting data to (n or more natural numbers) memory cells, and activated when a second test mode signal is enabled, accepting n data inputs from the n data input terminals, And a second transmission circuit for transmitting data to the memory cells, wherein data transmitted to a plurality of neighboring memory cells among the m memory cells is input from different input terminals of the n data input terminals. It is characterized by.
    [17] The data input / output format conversion circuit according to the present invention further includes a command register for receiving a command and an address from the outside of the semiconductor memory device and outputting the first test mode signal and the second test mode signal according to a combination thereof. . The command register is preferably composed of a mode register set (MRS).
    [18] According to another aspect of the present invention, there is provided a data input / output format conversion method, comprising: enabling a first test mode signal; and during the enable of the first test mode signal, n (n is a natural number) data inputs Accepting n data inputs from a terminal and transmitting data to m (n or more natural numbers) memory cells, enabling a second test mode signal, and enabling the second test mode signal, receiving n data inputs from n data input terminals and transmitting data to the m memory cells, wherein data transmitted to a plurality of neighboring memory cells among the m memory cells is Characterized in that the input from the different input terminal of the n data input terminal.
    [19] The data input / output format converting method according to the present invention may further include receiving a command and an address from the outside of the semiconductor memory device and generating the first test mode signal and the second test mode signal according to a combination thereof. .
    [20] In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.
    [21] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
    [22] 3 is a diagram illustrating a data input / output format conversion circuit according to an embodiment of the present invention.
    [23] Referring to FIG. 3, the data input / output format conversion circuit 30 according to an embodiment of the present invention may include a first transfer circuit 31, a second transfer circuit 32, a mode register set (MRS) 33, NAND gates 34 and 36, and inverters 35 and 37.
    [24] The first transmission circuit 31 is activated when the first test mode signal PBTX2_SS is enabled with a logic " high ", and receives two data inputs from two data input terminals DIN0 and DIN1. Data is transmitted to the cells MC0-MC5. The second transmission circuit 32 is activated when the second test mode signal PBTX2_DS is enabled with a logic " high ", and receives two data inputs from two data input terminals DIN0 and DIN1, thereby providing four memories. Data is transmitted to the cells MC0-MC5. At this time, the signal PCLKM always remains in a logic "high" state.
    [25] In particular, data transmitted to a plurality of neighboring memory cells among the four memory cells MC0-MC5 are input from different input terminals of the two data input terminals DIN0 and DIN1.
    [26] The mode register set (MRS) 33 receives the command COM and the address ADD from the outside of the semiconductor memory device and transmits the first test mode signal PBTX2_SS and the second test mode signal PBTX2_DS according to a combination thereof. Output
    [27] More specifically, the first transmission circuit 31 connects two data input terminals DIN0 and DIN1 and four memory cells MC0-MC5 in response to the enable of the first test mode signal PBTX2_SS. Four switches T1-T4 are included. The switches T1-T4 are composed of CMOS transmission gates.
    [28] The switch T1 connects the data input terminal DIN0 and the memory cell MC0 in response to the enable of the first test mode signal PBTX2_SS. The switch T2 connects the data input terminal DIN1 and the memory cell MC4 in response to the enable of the first test mode signal PBTX2_SS. The switch T3 connects the data input terminal DIN0 and the memory cell MC1 in response to the enable of the first test mode signal PBTX2_SS. The switch T4 connects the data input terminal DIN1 and the memory cell MC5 in response to the enable of the first test mode signal PBTX2_SS.
    [29] In response to the enable of the second test mode signal PBTX2_DS, the second transmission circuit 32 connects four data input terminals DIN0 and DIN1 to four memory cells MC0-MC5. Switches T5-T8. The switches T5-T8 are composed of CMOS transmission gates.
    [30] The switch T5 connects the data input terminal DIN0 and the memory cell MC0 in response to the enable of the second test mode signal PBTX2_DS. The switch T6 connects the data input terminal DIN0 and the memory cell MC4 in response to the enable of the second test mode signal PBTX2_DS. The switch T7 connects the data input terminal DIN1 and the memory cell MC1 in response to the enable of the second test mode signal PBTX2_DS. The switch T8 connects the data input terminal DIN1 and the memory cell MC5 in response to the enable of the second test mode signal PBTX2_DS.
    [31] Table 2 below shows the types of data patterns that can be written in the memory cells MC0-MC5 in the circuit according to the present invention shown in FIG. In the circuit according to the present invention, data of various cases that can be written to the memory cells MC0-MC5 as shown in Table 2 by adjusting the states of the first test mode signal PBTX2_SS and the second test mode signal PBTX2_DS. The pattern can be generated.
    [32] Memory cellDIN0 / DIN1 (PBTX2_SS = 1, PBTX2_DS = 0)DIN0 / DIN1 (PBTX2_SS = 0, PBTX2_DS = 1) 0/00/11/01/10/00/11/01/1 MC000OneOne00OneOne MC100OneOne0One0One MC40One0One00OneOne MC50One0One0One0One
    [33] For example, when PBTX2_SS is logic "1" and PBTX2_DS is logic "0", the switches T1-T4 in the first transmission circuit 31 are turned on and the switches T5-T8 in the second transmission circuit 32 are turned on. Is turned off. Accordingly, the data input terminal DIN0 and the memory cell MC0 are connected, and the data input terminal DIN1 and the memory cell MC4 are connected. In addition, the data input terminal DIN0 and the memory cell MC1 are connected, and the data input terminal DIN1 and the memory cell MC5 are connected. Therefore, according to the four cases applied to the data input terminals DIN0 and DIN1, four data patterns, namely (0,0,0,0), (0,0,1,1), (1,1, 0,0), (1,1,1,1) may be generated.
    [34] When PBTX2_SS is logic "0" and PBTX2_DS is logic "1", the switches T1-T4 in the first transmission circuit 31 are turned off and the switches T5-T8 in the second transmission circuit 32 are turned off. Is turned on. Accordingly, the data input terminal DIN0 and the memory cell MC0 are connected, and the data input terminal DIN0 and the memory cell MC4 are connected. In addition, the data input terminal DIN1 and the memory cell MC1 are connected, and the data input terminal DIN1 and the memory cell MC5 are connected. Therefore, according to the four cases applied to the data input terminals DIN0 and DIN1, four data patterns, namely (0,0,0,0), (0,1,0,1), (1,0, 1,0), (1,1,1,1) may be generated.
    [35] As described above, in the data input / output format conversion circuit according to the present invention, various data patterns in various cases may be generated. In particular, unlike the conventional circuit illustrated in FIG. 2, a data pattern capable of writing different data into two memory cells MC0 and MC1 or two memory cells MC4 and MC5, that is, (0,1,0, It is possible to form 1) or (1,0,1,0).
    [36] Therefore, a defect that has not been conventionally checked, that is, a defect between two adjacent input / output lines, for example, a defect between an input / output line connected to the memory cell MC0 and an input / output line connected to the memory cell MC1 or the memory cell MC4. The defect between the input / output line connected to the I / O line and the input / output line connected to the memory cell MC5 can be checked.
    [37] The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
    [38] As described above, the data input / output format converting circuit has an advantage of generating various data patterns even when the number of data input pins is smaller than the number of memory cells bound to one column selection line. Therefore, various kinds of defects can be checked by the data input / output format conversion circuit according to the present invention.
    权利要求:
    Claims (7)
    [1" claim-type="Currently amended] A first transmission circuit which is activated when the first test mode signal is enabled and receives n data inputs from n (n is natural numbers) data input terminals and transmits data to m (n or more natural numbers) memory cells ; And
    A second transmission circuit which is activated when a second test mode signal is enabled and receives n data inputs from the n data input terminals and transmits data to the m memory cells,
    And data transmitted to a plurality of neighboring memory cells among the m memory cells are input from different input terminals of the n data input terminals.
    [2" claim-type="Currently amended] The method of claim 1,
    And a command register for receiving a command and an address from the outside of the semiconductor memory device and outputting the first test mode signal and the second test mode signal according to a combination thereof. Conversion circuit.
    [3" claim-type="Currently amended] 3. The data input / output format converting circuit of claim 2, wherein the command register is a mode register set (MRS).
    [4" claim-type="Currently amended] The method of claim 1, wherein the first transmission circuit,
    And m switches connecting the n data input terminals and the m memory cells in response to the first test mode signal.
    [5" claim-type="Currently amended] The method of claim 1, wherein the second transmission circuit,
    And m switches connecting the n data input terminals and the m memory cells in response to the second test mode signal.
    [6" claim-type="Currently amended] Enabling the first test mode signal;
    During the enabling of the first test mode signal, receiving n data inputs from n (n is a natural number) data input terminals and transmitting data to m (n or more natural numbers) memory cells;
    Enabling a second test mode signal; And
    During the enabling of the second test mode signal, receiving n data inputs from the n data input terminals and transmitting data to the m memory cells,
    And data transmitted to a plurality of neighboring memory cells among the m memory cells are input from different input terminals of the n data input terminals.
    [7" claim-type="Currently amended] The method of claim 6,
    Receiving a command and an address from an outside of the semiconductor memory device and generating the first test mode signal and the second test mode signal according to a combination thereof. Way.
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    同族专利:
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    KR100464436B1|2004-12-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-11-20|Application filed by 삼성전자주식회사
    2002-11-20|Priority to KR20020072477A
    2004-05-27|Publication of KR20040043994A
    2004-12-31|Application granted
    2004-12-31|Publication of KR100464436B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20020072477A|KR100464436B1|2002-11-20|2002-11-20|Circuit and method for transforming data input output format in parallel bit test|
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