• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The sliding window method in the pipelined Maximum A Posteriori (MAP) decoder structure of the present invention is modified to reduce processing time. Once the forward metric is calculated for the decoder's first sliding window, the backward metric for each window is calculated while the forward metric for the next window is calculated. As each new forward metric is calculated and stored in memory 14, the forward metric from the previous window is read from memory 14 for use with the backward metric calculated in the calculation of the external value. Each forward metric for use in the calculation of the external value is read from memory on the same clock edge where the new forward metric is written to the same memory location. Although such a structure is being developed for the use of a turbo decoder, all convolutional codes can use the MAP algorithm of the present invention.
    公开号:KR20040034699A
    申请号:KR10-2004-7003317
    申请日:2002-04-15
    公开日:2004-04-28
    发明作者:헤플러에드워드엘；스타시닉마이클에프
    申请人:인터디지탈 테크날러지 코포레이션；
    IPC主号:
    专利说明:

    PIPELINE ARCHITECTURE FOR MAXIMUM A POSTERIORI (MAP) DECODERS}
    [2] Some error correction algorithms, such as the Turbo Decoder algorithm, utilize variations of the MAP algorithm to reproduce a sequence of information bits from a code bit sequence corrupted by noise. The repetitive nature of the calculations required by the MAP algorithm is expensive to implement.
    [3] For example, FIG. 1 illustrates the sequence output by the MAP algorithm as a function of Aforward @ metrics set and Abackward @ metrics set. However, each forward metric k is a function of the previous forward metric k-1 and each backward metric k-1 is a function of the next backward metric k. As illustrated in the timeline diagram of FIG. 1, the structure implementing this algorithm is sufficient to hold either all forward metric or all reverse metric so that another set of metrics can be calculated while the output is calculated. It requires a large buffer, and the design leads to a decoder whose latency is approximately twice the block size needed for decoding.
    [4] In an effort to reduce the buffer size required for the MAP algorithm, a modified version of the MAP algorithm called the sliding window algorithm has been developed. By constructing a small approximation in the backward metric calculation, the sliding window algorithm method reduces the size of the required metric buffer. This is accomplished by splitting the received sequence into windows and then processing each window.
    [5] 2 illustrates a timeline of how sliding window calculation is performed when data is divided into two windows. The length of tail and learn size is typically very small compared to the amount of data being processed. While the latency through the decoder does not increase significantly as long as the window size is relatively large compared to the size of the learning window, it is clear that the size of the buffer required to maintain the forward metric is significantly reduced.
    [6] Accordingly, an object of the present invention is to reduce both the waiting time and the costs associated with the implementation of the MAP algorithm.
    [1] TECHNICAL FIELD The present invention relates to the field of error detection and error correction algorithms, and more particularly to the pipelined architecture for processing a Maximum A Posteriori (MAP) algorithm. .
    [8] 1 shows an example of a timeline of an error correction algorithm structure of the prior art.
    [9] 2 shows a second example of a timeline of an error correction algorithm structure of the prior art in which forward and reverse metrics are calculated using a sliding window.
    [10] 3 is a block diagram of a turbo decoder in which the error correction algorithm structure of the present invention may reside.
    [11] 3A is a block diagram of another turbo decoder in which the forward metric calculation and the reverse metric calculation are opposite to each other.
    [12] 4 is a diagram illustrating a timeline of an error correction algorithm structure of the present invention.
    [7] In the pipelined MAP decoder structure of the present invention, the sliding window method is modified to reduce the processing time. Once the forward metric is calculated for the first window, the backward metric for each window is calculated while the forward metric for the next window is calculated. As each new forward metric is calculated and stored in memory, the forward metric from the previous window is read from the memory so that the new backward metric can be calculated. Each forward metric from the previous window is read from memory on the same clock edge where the new forward metric for the next window is written to the same memory location. By reading and writing the forward metric to memory in this manner, the size of the forward metric buffer does not need to be increased. In addition, pipelined calculations may be performed when data is divided into two windows. Although this structure has been developed for the use of turbo decoders, any decoder using a version of the MAP algorithm can be used for the structure. The pipelined sliding window structure reduces processing time. To achieve the same throughput, it is necessary to drive the standard sliding window structure at a fairly high clock speed.
    [13] Hereinafter, with reference to the accompanying drawings will be described in detail the present invention by giving the same reference numerals to the same components.
    [14] 3 of the present invention is a block diagram of a turbo decoder in which the pipelined decoder structure of the present invention may reside. In the pipelined MAP decoder structure of the present invention, the sliding window method is modified to reduce the processing time. 4 shows a timeline achieved by the present invention. Once the forward metric is calculated for the first window, the backward metric for each window is calculated while the forward metric for the next window is calculated. As each new forward metric is calculated and stored in memory, the forward metric from the previous window is read from the memory so that the new backward metric can be calculated. Each forward metric is read from memory on the same clock edge where the new forward metric is written to the same memory location. By reading and writing the forward metric to memory in this manner, the size of the forward metric buffer does not need to be increased.
    [15] 3 shows a block diagram of one embodiment of a turbo decoder incorporating the principles and techniques of the present invention.
    [16] The turbo decoder 10 may for example set each data bit A1 @ or A0 @ to three bits, namely data or system bits s, first parity bits p1 and second parity bits p2 [ Hereinafter, data is received from a transmission facility such as a base station (BS) which converts to sp1p2. The sp1p2 data is applied to the memory register 12, which is obtained from the interleaved address generator 16 and the extrinsic data read from the extrinsic memory 14, which will be described in more detail below. Receive the address. Therefore, the memory register 12 initially receives and stores sp1p2 data, external data extrin_data_out shown in line 14a, and address extrin_read_addr. In which external data shown in line 16a is located. The address is accompanied by the sp1p2 data through calculation for the purpose of explaining in more detail below.
    [17] The splp2 data is transferred from the memory register 12 to the gamma () calculator 18 and further stored in the local memory 20.
    [18] As in a conventional turbo decoder, three quantities are defined: alpha. (), Beta. () And gamma. (). For a particular state and a particular time step, it has a value that defines the probability that the turbo decoder is in that particular state or at that particular time step. Alpha derives inductive initiation and forward movement within time from time k = 1. The values are similar but move backwards in time. Gamma. () Is defined as the transition probability that the turbo decoder can move from the state of a given time to some allowed state of the next subsequent time increment. Alpha. () Can be calculated for all states with Trellis based on the state transition probability indicated by gamma. Gamma () The gamma () calculation executed in the calculator 18 is stored in the register 22. Computation stages 24 and 26 respectively calculate each alpha and normalize the alpha calculation. Each alpha. () Value is calculated based on the input from register 22 as well as the previous calculated alpha value provided to input 24b, so that the multiplexer (8) maintains eight calculated values from calculation 26. 28) and through the register 30. The output of the register 30 is coupled to an input of the alpha memory 32 that stores the first calculated alpha value at the first memory location 23a and provides the calculated alpha value to the input terminal 24b.
    [19] In order to initialize the calculation and start operation in its initial state, the initial eight alpha metrics are initialized input stage 28a of the multiplexer 28 to calculate eight alpha values at the computation stages 24, 26. It is set to some initial value applied to. As described above, the sp1p2 data is stored in the local memory 20.
    [20] Initially, once all alpha values are calculated, the beta values are reverse ordered from local memory 20 (ie, A last-in, first-out) to perform the calculations needed for the reverse general formula for beta. Calculated by the use of sp1p2 data which is read in order @]. The final read of local memory 20 as the sp1p2 data is read into register 34, which registers not only the sp1p2 data but also an external value (zero for an initial short operation) and its initial external value. It includes data indicative of a memory location located in the exogenous memory 14. The external data, which is the sp1p2 data, is calculated by the gamma calculation stage 36. The output of gamma calculation stage 36 is applied to gamma registers 38 and 40. Beta calculation is performed by the beta calculation stage 44 and the beta normalization stage 46, respectively. Initially, the starting condition of binary one (A1 @) is applied to input terminal 42a of multiplexer 42. The standardized beta calculation is initially applied to the external value calculation stage 50 via an output register 48 which further applies the final calculated input to the input stage 42b of the multiplexer 42. The external value calculating stage 50 is configured with an alpha value for the register 52 received at the input 58, a gamma value from the register 38 received at the input 50b, and a register 48 received at the input 50c. Calculate the external value for each time state k by examining the beta values from. Registers 48, 52, 38 are provided to ensure time registration of the signal at the external value calculating stage 50.
    [21] The median value calculated by the first external value calculating stage 50 is applied to a register 54 which conveys the contents to the second external value calculating stage 56 of the external value calculator.
    [22] As described above, register 34 transfers its contents to register 58, which register 58 transfers its contents to register 60, the contents of register 60 being a second external value. Subtracted from the external value represented by the output of the calculation stage 56, this subtraction stage is carried out in the subtraction circuit 62.
    [23] The external value obtained at the second external value calculating stage 56 is a soft-in-hard-out (SIHO) configured with a binary state determination circuit 64 which receives the output of the second external value calculating stage 56. Is further applied to the circuit 64. The operation of circuit 66 in SIHO circuit 64 will be described in more detail below.
    [24] The difference value output from the difference circuit 62 is applied to the register 68, which registers the external value calculation as external data 14b (i.e., extrin_data_in) of the extrinsic memory 14. Is authorized. As mentioned above, in addition to storing data, parity and external values, local memory 20 further stores a first external value address of exogenous memory 14, which addresses memory register 34 and external values. Successively coupled through time synchronization registers 70, 72, and 74 providing the location of the exogenous memory 14 in which the calculation is stored, the memory location data being applied as external data 14b of the exogenous memory 14. .
    [25] As described below with reference to the example shown in FIG. 2, half of the calculation for determining alpha is performed for a period of the first time window k / 2.
    [26] The calculation of the backward metric () is performed for the last half (k / 2) of the first window. Alpha values are read from alpha memory 32 in the reverse order in which they are stored. The alpha value calculated during the period of the forward metric (see FIG. 4) for window 2 is simultaneously stored in a memory location where the alpha value calculated during the period of window 1 is read for the purpose of calculating an external value, thereby providing In an embodiment the memory capacity is reduced by one half. Note that the newly calculated alpha values are stored in the reverse order of the calculated order for the duration of the first window.
    [27] For each subsequent pair of window calculations, the number of calculations performed is a number of desired iteration functions for calculating the external values, and the order of reading and writing the alpha values in the alpha memory 32 is inverted from each other, so as to calculate previously. The calculated alpha value is read in the order of storage of the first memory location from the last memory location, the alpha value is read in the reverse order of the last memory location from the first memory location, and the alpha value is obtained from the second iteration of the forward metric. Determined in window 2, the new values calculated in calculation stages 24 and 26 are read at the same position where the alpha value is read.
    [28] As described above, when the external value is calculated, i.e., when the first iteration is completed, this external value is read from the extrinsic memory 14 and used during the calculation of the next iteration. Conventional control circuits, not shown for the purpose of streamlining the description, determine the number of iterations performed.
    [29] As discussed above, as each external value is determined, each external value is applied to circuitry 66 that determines whether each data bit is A1 @ or A0 @ by examining its amplitude, where it is above a certain threshold. In the case of A1 @, it is determined to be A1 @. The value thus achieved is applied to register 76, merged with an external value memory location derived from register 74, and applied to merge circuit 78. The output bit is written to memory 84. The SIHO circuit 64 writes each bit into a memory location where each row is 16 bits wide. Merging circuit multiplexer 78, multiplexer circuit 80, and output memory read register 82 store 16 data bits evaluated by binary state determination circuit 66 to utilize the entire 16 binary bits of each memory location. To work.
    [30] Although the embodiment shown in FIG. 3 discloses an embodiment in which alpha is calculated for the first window period and beta is calculated for the second half of the first window period, the alpha calculation and the beta calculation are performed in the implementation shown in FIG. 1. As long as it still leads to the overall benefits for the example, i.e. it can lead to a significant reduction in computation time as well as a 50% reduction in the memory requirements for the turbo decoder of FIG. It can be understood that they can be reversed from each other as shown. The structure of the present invention enables further reduction of memory size. For example, processing data using three windows, four windows, or the like, can provide an additional reduction in memory size. For example, using four windows results in a memory size of three compared to a process that does not use windows.
    [31] 4 shows how pipeline calculations are performed when data is divided into two windows. Ignoring the size of the learning window and the number of tail bits, the latency through the pipelined sliding window decoder in this example is proportional to 12 K as opposed to 2 K in a simple sliding window structure. The waiting time can be reduced by changing the window size, the number of windows and the learning size according to the amount of data required for processing.
    [32] Although the structure described above is being developed for the use of a turbo decoder, all convolutional codes can use a MAP decoder. The calculation of the forward metric can be calculated before and after the reverse metric. The backward metric may be calculated first, and then the forward metric may be calculated while the output calculation is performed. This can be accomplished, for example, as shown by the embodiment of FIG. 3A, where calculation block 24 1 is a beta calculator; Computation block 24 is a beta standardization computation block, memory 32 1 is beta memory; Calculation block 44 1 is an alpha calculation block, and calculation block 46 1 is an alpha normalization calculation block.
    [33] In other respects with respect to the operation of the embodiment of FIG. 3A, the operation is substantially the same as that of the embodiment of FIG.
    权利要求:
    Claims (39)
    [1" claim-type="Currently amended] A method of determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for the execution of an output calculation,
    (a) performing said forward metric calculation in two stages, wherein the first group of forward metric calculations is calculated in a first stage followed by a second group of forward metric calculations calculated in a second stage; Performing forward metric calculations;
    (b) reading the forward metric calculated during the first stage period from memory using a reverse metric value to perform an output calculation;
    (c) performing said reverse metric calculation in a first stage subsequent to a second stage;
    (d) performing a second half of forward metric calculation as said reverse metric calculation is performed;
    (e) storing each of said forward metric calculations performed in a first stage;
    (f) writing each forward metric calculated for the duration of the second stage into a memory location where the forward metric calculated for the duration of the first stage is read for use in calculating the output.
    State determination method comprising a.
    [2" claim-type="Currently amended] 2. The method of claim 1, further comprising performing output calculations using the forward metric calculated at the first stage and the backward metric calculated at the second stage.
    [3" claim-type="Currently amended] The method of claim 1, wherein steps (e) and (f) are performed using a common clock edge of the clock signal.
    [4" claim-type="Currently amended] 3. The method of claim 2, wherein a backward metric is performed in a third stage following the second stage to use the forward metric calculated in the second stage, and the forward metric and the third stage calculated during the duration of the second stage. And performing an output calculation using the reverse metric calculated for a period of time.
    [5" claim-type="Currently amended] A method of decoding a transmission received from a remote location that includes data bits and associated parity bits and that may be damaged by noise in a transmission channel, the method comprising:
    (a) during the first time interval, calculating a forward metric value for each data bit received from the transmission location and a parity bit in accordance with the data bit;
    (b) storing each forward metric value in a first memory;
    (c) storing each received data bit and a parity bit in accordance with the data bit in a local memory in which the bits are received;
    (d) reading a forward metric value from said first memory for a second time interval to calculate an external value;
    (e) calculating a backward metric value during said second time interval using said data bits and associated parity bits previously stored in memory;
    (f) during the second time interval, calculate forward metric values for data bits and associated parity bits received during the second time interval, and calculate each forward metric value calculated during the second time interval, wherein ( storing in the memory location at which the forward metric value is read during step d).
    Decoding method comprising a.
    [6" claim-type="Currently amended] 6. The decoding method according to claim 5, wherein during the step (c), the reading of the data bits and the associated parity bits into the local memory is read out from the local memory in the reverse order used in calculating the backward metric.
    [7" claim-type="Currently amended] 6. The decoding method according to claim 5, wherein the calculated forward metric value is read from the memory in the reverse order in which the forward metric value is read into the memory used in the calculation of the external value.
    [8" claim-type="Currently amended] 6. The method of claim 5 wherein step (a) further comprises performing a gamma calculation on the data bits and associated parity bits before calculating a forward metric value for a first time interval.
    [9" claim-type="Currently amended] 6. The method of claim 5, further comprising calculating an initial external value based on a predetermined forward metric value, a predetermined reverse metric value, and a parity bit associated with a predetermined data bit.
    [10" claim-type="Currently amended] 10. The method of claim 9, wherein said external value is stored in an exogenous memory.
    [11" claim-type="Currently amended] The method of claim 9, wherein storing the external value comprises:
    Storing the internal value in a memory location associated with the data bits used to calculate the stored external value.
    [12" claim-type="Currently amended] 11. The method of claim 10, further comprising: extracting the data bits and associated parity bits from local memory;
    Performing a gamma calculation on the data bits and the associated parity bits during a second time interval for use in calculating the external value.
    [13" claim-type="Currently amended] 13. The method of claim 12, further comprising subtracting data bits and associated parity bits read from the local memory for a second time interval from the initial external value to obtain a final external value.
    [14" claim-type="Currently amended] 13. The method of claim 12, further comprising: determining a binary state of output data of an external value calculator to form a hard decision related to the binary state;
    And storing the hard decision output in a memory.
    [15" claim-type="Currently amended] A method of manipulating a turbo decoder that receives data bits, each of which may be corrupted and accompanied by an associated parity bit,
    (a) performing forward metric calculations at two successive time intervals, wherein one group of forward metric calculations is calculated at a first time interval followed by a second time interval. Wow;
    (b) storing each of the forward metric calculations performed during the first time interval;
    (c) reading each forward metric value calculated during the first time interval from the memory for use with the reverse metric value in the calculation of the external value;
    (d) performing a reverse metric calculation during the second time interval and after completion of the forward metric calculation performed during the first time interval;
    (e) writing each forward metric value calculated during the second time interval into a memory location where the forward metric value calculated during the first time interval is read from memory.
    Turbo decoder operation method comprising a.
    [16" claim-type="Currently amended] A turbo decoder for determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for carrying out a calculation,
    (a) creating a memory location in the exogenous memory;
    (b) receiving a signal comprising data bits and associated parity bits that may be corrupted by noise or the like;
    (c) storing the data bits, associated parity bits, memory location and starting external value;
    (d) calculating a first set of forward metric values based on the data bits, associated parity bits and starting external values;
    (e) storing the calculated forward metric value in a forward metric memory;
    (f) reading the calculated forward metric value from memory using together with a reverse metric value in the calculation of the external value;
    (g) calculating a second set of forward metric values while said backward metric values are calculated using steps (a) and (c);
    (h) storing each of the second set of forward metric values in the same memory location where one of the first set of forward metric values is read for use in calculating the reverse metric value.
    State determination turbo decoder comprising a.
    [17" claim-type="Currently amended] 17. The method of claim 16, further comprising reading the forward metric values in memory in the reverse order in which they are read from the memory upon calculation of reverse metric values.
    [18" claim-type="Currently amended] A turbo decoder for determining a binary state of a received signal by calculating a forward metric (α) and a reverse metric (β) necessary for carrying out a calculation,
    (a) receiving a signal comprising data bits each having an associated parity bit in which the signal may be corrupted by noise or the like;
    (b) creating a memory location in the exogenous memory to store the external value;
    (c) storing the first data bit, the associated parity bit, the memory location and the starting external value in the first memory;
    (d) calculating a first forward metric value based on the data bits, the associated parity bits, and a starting external value;
    (e) storing the calculated forward metric value in a forward metric memory;
    (f) reading the calculated forward metric value from forward metric memory for use with a backward metric value in the calculation of the external value;
    (g) calculating a first forward metric value of a second set of forward metric values while said backward metric value is calculated using steps (a) and (c);
    (h) storing the first forward metric value of the second set of forward metric values in the same memory location where one of the first set of forward metric values is read for use in calculating an external value.
    State determination turbo decoder comprising a.
    [19" claim-type="Currently amended] A turbo decoder for determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for carrying out a calculation,
    Exogenous memory;
    First means for creating a memory location in the exogenous memory;
    Second means for receiving a signal comprising data bits each having an associated parity bit that may be damaged by noise or the like;
    Third means for storing the data bits, the associated parity bits and a memory location;
    Fourth means for calculating a first set of forward metric values based on the data bits, the associated parity bits, and an initial starting external value;
    Fifth means for storing the calculated forward metric value in a forward metric memory;
    Sixth means for reading the calculated forward metric value from the forward metric memory for use with a reverse metric value in the calculation of the external value
    Including,
    The first means, second means and third means calculate a second set of forward metric values while the reverse metric value is calculated;
    The fifth means stores one of the second set of forward metric values in the same memory location of the forward metric memory as one of the first set of forward metric values is read for use in the calculation of an external value. Means for determining the state of the turbo decoder.
    [20" claim-type="Currently amended] A storage technique for use in a turbo decoder that calculates a forward metric and a reverse metric necessary for carrying out a calculation to determine a binary state of a received signal,
    (a) storing the first group of forward metric values in a predetermined order in memory;
    (b) reading the stored forward metric values in order of the first calculated value from the last calculated value;
    (c) storing the second group of forward metric values in memory in a predetermined order;
    Including,
    And wherein the first calculated forward metric value of the second group is stored in a memory location from which the last calculated metric value of the second group is read.
    [21" claim-type="Currently amended] 21. The storage technique of claim 20, further comprising calculating a backward metric value based on the forward metric value read from memory.
    [22" claim-type="Currently amended] An apparatus for use in a turbo decoder for determining the binary state of a received signal by calculating a forward metric and a reverse metric required for carrying out the calculation,
    A first memory for storing data bits and associated parity bits;
    Forward metric memory;
    Means for calculating a first group of forward metric values based on the data bits and associated parity bits;
    Means for storing the first group of forward metric values in a predetermined order in memory;
    Means for reading a first group of stored metric values from the memory in order of the first calculated value from the last calculated value;
    Means for controlling said calculating means for calculating a second group of forward metric values following the calculation of the first group of metric values;
    Means for storing the second group of forward metric values in the forward metric memory in a predetermined order
    Including,
    The first calculated forward metric value of the second group is stored in a memory location from which the last calculated metric value of the first group is read.
    [23" claim-type="Currently amended] 23. The turbo decoder of claim 22, further comprising second means for calculating a reverse metric value based on data bits read from the first memory and associated parity bits during calculation of the first group of forward metric values. Device for
    [24" claim-type="Currently amended] A method of determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for the execution of an output calculation,
    (a) performing said reverse metric calculation in two stages, wherein one group of reverse metric calculations is calculated in a first stage followed by a second group of reverse metric calculations calculated in a second stage; Performing a reverse metric calculation;
    (b) storing each of said reverse metric calculations performed in a first stage;
    (c) reading the reverse metric value calculated during the first stage period from memory for use in calculating the output;
    (d) performing the forward metric calculation after completion of the first stage of the backward metric calculation and before the second stage of the reverse metric calculation;
    (e) writing each reverse metric calculated for the duration of the second stage into a memory location where the reverse metric calculated for the duration of the first stage is read for use in calculating the output.
    State determination method comprising a.
    [25" claim-type="Currently amended] 25. The method of claim 24, further comprising performing output calculations using the backward metric calculated in the first stage and the forward metric calculated in the second stage.
    [26" claim-type="Currently amended] 25. The method of claim 24 wherein steps (c) and (e) are performed using a common clock edge of the clock signal.
    [27" claim-type="Currently amended] 26. The method of claim 25, further comprising: performing a forward metric at a third stage, subsequent to the second metric, in response to a reverse metric calculated at the second stage;
    And performing output calculation using a reverse metric value calculated during the second stage period and a forward metric value calculated during the third stage period.
    [28" claim-type="Currently amended] A method of decoding a transmission received from a remote location that includes data bits and associated parity bits and that may be damaged by noise in a transmission channel, the method comprising:
    (a) during the first time interval, calculating a reverse metric value for each data bit received from the transmission location and a parity bit in accordance with the data bit;
    (b) storing each reverse metric value in a first memory;
    (c) storing each received data bit and a parity bit in accordance with the data bit in a local memory in which the bits are received;
    (d) reading a backward metric value from said first memory for use in calculating an external value;
    (e) calculating a forward metric value using said data bits and associated parity bits previously stored in local memory;
    (f) during the second time interval, calculate reverse metric values for data bits and associated parity bits received during the second time interval, and calculate each reverse metric value calculated during the second time interval, wherein ( d) storing a reverse metric value in a memory location of said first memory during said period of step d).
    Decoding method comprising a.
    [29" claim-type="Currently amended] 29. The decoding method according to claim 28, wherein during the step (c), the reading of the data bits and the associated parity bits into the local memory is read out from the local memory in the reverse order used in calculating the external value.
    [30" claim-type="Currently amended] 30. The method of claim 29 wherein the reverse metric value calculated in the first time interval is read from the memory in the reverse order in which the reverse metric value calculated in the second time interval is read into the memory.
    [31" claim-type="Currently amended] 30. The method of claim 29, further comprising calculating an external value based on a predetermined forward metric value, a predetermined reverse metric value, and a parity bit associated with the predetermined data bit.
    [32" claim-type="Currently amended] A method of determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for carrying out a calculation,
    (a) performing a first group of forward metric calculations for a period of the first stage;
    (b) storing a first group of forward metric values in memory;
    (c) performing a reverse metric calculation for the duration of the second stage following the first stage;
    (d) performing a second group of forward metric calculations as a reverse metric value is calculated for the duration of the second stage;
    (e) performing calculations to determine the binary state of the received signal by reading the forward metric values of the first group at locations in memory for use with the reverse metric values calculated during the second stage period. Steps;
    (f) storing a calculation of a second group of forward metric values for a time period during which the reverse metric values are calculated in a second stage.
    Including,
    Each forward metric value calculated during the period of the second stage is read for use in the execution of the calculation to determine a binary state of the received signal during the period of the first stage. A state determination method characterized in that it is stored in the same location.
    [33" claim-type="Currently amended] An apparatus for determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for the execution of an output calculation,
    Performing said reverse metric calculation in two stages, wherein one group of reverse metric calculations is calculated in a first stage followed by a second group of reverse metric calculations calculated in a second stage Means for implementing;
    Means for storing each of said reverse metric calculations performed in a first stage;
    Means for reading the reverse metric value calculated during the first stage period from memory for use in output calculation;
    Means for performing the forward metric calculation after completion of the first stage of backward metric calculation and before the second stage of reverse metric calculation;
    Means for writing each reverse metric calculated for the duration of the second stage into a memory location where the reverse metric calculated for the duration of the first stage is read for use in calculating the output.
    State determination device comprising a.
    [34" claim-type="Currently amended] 34. The apparatus of claim 33, further comprising means for performing output calculation using the backward metric calculated in the first stage and the forward metric calculated in the second stage.
    [35" claim-type="Currently amended] 34. The apparatus of claim 33, further comprising: means for executing a forward metric at the third stage following the second metric in response to a reverse metric calculated at the second stage;
    And means for performing output calculation using a backward metric value calculated during the second stage period and a forward metric value calculated during the third stage period.
    [36" claim-type="Currently amended] An apparatus for decoding a transmission received from a remote location that includes data bits and associated parity bits and that may be damaged by noise in a transmission channel, the apparatus comprising:
    Means for calculating a reverse metric value for each data bit received from the transmission location and a parity bit in accordance with the data bit during the first time interval;
    A first memory for storing each reverse metric value;
    A local memory for storing each received data bit and a parity bit in accordance with the data bit;
    Means for reading a backward metric value from said first memory for use in calculating an external value;
    Means for calculating a forward metric value using said data bits and associated parity bits previously stored in local memory;
    During the second time interval, calculating backward metric values for data bits and associated parity bits received during the second time interval, and for each reverse metric value calculated during the second time interval, step (d) Means for storing a reverse metric value in a memory location of said first memory for which a period of time is read
    Decryption apparatus comprising a.
    [37" claim-type="Currently amended] 37. The decoding apparatus according to claim 36, further comprising means for reading out said local data and said parity bits from said local memory in a local memory in reverse order for use by said read-only means in calculating said external value.
    [38" claim-type="Currently amended] 38. The apparatus of claim 37, further comprising means for calculating an external value based on a predetermined forward metric value, a predetermined reverse metric value, and a parity bit associated with the predetermined data bit.
    [39" claim-type="Currently amended] An apparatus for determining a binary state of a received signal by calculating a forward metric and a reverse metric necessary for carrying out a calculation,
    Means for performing a first group of forward metric calculations for a period of the first stage;
    Memory means for storing a first group of forward metric values;
    Means for performing a reverse metric calculation for the duration of the second stage following the first stage;
    Means for performing a second group of forward metric calculations as a reverse metric value is calculated for the duration of the second stage;
    Means for reading the first metric forward metric value of the first group at a location in memory for use with the reverse metric value calculated during the second stage period and performing a calculation to determine a binary state of the received signal;
    Means for storing a calculation of a second group of forward metric values for a time period during which the reverse metric values are calculated in a second stage.
    Including,
    Each forward metric value calculated during the period of the second stage is read for use in the execution of the calculation to determine a binary state of the received signal during the period of the first stage. A state determining device, characterized in that stored in the same position.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-09-06|Priority to US31785501P
    2001-09-06|Priority to US60/317,855
    2002-01-02|Priority to US10/037,609
    2002-01-02|Priority to US10/037,609
    2002-04-15|Application filed by 인터디지탈 테크날러지 코포레이션
    2002-04-15|Priority to PCT/US2002/011664
    2004-04-28|Publication of KR20040034699A
    2006-05-22|Application granted
    2006-05-22|Publication of KR100582051B1
    优先权:
    申请号 | 申请日 | 专利标题
    US31785501P| true| 2001-09-06|2001-09-06|
    US60/317,855|2001-09-06|
    US10/037,609|US6961921B2|2001-09-06|2002-01-02|Pipeline architecture for maximum a posterioridecoders|
    US10/037,609|2002-01-02|
    PCT/US2002/011664|WO2003023709A1|2001-09-06|2002-04-15|Pipeline architecture for maximum a posterioridecoders|
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