• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention provides a stack structured semiconductor device that achieves a smaller size and a smaller size, and a semiconductor device that realizes high performance and high reliability in addition to the smaller size of its external size. Bonding leads provided correspondingly to bonding pads for address and data divided into opposing first and second sides of the memory chip, and a package substrate having address terminals and data terminals connected to the bonding leads, respectively. And an address output circuit and a data input / output circuit, which are also used for memory access, and a signal processing circuit having a data processing function, a bonding pad connected to a bonding lead corresponding to an address terminal of the package substrate, and a bonding corresponding to a data terminal. Bonding pads connected to the leads are mounted in a stacked structure with the semiconductor chip and the memory chip arranged in two of four sides.
    公开号:KR20040023493A
    申请号:KR1020030050878
    申请日:2003-07-24
    公开日:2004-03-18
    发明作者:미와타카시；츠츠미야수미；이치타니마사히로；하시즈메타카노리；사토마사미치；모리노나오즈미；나카무라아츠시；다마키사네아키；구도이쿠오
    申请人:가부시키가이샤 히타치세이사쿠쇼；
    IPC主号:
    专利说明:

    Semiconductor device {A SEMICONDUCTOR DEVICE}
    [49] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and for example, to a useful technique used for semiconductor devices in which a plurality of semiconductor chips are mounted in a stacked structure on a package substrate.
    [50] Stacked LSIs (large-scale integrated circuits) formed by assembling semiconductor chips on a package substrate in a stacked structure are often combined with existing semiconductor chips, and a common signal and wiring / ground are commonly connected by wiring of a package. All. After the present invention, the existence of the Japanese Unexamined Patent Application Publication No. 2000-43531 has been reported by the known example investigation as related to the present invention. However, the technique described in the publication relates to the reduction of time and effort required to develop a model design of a stacked package LSI, and lacks consideration regarding the size reduction and thickness of the package substrate as described below. It is.
    [51] Since common pads and power / ground in the two chips constituting the stacked package LSI do not necessarily have pads placed in a place where they are easily connected between the chips, even when wiring is carried out on a package board, cross wiring is performed. In many cases, the wiring is extremely dense, and the number of wiring layers of the package substrate increases, or the external size becomes large, which impedes miniaturization. Since the connection terminals of the chip to be mounted are also provided separately, a large terminal array area is required, which also increases the package outline size.
    [52] 19 to 21 show examples of stacked package LSIs examined prior to the present invention. Microcomputer LSI and memory LSI are each composed of conventional semiconductor chips. 19 shows each of the microcomputer LSI, memory LSI, and package substrate constituting the stacked package LSI. Microcomputer LSI and memory LSI are each composed of conventional semiconductor chips. Fig. 20 shows the appearance after bonding the memory LSI and the microcomputer LSI onto the substrate and bonding them together, and Fig. 21 shows a sectional view.
    [53] As shown in Fig. 19 to Fig. 21, the stacked package LSI die bonds the memory LSI onto a package substrate made of glass epoxy, and then die bonds the microcomputer LSIs to overlap each other, and wire-bonds between each chip and the substrate. After that, the mold is made of resin, and the back terminal portion is structured with solder balls.
    [54] In Fig. 19, the microcomputer LSI intensively arranges address terminals and data terminals for connection with a memory and the like on adjacent sides. In this configuration, when the microcomputer LSI, the memory LSI, and the like are planarly mounted, the address bus and the data bus can be arranged in the shortest distance and intensively from the mounting substrate toward the memory. On the other hand, in the memory LSI, corresponding to the terminal number itself and the external terminal arrangement of the standard package, an address terminal is mainly disposed on one side, and a data terminal is disposed on the other side opposite to this.
    [55] When the microcomputer LSI and the memory LSI in which the above bonding pads are arranged are stacked, for example, when the directions of the address terminals of the microcomputer LSI and the memory LSI coincide with each other, the directions of the data terminals do not coincide. Wiring extension for this is necessary. In addition, since the pitches of the arrangement of the bonding pads do not coincide with each other in the microcomputer LSI and the memory LSI, in some cases, the terminals must be provided independently.
    [56] As a result, in the package substrate, the number of bonding terminals (bonding leads) increases, so that the bonding leads cannot be arranged in one column, and it is necessary to arrange them in two rows as in the example of FIG. For this reason, there exists a problem that the external size of a package board | substrate also becomes large. In addition, depending on the arrangement of the terminals to be interconnected in the microcomputer LSI and the memory LSI, the wiring on the package substrate crosses, and it is necessary to form a multilayer wiring board, which also causes problems such as thickening of the external dimensions. Will be.
    [57] SUMMARY OF THE INVENTION An object of the present invention is to provide a stacked structure semiconductor device which realizes miniaturization and thinning of an external size. Another object of the present invention is to provide a semiconductor device that realizes high performance and high reliability in addition to miniaturization of an external size. The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.
    [1] 1 is a configuration diagram of a microcomputer LSI, a memory LSI, and a package substrate for explaining an embodiment of a stacked package LSI according to the present invention;
    [2] FIG. 2 is an external view after bonding the memory LSI and the microcomputer LSI on the substrate of FIG.
    [3] 3 is a cross-sectional view of one embodiment of the stacked package LSI shown in FIG. 2;
    [4] 4 is a top view showing another embodiment of a package substrate used in the present invention;
    [5] 5 is a top view showing an embodiment of a package substrate used in the present invention;
    [6] FIG. 6 is an external view after bonding the memory LSI and the microcomputer LSI on the substrate of FIG.
    [7] 7 is a top view showing another embodiment of a package substrate used in the present invention;
    [8] FIG. 8 is an external view after bonding the memory LSI and the microcomputer LSI on the substrate of FIG.
    [9] 9 is a top view showing another embodiment of a package substrate used in the present invention;
    [10] Fig. 10 is an external view after bonding the memory LSI and the microcomputer LSI on the substrate of Fig. 9 and then performing bonding;
    [11] 11 is a partial external view showing another embodiment of the semiconductor device according to the present invention;
    [12] 12 is a partial external view showing another embodiment of the semiconductor device according to the present invention;
    [13] 13 is a partial external view showing another embodiment of the semiconductor device according to the present invention;
    [14] 14 is a block diagram showing one embodiment of a microcomputer LSI used in the present invention;
    [15] FIG. 15 is a schematic pin layout view showing one embodiment of the microcomputer LSI of FIG. 14; FIG.
    [16] Fig. 16 is an external view after bonding after mounting a memory LSI and a microcomputer LSI on a substrate which is one embodiment of a semiconductor device according to the present invention;
    [17] 17 is an enlarged view of a portion of FIG. 16;
    [18] FIG. 18 is a top view showing an embodiment of a package substrate used in the semiconductor device of FIG. 16; FIG.
    [19] 19 is a block diagram of a microcomputer LSI, a memory LSI, and a package substrate for explaining an embodiment of the stacked package LSI discussed before the present invention;
    [20] 20 is an external view after bonding the memory LSI and the microcomputer LSI on the substrate of FIG. 19 and then performing bonding;
    [21] FIG. 21 is a sectional view of the stacked package LSI shown in FIG. 20. FIG.
    [22] (Explanation of the sign)
    [23] CPU Central Processing Unit
    [24] DSP Data Signal Processor (DSP)
    [25] XYMEM memory
    [26] XYCNT memory controller
    [27] CACHE Cache Memory
    [28] CCN Cache Memory Controller
    [29] MMU Memory Management Controller
    [30] TLB Translation Look-Aside Buffer
    [31] INTC Interrupt Controller
    [32] CPG / WDT Clock Oscillators / Watchdog Timers
    [33] VIO Video I / O Module
    [34] UBC User Brake Controller
    [35] AUD Advanced User Debugger
    [36] TMU Timer Unit
    [37] CMT COMPARE MATCH TIMER
    [38] SIOF0 Serial I / O with FIFO
    [39] SCIF1FIFO built-in serial communication interface
    [40] I 2 CI 2 C Controller
    [41] MFI Multifunction Interface
    [42] FLCTLNAND / AND flush interface
    [43] H-UDI user debug interface
    [44] ASERAMASE memory
    [45] PFC Memory Pin Function Controller
    [46] RWDTRCLK Operation Watchdog Timer
    [47] BSC Bus State Controller
    [48] DMAC Direct Memory Access Controller
    [58] The outline of a representative of the inventions disclosed herein will be briefly described as follows. Bonding leads provided in correspondence with the bonding pads for address and data divided into the first and second sides of the memory chip facing each other, and a package substrate having address terminals and data terminals connected to the bonding leads are used. And an address output circuit and a data input / output circuit, which are also used for memory access, and a signal processing circuit having a data processing function, and corresponding to a bonding pad and a data terminal connected to a bonding lead corresponding to an address terminal of the package substrate. Bonding pads connected to the bonding leads are mounted in a stacked structure with the semiconductor chip and the memory chip arranged in two of four sides.
    [59] 1 to 3 show a schematic diagram of an embodiment of a stacked package LSI according to the present invention. Fig. 1 shows each of the microcomputer LSI, the memory LSI, and the package substrate constituting the stacked package LSI, and Fig. 2 shows the appearance after bonding the memory LSI and the microcomputer LSI on the substrate and bonding them. 3, a cross section is shown. As shown in Figs. 1 to 3, the stacked package LSI of this embodiment die-bonds a microcomputer LSI after die bonding a memory LSI onto a package substrate made of glass epoxy, and between each chip and the substrate. After wire bonding, the mold is molded with a resin, and the rear terminal portion has a structure in which a solder ball is attached.
    [60] In Fig. 1, the memory LSI is composed of a conventional semiconductor chip, whereas the microcomputer LSI is arranged in a bonding pad corresponding to the memory LSI combined therewith. The microcomputer LSI constitutes a so-called application-specific integrated circuit (ASIC), that is, a specific use IC. In a semiconductor integrated circuit device, a plurality of circuit blocks centered on a CPU (central processing unit) are mounted so that the ASIC configuration is easy, and each circuit block forms a so-called module or macrocell as an independent circuit functional unit. Each functional unit can be changed in scale. The arrangement of the bonding pads of the microcomputer LSI corresponding to the combination with the memory LSI as described above is made at the time of the layout design of the functional blocks corresponding to the combination of the functional units.
    [61] In the package substrate (wiring substrate), the arrangement of the bonding leads (wire connection portions) is set corresponding to the arrangement of the bonding pads between the microcomputer LSI and the memory LSI. The package substrate may be formed of, for example, a base substrate of a glass / epoxy clock, a plurality of copper wirings formed on upper and lower surfaces thereof, and portions other than the wire connection portion and the external terminal connection portion (bumpland). And an insulating film (solder resist film) covering the surface of the copper wiring, and through-hole wiring for connecting a plurality of copper wirings formed on the upper and lower surfaces thereof with each other.
    [62] The memory LSI is not particularly limited, but is a static RAM having a storage capacity of about 8 M bits. The semiconductor LSI has a rectangular shape, and is divided into addresses and data on the short side, and bonding pads are provided. Compared with such a memory LSI, the microcomputer LSI is almost square in shape of a chip and has a smaller external size than the memory LSI. Therefore, after die-bonding the memory LSIs on the package substrate as described above, the microcomputer LSIs are overlapped and die-bonded, and wire bonding is performed between each chip and the substrate.
    [63] The package substrate secures the largest area with respect to the outer circumference in a substantially square shape in order to reduce the external dimension. In this case, since there is no area margin on the short side of the memory LSI, a bonding lead shown in a rectangle is arranged along the outer circumference thereof, and the lead-out direction of the wiring reaching the through hole is directed toward the inside of the package substrate. As for the bonding lead corresponding to the address and data, a through hole corresponding thereto is arranged inside the substrate. On the other hand, since there is an area margin on the long side of the memory LSI, the through holes are alternately arranged on both sides so as to sandwich the bonding leads.
    [64] As described above, the microcomputer LSI is arranged concentrated on the sides facing the address terminal and the data terminal. Terminals not contributing to the connection with the memory LSI are mainly disposed on the sides other than this. As a result, even when stacked with the memory LSI, the directions of the interconnected terminals do not coincide with each other. In addition, in the case of lamination and bonding, the microcomputer LSI is merged with the terminals of the memory LSI to adjust the pitch so that the wires do not cross complicatedly. That is, when the wires cross intricately, for example, when the wires overlap each other in the longitudinal direction as shown in Fig. 21, and when the wires are removed as two wires as shown in Fig. 3, the mold (resin sealing body) ) Can be thinned.
    [65] The pitch can be adjusted simply by adjusting the spacing. In this embodiment, the pitch is adjusted by arranging terminals having other functions in the address or data terminal columns. Since the pitch adjustment is performed in this manner, the terminals to be connected between the microcomputer LSI and the memory LSI can be bonded on the same pad on the substrate side, and wiring extension for connecting the terminals on the package substrate is necessary. There will be no. As a result, since the package substrate is only connected from the bonding lead to the ball terminal for external connection, it is possible to achieve a sufficiently necessary function by the two-layer wiring formed on the front and rear surfaces of the substrate. The configuration in which such pitch adjustment has been performed contributes to the thinning of the stacked package LSI as well as to the thinning of the mold. Since most of the bonding leads can be shared by the microcomputer LSI and the memory LSI, the number of leads is also reduced to the minimum necessary, and the external size can be reduced.
    [66] Regarding the leads of the sides shared and bonded by the microcomputer LSI and the memory LSI, the length of the lead is extended so that the wires connected to the microcomputer LSI and the memory LSI can be vertically lined and bonded. On the other hand, like the bonding lead corresponding to the long side of the memory LSI, the lead of the side bonding only the microcomputer LSI is limited to the length that can bond one wire, so that the wiring area is no longer necessary. have.
    [67] As in this embodiment, the lead length may be changed depending on whether or not a plurality of leads are bonded without changing the length of the bonding lead in units of sides. Another feature of this embodiment of the miniaturization is that since the memory chips are rectangular as described above, the sides on which the bonding leads of the memory chips are arranged have no room in the outer size, so that the bonding leads are placed on the outermost periphery. The through holes are arranged toward the inner circumference. On the other hand, the through hole is divided into and around the bonding lead with respect to the side which only a microcomputer chip bonds.
    [68] 4 is a top view of another embodiment of a package substrate used in the present invention. In the example of FIG. 1, the addresses of the memory LSI and the microcomputer LSI are the same as those in which the data are completely arranged on the same side. However, it is limited that the addresses and the data are completely concentrated on the opposite sides in terms of the layout of the chip. Can not. Even if the address and data are completely separated on opposite sides, the control signals, such as control signals such as read / write, chip select, and output enable, may not necessarily coincide in the microcomputer and the memory.
    [69] In this embodiment, when the same terminals or the terminals (bonding pads) to be interconnected are disposed on opposite sides in the microcomputer LSI and the memory LSI, wiring is provided on the substrate to cross the opposite sides. By concentrating most of the signals (address and data) to be interconnected in the microcomputer LSI and the memory LSI, the crossing lines are limited to a minimum. This makes it possible to achieve a sufficiently necessary function with two-layer wiring formed on the front and back surfaces of the substrate.
    [70] 5 shows a top view of one embodiment of a package substrate used in the present invention. This embodiment relates to the shape of the bonding lead. In the embodiment of the figure, it is an example of a package substrate in which rectangular bonding leads are arranged similarly to the embodiment of FIG. 6 shows an appearance in which a memory LSI and a microcomputer LSI are stacked and bonded to the package substrate. 6 also corresponds to the embodiment of FIG.
    [71] In this embodiment, in the bonding lead which bonds in common in the memory LSI and the microcomputer LSI, in order to bond at least two wires, the wires of the microcomputer LSI need to be connected to the corners (outer side) of the lead. As a result, the bonding pads of the microcomputer LSI are densely arranged near the center of the substrate, so that the wire is radially concentrated near the center of the substrate. As a result, there is a problem that the portion where the wire passes through the upper space of another adjacent lead is bonded, and the potential of the short between the adjacent lead and the wire becomes high.
    [72] Fig. 7 shows a top view of another embodiment of a package substrate used in the present invention. This embodiment relates to a method of avoiding the problem that a portion in which a wire, such as the embodiment of FIG. 5 above, is bonded through another adjacent lead may occur. In this embodiment, the bonding leads are arranged obliquely in consideration of the direction of the wires in which the bonding leads are connected to the bonding pads corresponding to the microcomputer LSI and the memory LSI. 8 shows an appearance in which the memory LSI and the microcomputer LSI are stacked and bonded to the package substrate.
    [73] In Fig. 8, in the bonding lead which bonds in common in the memory LSI and the microcomputer LSI, at least two wires are radially directed toward the corresponding bonding pads of the microcomputer LSI and the memory LSI. By becoming substantially the same in the longitudinal direction, there is no part where the wire is bonded through the air above other adjacent leads. At the same time, the wires do not cross complicatedly, and at least two wires overlap each other corresponding to the microcomputer LSI and the memory LSI, and the thickness of the mold can be reduced.
    [74] 9 is a top view of another embodiment of a package substrate used in the present invention. This embodiment relates to a method of avoiding the problem that a portion in which a wire, such as the embodiment of Fig. 5 above, is bonded through another adjacent lead, occurs. In this embodiment, the lead pitch can be narrowed to the minimum required while reducing the potential of the short between the adjacent lead and the wire by notching a portion through which the wire of the adjacent lead passes. The appearance of bonding and laminating a memory LSI and a microcomputer LSI on such a package substrate is shown in FIG.
    [75] In Fig. 10, in the bonding lead which bonds in common in the memory LSI and the microcomputer LSI as described above, at least two wires are radial to face the corresponding bonding pads of the microcomputer LSI and the memory LSI, and the microcomputer LSI. Wires need to be connected to the corners (outside) of the leads. As a result, a portion where the wire is bonded through the other lead adjacent to each other occurs, and the potential of the short between the adjacent lead and the wire becomes high, but the lead in the portion where the adjacent wire passes through the notch is notched, The problem of short between the adjacent lead and the wire can be avoided.
    [76] Fig. 11 shows a part of an external view of another embodiment of a semiconductor device according to the present invention. In this embodiment, a part of the appearance when one semiconductor chip LSI is mounted on a package substrate is exemplarily shown. In this embodiment, one semiconductor chip LSI is mounted on the semiconductor chip mounted on the package substrate. Of course, the same applies to a case where another semiconductor chip is stacked on this semiconductor chip LSI.
    [77] This embodiment is applied to the case where the number of bonding pads provided in the semiconductor chip LSI cannot be arranged in one row on the substrate. In this case, the bonding leads are arranged in two rows, and the inner and outer rows are alternately arranged in so-called stagger arrangements. The reason for this is to eliminate overlapping of adjacent wires connecting the bonding leads and the bonding pads, and to secure an area for forming wiring extending from the outer bonding lead to the through hole provided inside.
    [78] 12 is a partial external view of another embodiment of a semiconductor device according to the present invention. This embodiment is related to the improvement of the embodiment of Fig. 11, and a part of the appearance when one semiconductor chip LSI is mounted on a package substrate is exemplarily shown. In the embodiment of Fig. 11, a portion in which a wire extending from an outer bonding lead passes through an upper portion of another inner lead occurs and a potential of the short between the inner lead and the wire becomes high.
    [79] In this embodiment, in order to avoid such a problem, the bonding leads are arranged obliquely in consideration of the direction of the wires in which the bonding leads make connection with the corresponding bonding pads of the semiconductor chip LSI. By making the bonding lead and the wire connected to it radially in substantially the same direction, there is no part where the wire passes through the other lead inside and is bonded. At the same time, there is no case where the wires cross each other, and the thickness of the mold can be reduced while preventing the shorts between the wires.
    [80] FIG. 13 shows a partial external view of another embodiment of a semiconductor device according to the present invention. This embodiment is related to the improvement of the embodiment of Fig. 12, and a part of the appearance when one semiconductor chip LSI is mounted on a package substrate is exemplarily shown. In the embodiment of Fig. 12, when the leads are arranged in a row and the inclination of the leads is matched in the wire direction, the lead interval becomes wider toward the outside. On the contrary, the space | interval of the corner part of an inner lead becomes narrow, and the wiring which extends to a through hole from an outer lead may not pass. In order to avoid such a problem, in this embodiment, the inner circumferential corner portion of the lead widened radially therein is notched therein to secure the necessary space width for passing the wiring. This makes it possible to extend the wiring without widening the bonding area more than necessary.
    [81] Figure 15 shows a block diagram of one embodiment of a microcomputer LSI used in the present invention. Each circuit block in the figure is formed on a single substrate such as single crystal silicon by a manufacturing technique of a known CMOS (complementary MOS) semiconductor integrated circuit.
    [82] The microcomputer LSI is not particularly limited, but is realized by a reduced instruction set computer (RISC) type central processing unit (CPU), which realizes high performance arithmetic processing, directs peripheral devices required for system configuration, and is suitable for portable device applications. It is suitable. The central processing unit (CPU) has an instruction set of RISC type, and the basic instruction performs pipeline processing to operate in one instruction and one state (one system clock cycle). The following peripheral circuits are mounted mainly on the CPU and data signal processor, for example, for a mobile phone.
    [83] The internal bus is composed of I-bus, Y-bus, X-bus, L-bus and peripheral bus, and it is a built-in peripheral module that can configure the user system by minimum part points. (XYCNT) is installed. The memory XYMEM and the controller XYCNT are connected to the I bus, the X, Y bus, and the L bus, and data input / output for image processing and data output operation for the display operation are performed.
    [84] The I bus includes a cache memory (CACHE) and a cache memory controller (CCN), a memory management controller (MMU), a translation look-aside buffer (TLB), an interrupt controller (INTC), and a clock oscillator. The watchdog timer (CPG / WDT), video I / O module (VIO) and external bus interface are installed. It is connected to the memory LSI via this external bus interface.
    [85] The L bus includes the cache memory (CACHE) and the cache memory controller (CCN), the memory management controller (MMU), the translation look-side buffer (TLB), the central processing unit (CPU), and the data signal processor (DSP). ), A user brake controller (UBC) and an advanced user debugger (AUD) are connected.
    [86] The peripheral bus includes a 16-bit timer unit (TMU), a compare match timer (CMT), a serial I / O (with FIFO) (SIOF0), a FIFO built-in serial communication interface (SCIF1), and an I 2 C controller. (I 2 C), multifunction interface (MFI), NAND / AND flush interface (FLCTL), user debug interface (H-UDI), ASE memory (ASERAM) and pin function controller (PFC), The RCLK operation watchdog timer (RWDT) is connected. A bus state controller (BSC) and a direct memory access controller (DMAC) are connected to the peripheral bus and the I bus.
    [87] Figure 15 shows a schematic pinout diagram that is one embodiment of the microcomputer LSI of Figure 14. In this embodiment, there are 176 pins (bonding pads) in total, but among the pins connected to the memory LSI, black dots are attached. Similarly to the microcomputer LSI of FIG. 1, pins corresponding to addresses and data are arranged in two upper and lower sides. In this example, a pin corresponding to data is arranged on the upper side, and a pin corresponding to an address is arranged on the lower side. Then, in order to suit the pitch of the corresponding pin (bonding pad) of the memory LSI on which it is mounted, a pin connected to the microcomputer LSI alone is appropriately disposed between the black dots connected to the memory LSI.
    [88] Although not shown, pins provided in the microcomputer LSI are provided with AO to A25 as the address and DO to D15 as the data. In addition, a plurality of power supply voltages VCC and ground potentials VSS are provided as power supply systems, respectively. In order to reduce the influence of noise on the power supply system, for digital circuits, the power supply system is divided into an output circuit and an internal circuit which output signals to external terminals. In addition, a circuit for handling analog signals has its own power pin.
    [89] Since the memory LSI has a storage capacity of about 8 M bits and performs memory access in units of 16 bits, the address is 19 bits, which are A0 to A18. The microcomputer LSIs have 26 A0 to A25 as addresses as described above, but 19 microcomputer LSIs and memory LSIs are commonly connected to each other, and 19 + 16 = 35 for data.
    [90] In addition, although not particularly limited, there are four control signals that are commonly connected, WE (light enable), OE (output enable), US (upper selector), and LS (low selector). The signal US indicates that the upper 8 bits of the 16-bit data indicate the recording, and the signal LS indicates the lower 8 bits of the 16-bit data to indicate the recording. Thereby, the number connected in common in the microcomputer LSI and the memory LSI is as few as 39 in total. Therefore, in the microcomputer LSI, a bonding pad for jumping data and a bonding pad for address are arranged in the microcomputer LSI so as to match the arrangement of the pins commonly connected to the memory LSI.
    [91] Fig. 16 shows an external view after bonding the memory LSI and the microcomputer LSI after mounting them on the substrate which is one embodiment of the semiconductor device according to the present invention. This embodiment shows a stacked package LSI equipped with a memory LSI consisting of the microcomputer LSI described with reference to Figs. 14 and 15 and an SRAM of about 8M bits. In the same figure, the ball provided in the back surface of a package board | substrate is shown by the circle | round | yen.
    [92] In this embodiment, among the bonding leads provided on the substrate, the black ones are wired and connected in common to the memory LSI and the microcomputer LSI therefrom. In Fig. 17, an enlarged view of a part thereof is shown, and the bonding leads are made to be inclined along the extending direction of the wires, and the wires extending from the bonding leads toward the memory LSI and the microcomputer LSI do not cross each other. This configuration also prevents the wires extending from the adjacent leads from crossing the bonding leads.
    [93] 18 is a top view of an embodiment of a package substrate used in the semiconductor device of FIG. Bonding leads including data terminals and address terminals of the memory LSI and microcomputer LSI are provided on the upper and lower sides of the substrate. Bonding leads provided on the upper and lower sides are arranged along the outermost periphery. On the other hand, the bonding leads, which are connected only to the microcomputer LSI, are distributed from side to side with the center as the through holes. That is, in the left and right sides, a through hole is provided at the outermost circumference. The number of through holes distributed from side to side with respect to the bonding lead is not uniformly divided evenly alternately as in the embodiment of FIG. 1, but the number is appropriately determined in consideration of the space on the substrate.
    [94] In the above embodiment, since the extension of the wiring on the substrate package is minimized, the external size can be reduced. By eliminating the cross wiring, package wiring can be connected to the front and back two layers, thereby enabling the use of a thin and inexpensive substrate. Moreover, the mold part can be made thin by suppressing the cross of a wire. That is, in the case of the configuration as shown in Fig. 19 discussed above in the present invention, the semiconductor device that can only be LFBGA at 1.4 mm square is configured as shown in Fig. 16, so as to be TFBGA at 1.2 mm square. It is possible to realize a semiconductor device having a small rank of one.
    [95] As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, Needless to say that various changes are possible in the range which does not deviate from the summary. For example, the memory LSI may be a dynamic RAM or a flush memory (EEPROM) in addition to the SRAM described above. The microcomputer LSI may be any digital signal processing circuit including a microprocessor and the like. The present invention can be widely used for a semiconductor device in which one semiconductor chip is mounted on a substrate in addition to the stacked package LSI described above, and a package having a BGA configuration is employed.
    [96] When the effect obtained by the typical thing of the invention disclosed in this application is demonstrated briefly, it is as follows. Bonding leads provided in correspondence with the bonding pads for address and data divided into the first and second sides of the memory chip facing each other, and a package substrate having address terminals and data terminals connected to the bonding leads are used. An address output circuit and a data input / output circuit used for memory access, and a signal processing circuit having a data processing function, and corresponding to a bonding pad and a data terminal connected to a bonding lead corresponding to an address terminal of the package substrate. Since the bonding pads connected to the bonding leads are stacked in two of four sides and the semiconductor chips and the memory chips are stacked in a stacked structure, the extension of wiring on the substrate package can be minimized. It is possible to reduce the size to small and to connect two layers to the front and rear, so that a thin and inexpensive substrate It becomes usable.
    权利要求:
    Claims (14)
    [1" claim-type="Currently amended] A memory chip having a bonding pad corresponding to an address terminal along a first side, and a bonding pad corresponding to a data terminal along a second side opposite to the first side;
    A package substrate provided with a bonding lead provided in correspondence with a first side of said memory chip, a bonding lead provided in correspondence with a second side of said memory chip, an address terminal and a data terminal connected with said bonding lead;
    An address output circuit and a data input / output circuit, which are also used for memory access, and signal processing having a data processing function, and a bonding pad connected to a bonding lead corresponding to an address terminal of the package substrate and a bonding lead corresponding to a data terminal. Bonding pads to be connected are provided with a semiconductor chip disposed in two of the four sides,
    And the memory chip and the semiconductor chip are stacked on the package substrate.
    [2" claim-type="Currently amended] The method of claim 1,
    Corresponding terminals of the semiconductor chip and the memory chip are connected by wires to the common bonding lead of the package substrate.
    [3" claim-type="Currently amended] The method of claim 1,
    According to the pitch of each bonding pad of the address and data of the memory chip, each bonding pad of the address and the data corresponding to the semiconductor chip is arranged,
    And a bonding pad independently provided on the semiconductor chip so as to conform to a pitch on the memory chip side, between the bonding pads of the address and data of the semiconductor chip.
    [4" claim-type="Currently amended] The method of claim 1,
    The package substrate is a semiconductor device, characterized in that a wiring layer is provided on a surface on which a semiconductor chip is mounted and a back surface on which balls as external terminals are provided, and corresponding wiring layers are connected through through holes.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    The semiconductor chip constitutes a microcomputer of one chip,
    And bonding pads connected to the external terminals required for the microcomputer on the remaining two sides of the four sides.
    [6" claim-type="Currently amended] The method of claim 5, wherein
    The memory chip has a larger area than the semiconductor chip, and is a rectangle in which the lengths of the first and second sides are shorter than the lengths of the other two sides.
    And a lead-out direction of the wiring reaching the through hole is directed toward the inside of the package substrate with respect to the bonding lead rows provided corresponding to the first and second sides of the memory chip.
    [7" claim-type="Currently amended] The method of claim 6,
    The memory chip is mounted on the surface of the package substrate,
    And the semiconductor chip is mounted on a surface of the memory chip to form a stacked structure.
    [8" claim-type="Currently amended] The method of claim 5, wherein
    And a drawing lead direction of the wiring reaching the through hole is divided into an inner side and an outer side of the package substrate with respect to the bonding lead rows provided corresponding to two sides other than the first side and the second side of the memory chip.
    [9" claim-type="Currently amended] The method of claim 8,
    The length of the bonding lead provided corresponding to two sides other than the first side and the second side of the memory chip becomes shorter with respect to the length of the bonding lead provided corresponding to the first side and the second side of the memory chip. A semiconductor device characterized by the above-mentioned.
    [10" claim-type="Currently amended] The method of claim 6,
    Bonding leads of package substrates corresponding to the first and second sides of the memory chip may have a rectangular shape such that their lengths are oriented in the extending direction of the wires that connect the bonding pads of the memory chips and semiconductor chips corresponding thereto. A semiconductor device, characterized in that.
    [11" claim-type="Currently amended] The method of claim 7, wherein
    A bonding device provided respectively corresponding to the first side and the second side of the memory chip is provided with a notch in a portion where a wire connected to another bonding lead passes through the air. .
    [12" claim-type="Currently amended] The method of claim 10,
    Bonding leads provided respectively corresponding to the first and second sides of the memory chip are staggered in two rows, inside and outside, in accordance with an extension direction of a wire connected thereto.
    A semiconductor device, characterized in that the notch portion is provided at the inner end of the inner bonding lead.
    [13" claim-type="Currently amended] A semiconductor chip having bonding pads arranged along at least a first side and a second side opposite the first side;
    A package substrate having bonding leads provided respectively corresponding to the first and second sides of the semiconductor chip, and external terminals connected to the bonding leads,
    The bonding lead is a semiconductor device, characterized in that a notch is provided at a portion where a wire connected to another bonding lead passes through the air.
    [14" claim-type="Currently amended] A semiconductor chip having a bonding pad arranged along at least a first side and a second side corresponding to the first side;
    A package substrate having bonding leads provided respectively corresponding to the first and second sides of the semiconductor chip, and external terminals connected to the bonding leads,
    The bonding leads are staggered in two rows in and out along the extension direction of the wire connected thereto,
    The lead-out direction of the wiring leading to each lead through hole is directed toward the inside of the package substrate.
    A semiconductor device characterized in that a notch portion is provided at an inner end of an inner bonding lead.
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    同族专利:
    公开号 | 公开日
    US20040027869A1|2004-02-12|
    CN1481021A|2004-03-10|
    CN101079404A|2007-11-28|
    JP2004071838A|2004-03-04|
    US20060180943A1|2006-08-17|
    TW200409333A|2004-06-01|
    CN100433324C|2008-11-12|
    US7061785B2|2006-06-13|
    TWI283919B|2007-07-11|
    US7286386B2|2007-10-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-08-06|Priority to JP2002229250A
    2002-08-06|Priority to JPJP-P-2002-00229250
    2003-07-24|Application filed by 가부시키가이샤 히타치세이사쿠쇼
    2004-03-18|Publication of KR20040023493A
    优先权:
    申请号 | 申请日 | 专利标题
    JP2002229250A|JP2004071838A|2002-08-06|2002-08-06|Semiconductor device|
    JPJP-P-2002-00229250|2002-08-06|
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