• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for manufacturing a semiconductor device is provided to prevent damage of a polysilicon layer by enhancing the etching selectivity of the polysilicon layer against a silicon oxide layer. CONSTITUTION: The first interlayer dielectric(21A), the first lower line(22A), the second interlayer dielectric(21B) and the second lower line(22B) are sequentially formed on a substrate(20). A nitride layer(23) is formed by nitridizing the surface of the second lower line. After forming the third interlayer dielectric(21C), a deep contact hole(C4) is formed to expose the first lower line(22A) and a shallow contact hole(C3) is simultaneously formed to expose the nitride layer.
    公开号:KR20040008677A
    申请号:KR1020020042347
    申请日:2002-07-19
    公开日:2004-01-31
    发明作者:장성수；최봉호
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}
    [9] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can improve the etching selectivity of the polysilicon film to the silicon oxide film.
    [10] In general, in manufacturing semiconductor devices, polysilicon films are used in various ways, such as etching masks such as hard masks as well as electrodes and wirings. However, when the polysilicon film and the silicon oxide film are applied as the wiring material and the insulating material, respectively, to etch the silicon oxide film to form the contact hole, or to apply the polysilicon film as the hard mask, the silicon oxide film is etched. If the etching selectivity of the film is not sufficiently secured, a problem occurs that the polysilicon film is damaged.
    [11] For example, in forming a multi-layered interconnection in which lower interconnections and upper interconnections are connected to each other through contact holes, a difference in depth of contact holes occurs when the levels of lower interconnections are different from each other. If the etching selectivity of the silicon oxide film is not sufficient, a problem arises in that the etching depth from the low depth contact hole portion to the polysilicon film is generated.
    [12] FIG. 1 is a diagram illustrating a problem caused by silicon oxide film etching when a depth difference between contact holes is generated when wirings of the multilayer structure are described. FIG. 1 will be described in more detail with reference to FIG. 1.
    [13] Referring to FIG. 1, a second interlayer insulating film 11B is formed on a semiconductor substrate on which a first interlayer insulating film 11A and a first lower wiring 12A are sequentially formed, and a second interlayer insulating film 11B is formed on the second interlayer insulating film 11B. After the second lower wiring 12B is formed, a third interlayer insulating film 11C is formed on the entire substrate. Here, the first, second and third interlayer insulating films 11A, 11B, and 11C are made of a silicon oxide film, the first lower wiring 12A is made of a metal film, and the second lower wiring 12B is made of polysilicon. Is made of membrane.
    [14] Next, the first, second, and third interlayer insulating films 11A, 11B, and 11C on the first lower wiring 12A and the third interlayer insulating film 11C on the second lower wiring 12B are etched to form a first etching. And first and second contact holes C1 and C2 exposing portions of the second lower interconnections 12A and 12B, respectively. At this time, if the etching selectivity of the polysilicon film to the silicon oxide film is not sufficient, the second lower wiring 12B of the second contact hole C2 having a relatively low depth may be damaged when the contact holes C1 and C2 are formed. However, etching proceeds to the second lower interconnection 12B, thereby lowering the lower interconnection 12B, thereby causing problems such as an increase in contact resistance and a short circuit between the interconnections, thereby degrading the characteristics and reliability of the device.
    [15] The present invention is proposed to solve the problems of the prior art as described above, to improve the etching selectivity of the polysilicon film to the silicon oxide film to prevent problems caused by damage to the polysilicon film generated during the etching of the silicon oxide film. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
    [1] 1 is a view showing a problem caused by silicon oxide film etching when a depth difference of a contact hole occurs when forming a wire of a conventional multilayer structure.
    [2] 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
    [3] 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
    [4] ※ Explanation of symbols for main parts of drawing
    [5] 20, 30: semiconductor substrate 21A, 21B, 21C interlayer insulating film
    [6] 22A, 22B: lower wiring 23, 33: nitride film
    [7] C3, C4: contact hole 31: silicon oxide film
    [8] 32: polysilicon film 100: hard mask
    [16] According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is to sequentially form a first interlayer insulating film, a first lower wiring, a second interlayer insulating film and a second lower wiring on a semiconductor substrate. Doing; Nitriding the surface of the second lower interconnection by a predetermined thickness to form a nitride film; Forming a third interlayer insulating film on the entire surface of the substrate; And a first contact hole having a deep depth exposing a portion of the first lower interconnection by etching the first to third interlayer dielectric layers on the first lower interconnection and etching the third interlayer dielectric layer on the second lower interconnection. It can be achieved by a method of manufacturing a semiconductor device comprising the step of forming each of the second contact hole of a shallow depth to expose a portion of the. Preferably, the first to third interlayer insulating films are silicon oxide films, the second lower wiring is a polysilicon film, and the second lower wiring is nitrided so that the thickness of the nitride film is within 30% of the thickness of the second lower wiring.
    [17] In addition, according to another aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of sequentially forming a silicon oxide film and a polysilicon film on a semiconductor substrate; Nitriding the surface of the polysilicon film by a predetermined thickness to form a nitride film; Patterning the polysilicon film on which the nitride film is formed to form a hard mask; And etching the oxide layer using the hard mask as an etch mask. Preferably, nitriding of the polysilicon film is performed so that the thickness of the nitride film is within 30% of the thickness of the polysilicon film.
    [18] Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
    [19] 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. In the present embodiment, a polysilicon film, which is a lower wiring in which contact holes having a low depth are formed when a multi-layered wiring is formed. The case where a nitride film is applied to the surface is shown.
    [20] Referring to FIG. 2A, a first lower interconnection 22A is formed by depositing and patterning a metal film on the semiconductor substrate 20 on which the first interlayer insulating layer 21A is formed. Next, a second interlayer insulating film 21B is formed on the entire surface of the substrate on which the first lower wiring 22A is formed, and a polysilicon film is deposited and patterned on the second interlayer insulating film 21B to form the second lower wiring 22B. To form. Here, the first and second interlayer insulating films 21A and 21B are formed of a silicon oxide film.
    [21] Referring to FIG. 2B, the surface of the second lower interconnection 22A is nitrided by a thickness within a predetermined thickness, preferably within 30% of the thickness of the second lower interconnection 22A, thereby etching the second lower interconnection 22A. The nitride film 23 is formed as a prevention film. Here, nitriding of the second lower wiring 22A is performed by heat treatment or plasma treatment. Preferably, the heat treatment is NH 3 or in a gas atmosphere containing N 2 rapidly at a temperature of 700 to 1000 ℃ heat treatment; performed in (Rapid Thermal Anneal RTA) or, NH 3, or in a gas atmosphere containing N 2 500 to 800 At a temperature of < RTI ID = 0.0 > In addition, the plasma treatment is performed with a plasma formed of a gas containing NH 3 or N 2 O.
    [22] Referring to FIG. 2C, a third interlayer insulating film 21C is formed of a silicon oxide film on the entire surface of the substrate on which the nitride film 23 is formed. Then, the first, second and third interlayer insulating films 21A, 21B and 21C on the first lower wiring 22A are etched and the third interlayer insulating film 21C on the second lower wiring 22B is etched. Etching forms a first deep contact hole C3 exposing a portion of the first lower interconnection 22A and a second deep contact hole C4 having a shallow depth exposing a portion of the nitride film 23, respectively. .
    [23] According to the above embodiment, by forming an etch stop layer of the nitride film 23 on the surface of the second lower wiring 22A to improve the etch selectivity with respect to the interlayer insulating film, the shallow depth when forming the contact hole due to the level difference between the lower wiring Damage and etching of the second lower wiring 22A in which the contact hole of the second hole is formed are prevented.
    [24] 3A to 3B illustrate a method of manufacturing a semiconductor device according to another embodiment of the present invention. In the present embodiment, when the polysilicon film is used as a hard mask, the nitride film is applied to the surface of the polysilicon film.
    [25] Referring to FIG. 3A, a silicon oxide film 31 is deposited on the semiconductor substrate 30, and a polysilicon film 32 is formed on the silicon oxide film 31. Next, the surface of the polysilicon film 32 is nitrided by a predetermined thickness, preferably within 30% of the thickness of the polysilicon film 32, so that the nitride film 33 is used as an etch stopper for the polysilicon film 32. To form.
    [26] Here, nitriding of the polysilicon film 32 is performed by heat treatment or plasma treatment. Preferably, the heat treatment is carried out at a temperature of NH 3 or in the gas atmosphere containing N 2 to 700 performed by RTA at a temperature of 1000 ℃, or in a gas atmosphere containing NH 3 or N 2 500 to 800 ℃. In addition, the plasma treatment is performed with a plasma formed of a gas containing NH 3 or N 2 O.
    [27] Referring to FIG. 3C, the polysilicon layer 32 on which the nitride layer 33 is formed is patterned to form a hard mask 100, and the oxide layer 31 is etched using the hard mask 100 as an etching mask. At this time, the etching selectivity with respect to the oxide film 31 is improved by the nitride film 33 formed on the surface of the polysilicon film 32, thereby preventing damage to the polysilicon film 32 when the oxide film 31 is etched.
    [28] The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
    [29] The present invention as described above forms a nitride film on the surface of the polysilicon film to improve the etching selectivity of the polysilicon film to the oxide film, thereby preventing damage and etching of the polysilicon film generated during the oxide film, thereby improving the characteristics and reliability of the device. You can do it.
    权利要求:
    Claims (13)
    [1" claim-type="Currently amended] Sequentially forming a first interlayer insulating film, a first lower wiring, a second interlayer insulating film, and a second lower wiring on a semiconductor substrate;
    Forming a nitride film by nitriding the surface of the second lower wiring by a predetermined thickness;
    Forming a third interlayer insulating film on the entire surface of the substrate; And
    A first contact hole having a deep depth exposing a portion of the first lower interconnection by etching the first to third interlayer dielectric layers on the first lower interconnection and etching the third interlayer dielectric layer on the second lower interconnection; And forming a second contact hole having a shallow depth to expose a portion of the nitride film, respectively.
    [2" claim-type="Currently amended] The method of claim 1,
    Wherein the first to third interlayer insulating films are silicon oxide films, and the second lower interconnection is a polysilicon film.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    And nitriding the second lower interconnection so that the thickness of the nitride film is within 30% of the thickness of the second lower interconnection.
    [4" claim-type="Currently amended] The method of claim 3, wherein
    Nitriding the second lower interconnection is performed by heat treatment or plasma treatment.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    The heat treatment is a method of manufacturing a semiconductor device, characterized in that carried out in RTA at a temperature of 700 to 1000 ℃ in a gas atmosphere containing NH 3 or N 2 .
    [6" claim-type="Currently amended] The method of claim 4, wherein
    The heat treatment is a method for manufacturing a semiconductor device, characterized in that carried out at a temperature of 500 to 800 ℃ in a gas atmosphere containing NH 3 or N 2 .
    [7" claim-type="Currently amended] The method of claim 4, wherein
    The plasma treatment method is a semiconductor device manufacturing method characterized in that performed with a plasma formed of a gas containing NH 3 or N 2 O.
    [8" claim-type="Currently amended] Sequentially forming a silicon oxide film and a polysilicon film on a semiconductor substrate;
    Nitriding the surface of the polysilicon film by a predetermined thickness to form a nitride film;
    Patterning the polysilicon film on which the nitride film is formed to form a hard mask; And
    And etching the oxide film using the hard mask as an etching mask.
    [9" claim-type="Currently amended] The method of claim 8,
    And nitriding the polysilicon film so that the thickness of the nitride film is within 30% of the thickness of the polysilicon film.
    [10" claim-type="Currently amended] The method of claim 8,
    Nitriding the polysilicon film is a method of manufacturing a semiconductor device, characterized in that performed by heat treatment or plasma treatment.
    [11" claim-type="Currently amended] The method of claim 10,
    The heat treatment is a method of manufacturing a semiconductor device, characterized in that carried out in RTA at a temperature of 700 to 1000 ℃ in a gas atmosphere containing NH 3 or N 2 .
    [12" claim-type="Currently amended] The method of claim 10,
    The heat treatment is a method for manufacturing a semiconductor device, characterized in that carried out at a temperature of 500 to 800 ℃ in a gas atmosphere containing NH 3 or N 2 .
    [13" claim-type="Currently amended] The method of claim 10,
    The plasma treatment method is a semiconductor device manufacturing method characterized in that performed with a plasma formed of a gas containing NH 3 or N 2 O.
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    同族专利:
    公开号 | 公开日
    KR100895434B1|2009-05-07|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-07-19|Application filed by 주식회사 하이닉스반도체
    2002-07-19|Priority to KR1020020042347A
    2004-01-31|Publication of KR20040008677A
    2009-05-07|Application granted
    2009-05-07|Publication of KR100895434B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020042347A|KR100895434B1|2002-07-19|2002-07-19|Method of manufacturing semiconductor device|
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