• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Disclosed are a semiconductor integrated circuit and a memory device capable of selecting a power-down escape rate and a power saving mode, and a method of selecting the same. The memory device includes a command decoder for generating a power down signal in response to a power down command, a mode register for storing power down escape information, and a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal. And a control unit for controlling the DLL or PLL circuit. Upon powering down the memory device, the power down escape information may select a fast wake-up time and a slow wake-up time.
    公开号:KR20040007203A
    申请号:KR1020020077282
    申请日:2002-12-06
    公开日:2004-01-24
    发明作者:이동양；이정배
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    Device and method for selecting power down exit
    [10] The present invention relates to an apparatus and method for controlling a semiconductor memory device, and more particularly, to a memory device and a method having a circuit for controlling the operation of the memory in the power-down escape mode and controlling the memory.
    [11] As the operation speed and capacity of the semiconductor memory device gradually increase, a method of incorporating a memory control circuit such as a clock synchronizer into the memory device is used. The clock synchronizer is used to generate an internal clock signal synchronized with an external clock signal such as a system clock. The internal clock signal is used to synchronously drive memory devices such as SDRAMs or DDR-SDRAMs. The clock synchronizer is a phase locked loop (PLL), a delay locked loop (DLL), or a duty-cycle correction circuit.
    [12] PLL circuits typically include a phase detector, charge pump, loop filter, and voltage controlled oscillator (hereinafter referred to as "VCO"). The phase detector compares a phase of an external clock signal and an internal clock signal (output of a VCO), generates an UP signal or a DOWN signal according to the phase difference, and transmits an up or down signal to the loop filter. The charge pump generates a constant output voltage in response to an up or down signal and sends it to the loop filter. The loop filter filters the output voltage of the charge pump to generate a control voltage to regulate the VCO. The VCO inputs a control voltage and outputs a predetermined frequency proportional thereto. As a result, the PLL circuit synchronizes the output frequency with the input frequency to synchronize the phase of the internal clock signal and the external clock signal.
    [13] In the DLL circuit, when synchronizing the external clock signal with the internal clock signal, the DLL circuit delays the phase of the external clock signal. DLL circuits are commonly used in DRAM. One exemplary DLL circuit is disclosed in US Pat. No. 5,614,855. Another example DLL circuit changes the length of the delay line through which the clock signal passes. Delay line changes are implemented using tapping points that selectively activate coarse and fine delay chains. The phase detector is connected to the delay line to detect the phase difference.
    [14] Other phase or duty cycle correction (DCC) circuits are implemented in the form of a register that stores the phase delay values of the internal and external clock signals. The phase delay value is stored at power down and updated after a power-down exit that locks the internal and external clock signals. In the above clock synchronizing circuits, the operation of the clock synchronizing circuit and the driver buffer are necessary to fan out the clock signal to the internal circuits of the SDRAM which consumes a lot of power.
    [15] The SDRAM enters a power down mode to conserve power when not in use. 1 to 3 show conventional memory devices, mode registers and power down circuits.
    [16] FIG. 1 is a diagram illustrating a mode register (MRS) used in the memory device of FIG. 2. The MRS has A0 to A12 address fields in which information for adjusting the operation mode of the SDRAM (for example, burst length BL, burst type BT, cas latency and test mode) is stored. This information is issued from the central processing unit (CPU) to the memory device to operate in a different mode. In general, burst length, burst type, cas latency, and test mode are used in the A0-A2 field, in the A3 field, in the A4-A6 field, and in the A7 field, respectively. The A8-A12 field is reserved for future use and is typically set to "0" for normal operation operation.
    [17] 2 illustrates a conventional memory device, which includes a memory core 100 having an array of memory cells, a mode register 250 having address fields and operation mode information shown in FIG. 1, address decoders 270 and 280, The DLL circuit 230 which generates an internal clock ICLK, a clock buffer 210, an address buffer 260, a data buffer 290, and a command buffer and a decoder 240 are included. Commands from the CPU or memory controller are received by the command buffer and decoder 240. The instructions are processed and distributed to related components, such as mode register 250, which accesses memory core 100. The external clock ECLK is received by the clock buffer 210 and the buffered clock ECLK1 is input to the DLL circuit 230 through the DLL enable circuit 220.
    [18] The DLL circuit 230 generates an internal clock ICLK for driving the memory core 100. The memory core 100 is placed in a power down or standby mode that conserves power when memory cells in the memory core 100 are not accessed. The power down command (PWDN) generated from the command buffer and decoder 240 is used to enter or exit the memory device into a power down mode, which is implemented by the circuit of FIG. 3. As shown in FIG. 3, the external clock ECLK is buffered through the clock buffer 210, transferred to the DLL circuit 230 through the gate 224, and synchronized with the external clock signal ECLK. ICLK) is generated to drive the memory device. If you want to put the memory device in power-down mode, the logic gate 224 is disabled at logic " 1 " of the power down signal (PWDN) when the active command enters the power-down mode and the DLL circuit 230 output The internal clock ICLK is deactivated. Since the memory core 100 does not operate without a clock signal, power consumption is conserved when the memory device is in the power down mode.
    [19] In the conventional memory device and power down mode operation described above with reference to FIGS. 230 is not turned off. Accordingly, to further reduce power consumption, the DLL circuit 230 must be turned off. This description of the DLL circuit can be applied to other clock synchronizing circuits, such as a PLL circuit and a duty cycle correction circuit. As mentioned earlier, the DLL and PLL circuits include a number of components, including a phase detector, a charge pump and a VCO. Turning off the clock synchronizing circuit means that significant power consumption can be reduced. However, when the PLL circuit or the DLL circuit is turned off, it takes a predetermined time to lock and synchronize the phases of the internal clock and the external clock. Typically, about six clock cycles are needed to synchronize the internal clock to an external clock, so there is a tradeoff between power saving and escape or wake-up in power down mode.
    [20] Wake-up or escape in power down mode returns the device in power down or standby mode to normal operation mode. After a power down escape command, some time is required for the device to properly perform normal operations. The normal operation means an operation by an active command, an operation by a read command, an operation by a write command, or the like.
    [21] Therefore, a memory device capable of selecting various power saving modes is desired.
    [22] It is an object of the present invention to provide a memory device capable of variously selecting a power saving mode.
    [1] 1 is a view showing a conventional mode register.
    [2] 2 is a diagram illustrating a conventional memory device.
    [3] 3 is a diagram illustrating a conventional clock generator enable circuit in the memory device of FIG. 2.
    [4] 4 is a diagram illustrating a memory device according to an exemplary embodiment of the present invention.
    [5] 5 illustrates a mode register according to an embodiment of the present invention.
    [6] 6 is a diagram illustrating a circuit for controlling a memory according to an exemplary embodiment of the present invention.
    [7] 7A is a diagram illustrating an example timing diagram according to a power down escape mode according to an embodiment of the present invention.
    [8] 7B is a diagram illustrating another example timing diagram according to the power down escape mode of the embodiment of the present invention.
    [9] 8 is a diagram illustrating a memory device according to another exemplary embodiment of the present invention.
    [23] In order to achieve the above object, the present invention provides a memory control circuit for controlling a memory having a plurality of memory cells arranged in rows and columns, at least one of decoding an address field and outputting a decoded address for addressing the memory. And a mode register for storing mode register set (MRS) data used to specify at least one of a plurality of operating modes of the memory device including a plurality of power down exit modes based on an address field of the < RTI ID = 0.0 > do.
    [24] Preferably, the memory control circuit selectively clocks the memory to generate an internal clock signal synchronized with the external clock signal, and selectively enables the output of the external clock signal to the clock generator based on a power down command. In order to receive the external clock signal and the power down command directly or indirectly includes an enable circuit generation unit. The clock generator enable circuit receives a power down escape mode selection signal that selects at least one of the power down escape modes and selectively enables the power down command.
    [25] Multiple power down escape modes include a slow wake-up escape mode and a fast wake-up escape mode. The memory device operates in a normal mode within a first clock cycle number after reception of the slow wake-up escape mode and within a second clock cycle number less than the first clock cycle number after reception of the fast wake-up escape mode. Preferably, the first clock cycle number is at least five and the second clock cycle number is at least two.
    [26] The clock generator enable circuit receives the power down escape mode select signal and generates an additional power down signal for powering down a circuit other than the memory cells. Circuitry other than memory cells includes at least a clock generator portion. The address field includes A0 to A12, and the power down escape mode selection signal is any one of the A8 to A12 address fields.
    [27] The memory device is SDRAM or DDR SDRAM. The clock generator is a phase locked circuit PLL, a delay locked circuit DLL or a duty cycle correction circuit DCC. Address fields and power down commands are provided from the memory controller.
    [28] Further, the present invention provides a memory control system for controlling a memory device having an array of memory cells arranged in rows and columns, comprising: at least one address decoder for decoding an address field to output decoded addresses addressing the memory device; A mode register for storing mode register set (MRS) data specifying at least one of a plurality of operating modes of a memory device including a plurality of power down exit modes based on an address field; and an address field and the mode register ( Memory controller for providing signals for generating MRS. The memory control system includes a clock generator for generating an internal clock signal synchronized with an external clock signal to clock a memory device, and an external clock for selectively enabling the output of the external clock signal to the clock generator based on a power down command. The apparatus may further include a clock generator enable circuit configured to directly or indirectly receive a signal and a power down command.
    [29] The clock generator enable circuit receives a power down escape mode selection signal that selects at least one of the power down escape modes and selectively enables the power down command.
    [30] In addition, the present invention provides a memory control circuit of a memory device having an array of memory cells arranged in rows and columns, the memory control circuit comprising: at least one address decoder for decoding an address field to output decoded addresses addressing the memory device; Logic circuitry for receiving a signal specifying at least one of a plurality of operating modes of a memory device comprising a plurality of power down escape modes based on the field.
    [31] The memory control circuit includes a clock generator for generating an internal clock signal synchronized with an external clock signal to clock the memory device, and an external clock for selectively enabling the output of the external clock signal to the clock generator based on a power-down command. The apparatus may further include a clock generator enable circuit configured to directly or indirectly receive a signal and a power down command. The enable circuit generator receives a power down escape mode selection signal that selects at least one of the power down escape modes to selectively enable the power down command.
    [32] The present invention provides a method of controlling a memory device having an array of memory cells arranged in rows and columns, the method comprising: decoding an address field and outputting decoded addresses addressing the memory device; Storing mode register set (MRS) data used to specify at least one of a plurality of operating modes of a memory device including a power down exit mode.
    [33] The memory device control method includes generating an internal clock signal synchronized with an external clock signal through a clock generator to clock a memory device, and generating a clock based on a power down command and one of a plurality of power down escape modes. And disabling the wealth.
    [34] The memory device control method further includes assigning a power down escape mode selection signal to one bit of the address field to select one of the plurality of power down escape modes. Preferably, one bit is any one of A8 to A12 (RFU field) of the A0 to A12 address field.
    [35] Hereinafter, according to embodiments of the present invention, when the memory device exits the power down mode from the normal mode, the wake-up time and the power consumption of the memory device may be selected. The normal mode means a state of an active command, a read command, or a write command. The choice of wake-up time and power consumption is based on the power down ejection information stored in the mode register (MRS). If SDRAM is used in portable products such as power saving, slow wake-up and power saving modes are selected. If SDRAM is used in a high performance computer system, a fast wake-up power down exit mode is selected because fast wake-up is required.
    [36] 4 is a diagram illustrating a memory device according to an exemplary embodiment of the present invention. The memory device 10 is composed of a memory core 100 which is a DRAM in which memory cells are arranged in rows and columns. DRAM is preferably SDRAM or DDR SDRAM. Row address buffer and decoder 270 and column address buffer and decoder 280 provide the row address and column address during a read / write operation of the memory. Data to the memory core 100 is input through the data buffer 290, and the address buffer 260 receives an address field, such as A0-A12, and then stores the addresses into a row address buffer and a decoder 270, and a column address buffer. And a decoder 280 and a mode register 350.
    [37] The command buffer and decoder 240 receive and decode commands from the outside according to the present embodiment, and provide the decoded commands to the memory core 100 through a peripheral circuit (not shown). The decoded command of the command buffer and decoder 240 includes a mode register set (MRS) command for input to the mode register 350 and a power down command (PWDN) coupled with the DLL enable circuit 320. The DLL circuit 230 is a clock synchronization circuit that generates an internal clock ICLK used to drive the memory core 100. The power down command PWDN is used to power down the memory core, preferably to disable the internal clock ICLK to put the memory core 100 in standby mode. The DLL circuit 230 may be a clock synchronization circuit using feedback and phase locking such as PLL, DLL, DCC, and the like. Here, a DLL circuit is used to describe an embodiment of the present invention. The clock buffer 210 receives and buffers the external clock ECLK to provide the buffered clock signal ECLK1 to the DLL enable circuit 320.
    [38] According to a preferred embodiment of the present invention, a power down cancel mode select signal PD is optionally provided to the DLL enable circuit 320 through the mode register 350 to provide a plurality of power down escape modes. Multiple escape command modes preferably include a fast wake-up mode and a power saving or slow wake-up mode. Fast wake-up mode allows the SDRAM to wake up quickly in two to four clock cycles in power-down mode. Power-saving or slow wake-up mode allows users to save more power by letting the SDRAM take at least 5 clock cycles, or preferably 6 to 10 clock cycles, to escape from the power-down mode. Let it be. The power down cancel mode selection signal PD is provided to the DLL enable circuit 320 in the mode register 320 to selectively control the DLL enable circuit 320 and the DLL circuit 230.
    [39] 5 illustrates the use of A0 through A12 address fields in mode register 350. According to this embodiment, A12 of the address fields A0-A12 is used to provide the power down escape mode selection signal PD. One of the fields RFU reserved for the future in the mode register 350 corresponds to A12. In this embodiment, a logic "0" is assigned to A12 to indicate that the power down escape signal PD is in fast wake-up escape mode, and a logic "1" is assigned to A12 to indicate a slow wake-up or power saving escape mode. . Although the power down escape mode signal PD is associated with A12, it is apparent to those skilled in the art that any one of the address bits in the address field can be used as the power down escape mode signal PD. The manufacturer or user can select a fast wake-up exit mode for high performance devices such as desk-top computers. The slow wake-up or power saving escape mode may be selected by the manufacturer or users of a portable device such as a PDA.
    [40] 6 is a diagram illustrating a circuit for controlling a memory device according to an exemplary embodiment of the present invention. The clock buffer 210 receives and buffers the external clock ECLK to provide the buffered clock ECLK1 to the DLL enable circuit 320. The power down entry / exit command (PWDN) is received by the logic circuitry in the DLL enable circuit 3200. The power down exit mode selection signal PD operates the power down entry / exit command PWDN and NAND to operate the DLL. It is input to the logic gate 322 which outputs the enable signal DLL_EN. The DLL enable signal DLL_EN is input to another logic circuit, in this case, the AND gate 324. The other of the AND gate 324. The input is the buffered clock ECLK1 The DLL enable signal DLL_EN is connected to the DLL circuit 230.
    [41] For convenience of explanation, the power down entry command PWDN is set to logic "1" and the power down escape command PWDN is set to logic "0". Fast wake-up escape mode is selected when power down escape mode select signal PD is logic " 0 ", and slow wake-up (power saving) escape mode when power down escape mode select signal PD is logic " 1 " Is selected. When both the power down exit mode select signal PD and the power down enter command PWDN are "1", i.e., enter power down and slow wake-up exit mode, the DLL enable signal DLL_EN is a logic "0". &Quot; disables the gate 324 and the buffered clock ECLK1 is also blocked so that the ECLK2 signal remains logic " 0 ". Accordingly, the internal clock ICLK by the DLL circuit 230 is not generated. The memory core 100 is placed in a power down or standby mode.
    [42] According to a preferred embodiment of the present invention, the DLL enable signal DLL_EN is also used to turn off circuits in the DLL circuit 230 to further reduce the overall power consumption of the memory device. According to another embodiment, the DLL enable signal DLL_EN is used as an additional power down signal SPD to turn off other internal circuits such as buffers and drivers to save more power. To exit the power down mode in the SDRAM, the DLL circuit 230 takes a long time (about 6 clock cycles) to lock the phase and generate an internal clock ICLK.
    [43] According to this embodiment, when in the power down escape mode, the power down escape command PWDN is logic " 0 " so that the internal clock ICLK is always turned on regardless of the power down escape mode select signal PD. When the power down escape command PWDN is logic "1" in the power down entry mode, the fast power down escape mode is selected when the power down escape mode select signal PD is logic "0" and the DLL circuit 230 is selected. Is always on. In this power down escape situation, the power down escape is fast (e.g., two clock cycles). The DLL enable signal DLL_EN is preferably not used to turn off other circuits such as clock buffers or data buffers in fast wake-up exit mode.
    [44] The logic gates 322, 324 used in the DLL enabling circuit 320 can be replaced with equivalent circuits thereof, and the activating / deactivating logic to perform the same functions described in the DLL enabling circuit 320. It will be apparent to one skilled in the art that this can be reversed. In addition, the DLL circuit 230 represents a feedback circuit that requires a certain locking time to perform synchronization, such as PLL, DLL, DCC (duty cycle correction circuit). Although in this embodiment two clock cycles and six clock cycles were used for the fast escape mode and the power save mode, respectively, two to four clock cycles were used for the fast wake-up escape mode, and at least five for the power save mode. Clock cycles, 6 to 8 clock cycles may be used. It is also apparent to those skilled in the art.
    [45] FIG. 7A illustrates a timing diagram of a memory device escaping power down in a slow or power saving wake-up mode. At the C1 clock, the power down escape mode select signal PD transitions to logic " 1 " from the A12 address via the mode register 350. After the C3 clock, the power down escape command (PWDN) becomes a logic "1" to indicate power down entry. In this clock cycle, the DLL enable signal DLL_EN transitions to logic " 0 " to disable the internal clock signal ICLK and the DLL circuit 230. After the C6 clock, when the power down escape command PWDN of logic " 0 " is received and the DLL enable signal DLL_EN is changed to logic " 1 ", the DLL circuit 230 is connected to an external clock ECLK and an internal clock. ICLK) is enabled to synchronize. During this period, that is, 6, 8 or 10 clock cycles, the memory device is inaccessible up to the C12 clock, where the internal clock ICLK is synchronized with the external clock ECLK.
    [46] Referring to FIG. 7B, which is a timing diagram of the fast wake-up escape mode, a logic “0” at address A12 at C1 clock is read from the mode register 350, and the power down escape mode select signal PD is always at logic “0”. Is in a state. At C3 clock, a power down entry command (PWDN) of logic "1" comes in. Here, the DLL enable signal DLL_EN maintains a logic " 1 ", and the clock signal generated from the DLL circuit 230 remains locked. The internal clock ICLK remains active to drive the memory core 100. Subsequently, when the power down escape command (PWDN) becomes logic " 0 " at C6 clock, an active, read or write command is initiated at C8 clock two clock cycles later.
    [47] 8 is a diagram illustrating a memory device according to another exemplary embodiment of the present invention. In this embodiment, the memory device 10 is driven by the memory controller 20, as described in FIG. Instructions, address fields, and external clocks provided from the outside are provided through the memory controller 20. The memory controller 20 is a well known controller for controlling the SDRAM.
    [48] According to embodiments of the present invention, when the memory device exits the power down mode from the normal mode, the wake-up time and the power consumption of the memory device are selected. This selection is based on the power down escape information stored in the mode register (MRS). When power savings in SDRAM are required, like handhelds, slow wake-up and power saving modes are selected. If a memory device such as SDRAM is used in a high performance computer that requires fast wake-up, a fast wake-up power down exit mode is selected.
    [49] While the embodiments of the present invention are described, the embodiments are merely illustrative, and the spirit or scope of the present invention is not limited thereto. Embodiments apply not only to SDRAM but also to memory devices or semiconductor integrated circuits having DLL circuits. Although the power down escape information is stored in the A12 address field of the mode register (MRS) as an example, it may be stored in another address field of the MRS according to user definition. In addition, although the wake-up time of the DLL circuit stored in the MRS is set to 2/6 clock cycles, the wake-up time may vary. The power down exit information may be used to control the operation of the active phase termination circuit (ODT) in the SDRAM as well as the operation of the phase locked circuit (PLL). Accordingly, various modifications and changes may be made without departing from the spirit and scope of the invention.
    [50] According to the present invention described above, the wake-up time and power consumption of the memory device are selected when the memory device exits from the power down mode to the normal mode. This selection is based on the power down escape information stored in the mode register (MRS). When power savings in SDRAM are required, like handhelds, slow wake-up and power saving modes are selected. If a memory device such as SDRAM is used in a high performance computer that requires fast wake-up, a fast wake-up power down exit mode is selected. Therefore, the memory device of the present invention can select various power saving modes.
    权利要求:
    Claims (24)
    [1" claim-type="Currently amended] A memory control circuit for controlling a memory having a plurality of memory cells arranged in rows and columns, the memory control circuit comprising:
    At least one address decoder for decoding an address field to output a decoded address for addressing the memory; And
    And a mode register for storing mode register set (MRS) data used to specify at least one of a plurality of operating modes of the memory device including a plurality of power down exit modes based on the address field. Memory control circuit.
    [2" claim-type="Currently amended] The memory control circuit of claim 1, wherein the memory control circuit comprises:
    A clock generator for generating an internal clock signal synchronized with an external clock signal to clock the memory; And
    And a clock generator enable circuit for directly or indirectly receiving the external clock signal and the power down command to selectively enable the output of the external clock signal to the clock generator based on a power down command. And a memory control circuit.
    [3" claim-type="Currently amended] 3. The clock generator of claim 2, wherein the clock generator enable circuit
    And selectively enable the power down command by receiving a power down escape mode selection signal that selects at least one of the power down escape modes.
    [4" claim-type="Currently amended] The method of claim 2, wherein the plurality of power down escape mode is
    And a slow wake-up escape mode and a fast wake-up escape mode.
    [5" claim-type="Currently amended] The memory device of claim 4, wherein the memory device
    Operate in a normal mode within a first clock cycle number after receiving the slow wake-up escape mode and within a second clock cycle number less than the first clock cycle number after receiving the fast wake-up escape mode. Memory control circuit.
    [6" claim-type="Currently amended] The method of claim 5,
    And the first clock cycle number is at least five and the second clock cycle number is at least two.
    [7" claim-type="Currently amended] 3. The clock generator of claim 2, wherein the clock generator enable circuit
    And receiving the power down escape mode selection signal to generate an additional power down signal for powering down a circuit other than the memory cells.
    [8" claim-type="Currently amended] 8. The circuit of claim 7, wherein circuitry other than the memory cells is
    And at least a clock generator portion.
    [9" claim-type="Currently amended] The method of claim 3,
    The address field includes A0 to A12,
    And the power down escape mode selection signal is any one of an A8 to A12 address field.
    [10" claim-type="Currently amended] The memory device of claim 1, wherein the memory device
    A memory control circuit, characterized in that the SDRAM.
    [11" claim-type="Currently amended] The memory device of claim 1, wherein the memory device
    Memory control circuit, characterized in that the DDR SDRAM.
    [12" claim-type="Currently amended] The clock generator of claim 2, wherein the clock generator
    And a phase locked circuit (PLL).
    [13" claim-type="Currently amended] The clock generator of claim 2, wherein the clock generator
    A memory control circuit comprising a delay synchronization circuit (DLL).
    [14" claim-type="Currently amended] The clock generator of claim 2, wherein the clock generator
    And a duty cycle correction circuit (DCC).
    [15" claim-type="Currently amended] The method of claim 2, wherein the address field and the power down command is
    And a memory control circuit provided from the memory controller.
    [16" claim-type="Currently amended] A memory control system for controlling a memory device having an array of memory cells arranged in rows and columns, the memory control system comprising:
    At least one address decoder that decodes an address field and outputs decoded addresses addressing the memory device;
    A mode register for storing mode register set (MRS) data specifying at least one of a plurality of operating modes of the memory device including a plurality of power down exit modes based on the address field; And
    And a memory controller providing signals for generating the address field and the mode register (MRS).
    [17" claim-type="Currently amended] 17. The system of claim 16, wherein the memory control system is
    A clock generator for generating an internal clock signal synchronized with an external clock signal to clock the memory device; And
    And a clock generator enable circuit for directly or indirectly receiving the external clock signal and the power down command to selectively enable the output of the external clock signal to the clock generator based on a power down command. Memory control system, characterized in that.
    [18" claim-type="Currently amended] 18. The circuit of claim 17, wherein the clock generator enable circuit
    And selectively enable the power down command by receiving a power down exit mode selection signal that selects at least one of the power down exit modes.
    [19" claim-type="Currently amended] A memory control circuit of a memory device having an array of memory cells arranged in rows and columns, the memory control circuit comprising:
    At least one address decoder that decodes an address field and outputs decoded addresses addressing the memory device; And
    And a logic circuit for receiving a signal specifying at least one of a plurality of operating modes of the memory device including a plurality of power down exit modes based on the address field.
    [20" claim-type="Currently amended] 20. The system of claim 19, wherein the memory control circuit is
    A clock generator which generates an internal clock signal synchronized with an external clock signal to clock the memory device; And
    And a clock generator enable circuit for directly or indirectly receiving the external clock signal and the power down command to selectively enable the output of the external clock signal to the clock generator based on a power down command. And a memory control circuit.
    [21" claim-type="Currently amended] 21. The circuit of claim 20, wherein the clock generator enable circuit
    And selectively enable the power down command by receiving a power down escape mode selection signal that selects at least one of the power down escape modes.
    [22" claim-type="Currently amended] A control method of a memory device having an array of memory cells arranged in rows and columns, the method comprising:
    Decoding the address field and outputting decoded addresses addressing the memory device; And
    Based on the address field, storing mode register set (MRS) data used to specify at least one of a plurality of operating modes of the memory device including a plurality of power down exit modes. Memory device control method.
    [23" claim-type="Currently amended] The method of claim 22, wherein the memory device control method is
    Generating an internal clock signal synchronized with an external clock signal through a clock generator to clock the memory device; And
    And disabling the clock generator based on a power down command and one of the plurality of power down exit modes.
    [24" claim-type="Currently amended] The method of claim 22, wherein the memory device control method is
    And allocating a power down escape mode selection signal for selecting one of the plurality of power down escape modes to any one bit of the address field.
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    US6489823B2|2002-12-03|Semiconductor device capable of generating highly precise internal clock
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    同族专利:
    公开号 | 公开日
    KR100521365B1|2005-10-12|
    EP1381053B1|2013-02-13|
    TW200414217A|2004-08-01|
    CN100424784C|2008-10-08|
    EP1381053A3|2006-05-24|
    EP1381053A2|2004-01-14|
    CN1485858A|2004-03-31|
    JP4195835B2|2008-12-17|
    TWI236022B|2005-07-11|
    JP2004047066A|2004-02-12|
    US6650594B1|2003-11-18|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-07-12|Priority to US39527602P
    2002-07-12|Priority to US60/395,276
    2002-10-28|Priority to US10/281,342
    2002-10-28|Priority to US10/281,342
    2002-12-06|Application filed by 삼성전자주식회사
    2004-01-24|Publication of KR20040007203A
    2005-10-12|Application granted
    2005-10-12|Publication of KR100521365B1
    优先权:
    申请号 | 申请日 | 专利标题
    US39527602P| true| 2002-07-12|2002-07-12|
    US60/395,276|2002-07-12|
    US10/281,342|US6650594B1|2002-07-12|2002-10-28|Device and method for selecting power down exit|
    US10/281,342|2002-10-28|
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