• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for fabricating an embedded memory device is provided to obtain simultaneously a data reserve function of a flash element and a data storage function of a mask cell by integrating the flash element and the mask cell on the same substrate. CONSTITUTION: An isolation layer is formed on a semiconductor substrate(32). A well for a mask cell, a flash cell, a high voltage transistor, and a low voltage transistor is formed on the semiconductor substrate(32). A channel region of the mask cell and a source region for the flash cell are defined. Impurities are implanted into the channel region of the mask cell and the source region for the flash cell. A gate oxide layer(44) of the high voltage transistor is formed. The flash cell and a gate oxide layer of the low voltage transistor are formed. A floating gate(52a) of the floating cell is formed. A conductive layer for gate is formed on a high voltage transistor region and a low voltage transistor region. An insulating layer and a control gate are formed on the floating gate(52a). The mask cell and the gates(52b,52c,52d,52e) of the high and the low voltage transistors are formed. Each source/drain(66,68,70) of the flash cell and the high and the low voltage transistors is formed.
    公开号:KR20040007144A
    申请号:KR1020020041802
    申请日:2002-07-16
    公开日:2004-01-24
    发明作者:민윤홍
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Method for fabricating an embedded memory device
    [3] The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to provide a method of manufacturing an embedded memory device in which a flash memory device and a mask cell are integrated on the same substrate to simplify a process.
    [4] Flash memory devices, which are a kind of nonvolatile memory devices, are increasingly being demanded due to the recent growth of the portable electronics market due to their nonvolatile characteristics. Mask cell products are also commonly used in MCUs (main control units) or controllers.
    [5] 1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional flash memory device.
    [6] Referring to FIG. 1A, a field oxide film 4 for device isolation is formed on the surface of a semiconductor substrate 2 using a conventional device isolation process. The semiconductor substrate is formed on the semiconductor substrate using a photographic process, an ion implantation process, and a heat treatment process. N wells 6 and P wells 8 are formed. A low voltage PMOS transistor and a high voltage PMOS transistor are formed in the N well 6, and a flash memory device, a low voltage NMOS transistor, and a high voltage NMOS transistor are respectively formed in the P well 8.
    [7] Next, an oxide film is formed on the semiconductor substrate and then etched to form a gate oxide film 10 of a high voltage transistor. The photoresist pattern 12 defining the flash cell, low voltage NMOS and PMOS transistor regions is formed using a photolithography process, and then the gate oxide film in the exposed region is removed. Therefore, the gate oxide film 10 remains only in the high voltage region.
    [8] Referring to FIG. 1B, the tunnel oxide layer 14 is formed by removing the photoresist pattern and forming a thin oxide layer on the exposed semiconductor substrate. Next, a doped first polysilicon film is formed on the entire surface of the semiconductor substrate, and then a photolithography process is performed to form the floating gate 16a of the flash device. At this time, the gate first polysilicon film 16 is formed in the region where the high voltage and low voltage transistors are to be formed.
    [9] Next, in order to prevent electrons from leaking from the floating gate to the control gate, an insulating film 18 having an oxide film / nitride film / oxide film structure is formed on the semiconductor substrate on which the floating gate is formed. Next, a doped second polysilicon film is formed on the entire surface of the semiconductor substrate, and then the control gate 20 of the flash cell is formed by removing the second polysilicon film and the insulating layer in all regions except the flash cell by a photolithography process. do.
    [10] Referring to FIG. 1C, a doped polysilicon film and tungsten silicide (WSi) are deposited to form a conductive layer (not shown), and then an oxynitride film ( oxynitride) to form an antireflection film (not shown). Subsequently, a photolithography process is performed to form gates 16b, 16c, 16d, and 16e of the high voltage and low voltage transistors. At this time, the control gate 20 of the flash cell is also patterned. Subsequently, only the flash cell region is opened by the photolithography process, and then the insulating layer 18 and the floating gate 16a of the exposed region are etched using the control gate as a mask.
    [11] Referring to FIG. 1D, the source / drains 22, 24, and 26 of the flash cell, the high voltage and the low voltage transistors are formed using conventional ion implantation and heat treatment processes, respectively. At this time, a source / drain 22 having an LDD structure is formed in the flash cell. An oxide film is deposited on the entire surface of the resultant and then planarized to form an interlayer insulating film 28, and a photolithography process is performed to form contact holes. Thereafter, the normal process is continued to complete the device.
    [12] Existing portable products such as mobile phones and PDAs implement SRAM and flash chips separately, which increases the area occupied by the product, which increases the consumption of power, as well as the trend toward miniaturization and slimming. In fact, the products made by the SRAM process because the characteristics of the SRAM device must be implemented with four or six transistors to complete the chip, SRAM products using the same design rule process is less storage capacity. In addition, in the process of etching the floating gate using the control gate as a mask, there is a problem in that charge retention characteristics are deteriorated due to side attack of the tunnel oxide layer.
    [13] The present invention is to solve the above problems of the prior art, the technical problem to be achieved by the present invention, an embedded memory that can reduce the area of the device without reducing the characteristics of the device and simplify the manufacturing process It is to provide a method for manufacturing a device.
    [1] 1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional flash memory device.
    [2] 2A to 2F are cross-sectional views briefly illustrating a method of manufacturing an embedded memory device according to the present invention.
    [14] According to an aspect of the present invention, there is provided a method of manufacturing an embedded memory device, including forming an isolation layer on a semiconductor substrate, and forming a well on which a mask cell, a flash cell, a high voltage and a low voltage transistor are formed on the semiconductor substrate. Defining a region where a channel of the mask cell is to be formed and a region where the source of the flash cell is to be formed, implanting impurities into the limited region of the mask cell and the flash cell, and forming a gate oxide film of the high voltage transistor Forming a gate oxide film of the flash cell and the low voltage transistor; forming a floating gate of the flash cell; forming a gate conductive layer in the high voltage and low voltage transistor regions; and forming a gate conductive layer on the floating gate. An insulating film and a control gate are formed, and the mask cell and the high voltage And forming a gate of the low voltage transistor, and forming a source / drain of the flash cell, the high voltage and the low voltage transistor.
    [15] Here, in the forming of the gate oxide film of the high voltage transistor, the implanted channel is also oxidized while the buried channel is formed in the mask cell and the flash cell. In the forming of the gate oxide film of the high voltage transistor, an oxide film of about 3,500 to 4,000 kV is formed in a region in which impurities of the mask cell and the flash cell are injected.
    [16] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [17] 2A to 2F are cross-sectional views briefly illustrating a method of manufacturing an embedded memory device according to the present invention.
    [18] Referring to FIG. 2A, a field oxide film 34 is formed on the surface of the semiconductor substrate 32 to define active and inactive regions, for example, using a conventional device isolation process such as selective oxidation (LOCOS). And the N well 36 and the P well 38 are formed on the semiconductor substrate by using an ion implantation and heat treatment process. A low voltage PMOS transistor and a high voltage PMOS transistor are formed in the N well 36, and a mask cell, a flash device, a low voltage NMOS transistor, and a high voltage NMOS transistor are respectively formed in the P well 38. In particular, the region in which the flash device and the high voltage NMOS transistor are formed is formed in a triple P-well structure. In the subsequent oxidation process, impurities in the P well, for example, boron (B), are diffused into the oxide film to reduce the impurity concentration of the P well, thereby reinforcing the problem of weak field transistor characteristics. It is preferable to perform a field ion implantation process.
    [19] Referring to FIG. 2B, an oxide film is formed on the semiconductor substrate to form a pad oxide film 40. On the semiconductor substrate, a photoresist pattern 42 is formed using a pattern for forming a buried channel, which serves as a bit line of a mask cell and insulates the cells. At this time, the region exposed by the photoresist pattern 42 becomes a region where the buried channel of the mask cell is to be formed and a source region of the flash element. Next, an N-type impurity, for example, an As, is implanted into the exposed semiconductor substrate using the photoresist pattern 42 as a mask at a dose of 2.0 × 10 15 ions / cm 2 and a voltage of 50 KeV. do. The impurities implanted in this way diffuse into the substrate to form a buried N-channel in a subsequent oxide film forming process, thereby reducing the contact line of the mask cell, and supplying a power voltage (Vcc) and a ground line through the buried N-channel. Is formed.
    [20] Referring to FIG. 2C, the buried N-channel photoresist pattern is removed, and then annealing is performed at a predetermined temperature in order to remove damage in the ion implantation process. Next, a low voltage using a photolithography process and an ion implantation process is performed. And a step for adjusting the threshold voltage of the high voltage transistor. At this time, it is preferable to also perform a cleaning process to remove the particles (particles) generated when the buried channel is formed.
    [21] Subsequently, the semiconductor substrate is oxidized to form a gate oxide film 44 of a high voltage transistor. The high voltage gate oxide film 44 is used as a gate oxide film of a transistor for pumping or transitioning a high voltage used in a data program or erase of a cell. The high-voltage gate oxide film 44 is formed to a thickness of about 150 kW. At this time, the region implanted for forming the buried N-channel is rapidly oxidized to form an oxide film 46 of about 3,500 to 4,000 kW. In this oxidation process, impurities implanted at a high concentration diffuse into the bulk of the semiconductor substrate to form a buried N-channel 48 under the oxide film 46.
    [22] Referring to FIG. 2D, the photolithography process is performed to form a photoresist pattern exposing regions other than the high voltage transistor region, that is, the mask cell region, the flash cell region, and the low voltage transistor region. Using the photoresist pattern as a mask, the high voltage gate oxide film in the exposed region is etched and removed. In this etching process, the oxide film 46 formed on the buried N-channel is partially etched, leaving only about 1,300 to 1,500 Å.
    [23] Next, after removing the photoresist pattern, the semiconductor substrate is cleaned using a predetermined cleaning solution, and then oxidized to form a tunnel oxide film 50 having a thickness of about 100 kV in the exposed region. A low voltage gate oxide film is formed in the flash cell and the low voltage region. The tunnel oxide film 50 is an oxide film of a floating gate, that is, a cell gate, and film quality is very important. The reason is that the tunnel oxide film can easily pass electrons in data programming, but can act as a barrier so that once charged electrons can not escape, the charged electrons of the floating gate must be kept constant and erased. The poem must be able to escape all of the electrons at once.
    [24] The cleaning and oxidation process is performed in a state where the high voltage gate oxide film 44 is exposed.
    [25] Next, a polysilicon film is deposited on the resultant and then doped. The doped polysilicon film is anisotropically etched to form a floating gate 52a of the flash device. At this time, the gate first polysilicon film 52 is formed in the region where the high voltage and low voltage transistors are to be formed.
    [26] Subsequently, in order to prevent electrons from leaking from the floating gate to the control gate, an insulating film 54 having an oxide film / nitride film / oxide film structure is formed on the semiconductor substrate on which the floating gate 52a is formed. In order to perform such a barrier role, a thermal oxide film is best, but since the floating gate 52a is doped, it must be deposited by chemical vapor deposition (CVD). In particular, the thickness of the uppermost oxide film of the ONO insulating film 54 is about 30 to 40 kPa in order to prevent leakage current caused by holes, which are the main cause of the dielectric breakdown of the oxide film. In order to improve the film quality of the ONO insulating film 54 and to strengthen the bonding between the films, the wet oxidation process is performed.
    [27] Next, a doped polysilicon film is deposited on the entire surface, and then patterned to form a control gate 56a of the flash device and a gate 56b of the mask cell.
    [28] On it, a doped polysilicon film 58 and tungsten silicide (not shown) are deposited. Subsequently, an oxynitride is deposited on the entire surface of the resultant to facilitate the subsequent photographic process to form the antireflection film 60. On the anti-reflection film 60, a photoresist pattern 62 for patterning the gate of each transistor is formed.
    [29] Referring to FIG. 2E, the tungsten silicide, the third polysilicon film, the second polysilicon film, and the gate first polysilicon film are sequentially patterned by a photolithography process using the photoresist pattern as a mask, and gate electrodes 52b of the transistors. , 52c, 52d, 52e), respectively. In the mask cell region, the mask cell line 56b is formed in the word line direction, and the control gate 56a is defined in units of cells in the flash device region. After removing the photoresist pattern, a photoresist pattern 64 exposing the flash device region is formed.
    [30] Referring to FIG. 2F, the ONO insulating layer 54 and the floating gate 52a of the exposed region are etched using the photoresist pattern exposing the flash element region as a mask to be limited in units of cells. This etching process is self-aligned using the control gate 56a as a mask. When the insulating layer 54 is etched, the oxide layer formed on the buried N-channel of the flash cell region is also etched, leaving only a thickness of about 200 μm or less.
    [31] In order to recover the damage caused by the self-aligned etching and to prevent damage caused by ion implantation in the subsequent bonding layer forming process, reoxidation is performed at a predetermined temperature, for example, 900 ° C. and oxygen (O 2 ) atmosphere. .
    [32] Next, the photo process and the ion implantation process are performed in order to form the source / drain 68 and 70 of the high voltage transistor and the source / drain 66 of the flash element, respectively. Next, the photolithography process and the ion implantation process are performed to encode the mask cell into a desired pattern. Subsequently, the interlayer insulating film formation, planarization, contact forming step, and subsequent steps are performed in a conventional manner to complete the device.
    [33] According to the method of manufacturing the embedded memory device according to the present invention, the flash element and the mask cell may be integrated on the same substrate to simultaneously implement the data retention capability of the flash element and the data storage function of the mask cell. In addition, it is possible to significantly reduce the area of the cell compared to the memory device using a conventional SRAM and to manufacture a device having more storage capacity in the same area. In addition, by forming a buried channel when forming a conventional flash cell source, the metal line forming process can be reduced by one without adding a mask or a process, thereby simplifying a manufacturing process and further reducing a cell area. The present invention can be applied to various applications in the field of portable wireless communication such as a smart card using a MCU or a PDA mobile phone.
    [34] On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] Forming an isolation layer on the semiconductor substrate;
    Forming a well in which a mask cell, a flash cell, a high voltage and a low voltage transistor are to be formed on the semiconductor substrate;
    Defining an area where a channel of the mask cell is to be formed and an area where a source of the flash cell is to be formed;
    Implanting impurities into defined regions of the mask cell and the flash cell;
    Forming a gate oxide film of the high voltage transistor;
    Forming a gate oxide film of the flash cell and the low voltage transistor;
    Forming a floating gate of the flash cell, and forming a gate conductive layer in high and low voltage transistor regions;
    Forming an insulating film and a control gate on the floating gate, and forming gates of the mask cell and the high voltage and low voltage transistors; And
    And forming a source / drain of the flash cell, the high voltage and the low voltage transistor.
    [2" claim-type="Currently amended] The method of claim 1, wherein the forming of the gate oxide film of the high voltage transistor comprises oxidizing a region in which impurities are injected into the mask cell and the flash cell.
    [3" claim-type="Currently amended] 3. The method of claim 2, wherein an oxide film having a thickness of about 3,500 to 4,000 kV is formed in a region in which impurities of the mask cell and the flash cell are implanted.
    [4" claim-type="Currently amended] The method of claim 1, wherein the gate oxide film formed in the flash cell and the low voltage transistor region is removed before the gate oxide film of the flash cell and the low voltage transistor is formed.
    [5" claim-type="Currently amended] The insulating film of claim 1, wherein the insulating film is formed on the floating gate.
    A method of manufacturing an embedded memory device, characterized by forming an oxide film / nitride film / oxide film in a stacked structure.
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    同族专利:
    公开号 | 公开日
    KR100567024B1|2006-04-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-07-16|Application filed by 주식회사 하이닉스반도체
    2002-07-16|Priority to KR1020020041802A
    2004-01-24|Publication of KR20040007144A
    2006-04-04|Application granted
    2006-04-04|Publication of KR100567024B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020041802A|KR100567024B1|2002-07-16|2002-07-16|Method for fabricating an embeded memory device|
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