• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The semiconductor memory device of the present invention operates at a low operating voltage (for example, 1.8V) and includes a bit line discharge circuit for discharging the voltage of the bit line before the read / write operation is performed. The bit line discharge circuit is composed of high voltage and low voltage transistors connected in series between the bit line and the reference voltage. The high voltage transistor is switched on / off by a high voltage, and the low voltage transistor is switched on / off by a discharge signal.
    公开号:KR20030087674A
    申请号:KR1020020025515
    申请日:2002-05-09
    公开日:2003-11-15
    发明作者:이승근；임영호
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    LOW-VOLTAGE SEMICONDUCTOR MEMORY DEVICE
    [10] FIELD OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to low voltage semiconductor devices operating at low operating voltages (eg, about 1.8V).
    [11] Various electronic devices have been designed to be operated by a battery and have a small size for the convenience of movement. When using a battery instead of an AC power source, the power consumption of the electronic device must be considered considerably. This is because power consumption is closely related to the operation time of the electronic device. One way to increase the operating time of an electronic device is to increase battery capacity. However, to increase battery capacity, the battery size must be turned on. This is inconsistent with the miniaturization of the electronic device. Another way to increase the operating time of the electronic device is to lower the operating voltage (or power supply voltage) of the electronic device. When the electronic device operates at a low power supply voltage, the consideration of the operating speed of the electronic device is given. Therefore, even if the power supply voltage of the electronic device is lowered, a technique of preventing the operation speed of the electronic device from relatively decreasing is relatively important.
    [12] It is an object of the present invention to provide a low voltage semiconductor memory device capable of improving the operating speed under operating conditions of a low power supply voltage.
    [1] 1 is a circuit diagram illustrating a typical nonvolatile semiconductor memory device along a read path;
    [2] 2 is a block diagram illustrating a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention;
    [3] 3 is an operation timing diagram for explaining a bit line discharge operation of the nonvolatile semiconductor memory device according to the present invention; And
    [4] 4 is a block diagram illustrating a nonvolatile semiconductor memory device according to another exemplary embodiment of the present invention.
    [5] Explanation of symbols on the main parts of the drawings
    [6] 100: memory device 110: memory cell array
    [7] 120: row decoder circuit 130: column pass gate circuit
    [8] 140: column decoder circuit 150: sense amplifier and write driver circuit
    [9] 160: discharge circuit 170: discharge control circuit
    [13] According to an aspect of the present invention for achieving the above object, a semiconductor memory device comprises a bit line connected to a memory cell; A sense amplifier coupled to the bit line through a first transistor; And a discharge circuit connected to the bit line and discharging the voltage of the bit line in response to a discharge signal. The discharge circuit includes second and third transistors connected in series between the bit line and a first voltage, the gate of the second transistor is connected to a second voltage and the gate of the third transistor is connected to the discharge signal. It is connected. Here, the first voltage is a ground voltage and the second voltage is a voltage higher than a power supply voltage. Each of the first and second transistors is a high voltage transistor having a threshold voltage of about 0.9V, and the third transistor is a low voltage transistor having a threshold voltage of about 0.6V. In this embodiment, the semiconductor memory device operates at a power supply voltage of about 1.8V.
    [14] According to another feature of the invention, a nonvolatile semiconductor memory device comprises an array of memory cells, the array arranged in a number of word lines, a plurality of bit lines, and a matrix of the word lines and the bit lines Has a plurality of memory cells. The bit lines are divided into a plurality of input / output groups. The row select circuit selects at least one of the word lines in response to row address information, and the column select circuit selects one of the bit lines of each input / output group in response to column select information. The discharge control circuit generates discharge signals corresponding to the bit lines of the respective groups in response to the address transition detection information and the column address information. A discharge circuit discharges the voltages of the bit lines in response to the discharge signals. The discharge circuit includes a plurality of bit line discharge units respectively corresponding to the input / output groups of the bit lines. Each of the bit line discharge units consists of first and second transistors connected in series between a corresponding bit line and a ground voltage, the gate of the first transistor being connected to a voltage higher than a power supply voltage and of the second transistor. The gate is connected to receive the corresponding discharge signal. Here, the first transistor is composed of a high voltage transistor having a threshold voltage of about 0.9V, and the second transistor is composed of a low voltage transistor having a threshold voltage of about 0.6V. In this embodiment, the nonvolatile memory device operates at a power supply voltage of about 1.8V.
    [15] According to still another aspect of the present invention, a NOR flash memory device comprises: a memory cell array divided into a plurality of memory blocks; Each memory block comprises a memory cell array having a plurality of word lines, a plurality of local bit lines, and a plurality of memory cells arranged in a matrix form of the word lines and the local bit lines; The bit lines are divided into a plurality of segments; A plurality of global bit lines respectively corresponding to bit line segments of each memory block, and divided into a plurality of input / output groups; A plurality of first column select circuits respectively corresponding to the memory blocks, each of the plurality of first column selection circuits selecting one of the local bit lines of each segment in the corresponding memory block; A second column select circuit for selecting one of the global bit lines in each input / output group and connecting the selected global bit lines to corresponding data lines; A discharge control circuit for generating discharge signals in response to address transition detection information and the column address information; And a discharge circuit for discharging voltages of the global bit lines in response to the discharge signals. The discharge circuit includes a plurality of bit line discharge units corresponding to the input / output groups of the global bit lines, respectively; Each of the bit line discharge units includes first and second transistors connected in series between a corresponding global bit line and a ground voltage; And the gate of the first transistor is connected to a voltage higher than the power supply voltage and the gate of the second transistor is connected to receive a corresponding discharge signal.
    [16] DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings.
    [17] 1 is a diagram illustrating a circuit configuration forming a read path of a general nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device is, for example, a NOR flash memory device, which includes a memory cell MC, and the memory cell MC is implemented using a floating gate transistor. The floating gate transistor has a grounded source, a drain connected to the bit line, a floating gate, and a control gate connected to the word line WL. The bit line BL is connected to the sense amplifier SA and the write driver WD through the NMOS transistor M1, which is turned on / off according to the YA signal. An NMOS transistor M2 is connected as a discharge transistor between the bit line BL and the ground voltage GND, and the NMOS transistor M2 is turned on / off according to the DIS signal.
    [18] In the case of a NOR flash memory device, before a read / erase / program operation is performed, a bit line discharge operation is performed, which is performed through the NMOS transistor M2 controlled to the DIS signal. Then, in a read operation, the sense amplifier senses a voltage change of a bit line that varies according to a memory cell. In the program operation, the write driver supplies a voltage higher than the supply voltage (for example, 5V-6V) to the bit line. As is well known, the memory cells MC of a NOR flash memory device are programmed through hot electron injection and erased through F-N tunneling. Program and erase methods are described in U.S. Patent No. 6,347,053 entitled "Nonviolatile Memory Device Having Improved Threshold Voltages In Erasing And Programming Operations" and U.S. Pat. Patent No. 6,157,575, entitled "Nonvolatile Memory Device And Operating Method Thereof," respectively, incorporated by reference.
    [19] As described above, since a high voltage is applied to the bit line BL during the program operation, the transistors on the data input / output path refer to a transistor having a thick gate oxide film (hereinafter referred to as a “high voltage transistor”) so that high voltage immunity is increased. Should be implemented. That is, the NMOS transistors M1 and M2 of FIG. 1 are implemented using high voltage transistors.
    [20] Since the high voltage transistor uses a gate oxide film that is considerably thicker than the low voltage transistor, the threshold voltage (for example, 0.9 V) of the high voltage transistor is higher than the threshold voltage (for example, 0.6 V) of the low voltage transistor. When the NMOS transistor M2 for discharging the voltage of the bit line BL is constituted by a high voltage transistor, the time taken to discharge the bit line BL (hereinafter referred to as "bit line discharge time") is referred to as an NMOS transistor ( It becomes relatively longer than the bit line discharge time when M2) is constituted by the low voltage transistor. This phenomenon will worsen as the supply voltage is lowered. Increasing the bit line discharge time is one factor that lowers the operation speed. When the NMOS transistor M2 is configured as a low voltage transistor, breakdown occurs in the NMOS transistor when a high voltage is applied to the bit line. Therefore, the discharge transistor M2 must be composed of a high voltage transistor.
    [21] 2 is a block diagram illustrating a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention. Referring to FIG. 2, the nonvolatile semiconductor memory device 100 according to the present invention is a NOR flash memory device and includes a memory cell array 110. The memory cell array 110 includes a plurality of word lines WL0-WLi arranged in parallel in a row direction, and a plurality of bit lines BL00-BL0j- (BLx0-BLxj arranged in parallel in a column direction. And a plurality of memory cells MC arranged in intersection regions of word lines and bit lines, respectively. The bit lines arranged in the memory cell array 110 include a plurality of input / output groups BL00-BL0j, BL10-BL1j,... , (BLx0-BLxj).
    [22] 2, the word lines WL0-WLi are connected to the row decoder circuit 120, and the row decoder circuit 120 responds to the row address information RA. -WLi). Although not shown in the figure, the row decoder circuit 120 accepts a high voltage from a high voltage generator as a pump circuit and delivers the high voltage to the selected word line. The bit lines are connected to a column pass gate circuit 130, and the column pass gate circuit 130 bit of each input / output group in response to column select signals Y 0 -Y n output from the column decoder circuit 140. One of the lines is selected, and the selected bit lines are connected to corresponding data lines DL0-DLm, respectively. The data lines DL0-DLm are connected to the sense amplifier and the write driver circuit 150.
    [23] The column pass gate circuit 130 includes a plurality of column pass gate groups respectively corresponding to the data lines DL0-DLm (or input / output groups of bit lines). Each column pass gate group includes a plurality of NMOS transistors respectively corresponding to bit lines of a corresponding input / output group. For example, the column pass gate group corresponding to the data line DL0 includes NMOS transistors PTR00-PRT0j. The NMOS transistors PRT00-PRT0j are connected in parallel between the corresponding bit lines BL00-BL0j and the data line DL0, and are respectively turned on / off by corresponding column select signals Y0-Yn. Is off. The column pass gate group corresponding to the data line DL1 includes NMOS transistors PTR10 -PRT1j. The NMOS transistors PRT10-PRT1j are connected in parallel between the corresponding bit lines BL10-BL1j and the data line DL1, and are respectively turned on / off by corresponding column select signals Y0-Yn. Is off. Similarly, the column pass gate group corresponding to the data line DLm includes NMOS transistors PTRx0-PRTxj. The NMOS transistors PRTx0-PRTxj are connected in parallel between the corresponding bit lines BLx0-BLxj and the data line DLm, and are respectively turned on / off by corresponding column select signals Y0-Yn. Is off.
    [24] The NOR flash memory device 100 according to the present invention further includes a discharge circuit 160 and a discharge control circuit 170. The discharge circuit 160 is connected to bit lines of the input / output groups, and discharges voltages of the bit lines in response to discharge signals BLDIS0 to BLDISn from the discharge control circuit 170. The discharge circuit 160 is divided into discharge units corresponding to input / output groups of the bit lines, respectively, each discharge unit including a plurality of NMOS transistors. For example, the discharge unit corresponding to the first input / output group includes two NMOS transistors DTR00 and DTR01 connected in series between each bit line BL00-BL0j and the ground voltage of the first input / output group. The discharge unit corresponding to the second input / output group includes two NMOS transistors DTR10 and DTR11 connected in series between each bit line BL00-BL0j and the ground voltage of the second input / output group. The discharge unit corresponding to the last input / output group includes two NMOS transistors DTRx0 and DTRx1 connected in series between each bit line BLx0-BLxj and the ground voltage of the last input / output group.
    [25] Here, the NMOS transistors connected in series between each bit line and the ground voltage each include a high-voltage transistor and a low-voltage transistor. For example, an NMOS transistor whose drain is connected to a corresponding bit line is a high voltage transistor, and an NMOS transistor whose source is connected to a ground voltage is a low voltage transistor. Gates of the NMOS transistors DTR00, DTR10, ..., DTRx0 as high voltage transistors are connected to the high voltage Vpp. As the low voltage transistor, the NMOS transistors DTR01 of each discharge unit are each turned on / off by corresponding discharge signals BLDIS0-BLDISn. High voltage Vpp will be generated in the pump circuit although not shown in the figure.
    [26] The discharge control circuit 170 outputs discharge signals BLDIS0-BLDISn in response to the address transition detection information and the column address information. In this embodiment, the discharge signals BLDIS0-BLDISn all have a high level in the bit line discharge period. Then, the discharge signal corresponding to the selected bit line of the discharge signals BLDIS0-BLDISn is deactivated to the low level while the remaining discharge signals continue to maintain the high level. This means that the non-selected bit lines except for the selected bit line of each input / output group are connected to the ground voltage through corresponding high voltage and low voltage transistors.
    [27] 3 is an operation timing diagram illustrating a bit line discharge operation of the nonvolatile semiconductor memory device according to the present invention. As described above, before the read / write operation is performed, the voltages of the selected bit lines must be discharged during the previously performed read / write operation. In order to terminate the previous read / write operation and perform the next read / write operation, address information is changed, and the change of the address information is detected by the address transition detection circuit (not shown). The discharge control circuit 170 outputs discharge signals BLDIS0-BLDISn in response to the address transition detection information and the column address information.
    [28] In this embodiment, it is assumed that the first bit line of each input / output group is selected consecutively in previous and current read operations. According to this assumption, the voltage of the selected bit line must be discharged before the read operation is performed. To this end, the discharge control circuit 170 activates the discharge signal BLDIS0 corresponding to the selected bit line to the high level in response to the address transition detection information and the column address information. As the discharge signal BLDIS0 goes high, the voltage applied to the selected bit line (eg, BL00) in the previous read / write operation is transferred through the NMOS transistors DTR00 and DTR01 of the discharge circuit 160. Discharged. After the voltages of the selected bit lines are all discharged, the activated discharge signal BLDIS0 is inactivated to a low level. At this time, as shown in FIG. 3, the remaining discharge signals BLDIS1-BLDISn are continuously maintained at a high level. Thereafter, the read / write operation will be substantially performed according to a well-known method.
    [29] In the discharge circuit according to the present invention, high voltage and low voltage transistors are connected in series between the bit line and the ground voltage to discharge the voltage of the bit line. Here, since the gate of the high voltage transistor is fixed to the high voltage Vpp, the high voltage transistor is always turned on. Therefore, when the discharge signal corresponding to the selected bit line is activated, the bit line discharge time of the memory device according to the present invention is equal to the bit line discharge time of the device shown in FIG. 1, as shown in FIG. 3. By comparison, it is shortened by Δt. More specifically, it is as follows.
    [30] Since the discharge transistor M1 shown in FIG. 1 is a high voltage transistor, the voltage of the bit line is not discharged until the DIS signal reaches the V2 voltage (threshold voltage of the high voltage transistor). In other words, the discharge transistor M1 is not turned on. In contrast, in the case of the present invention, since the high voltage transistor is always turned on, the bit line voltage starts to discharge when the discharge signal BLDIS0 reaches the V1 voltage (threshold voltage of the low voltage transistor). As can be seen in FIG. 3, therefore, the bit line discharge time can be shortened by [Delta] t by using the discharge circuit 160 of the present invention. Shortening the bit line discharge time results in an improvement in operating speed.
    [31] 4 is a block diagram illustrating a nonvolatile semiconductor memory device according to another exemplary embodiment of the present invention.
    [32] Referring to FIG. 4, a nonvolatile semiconductor memory device includes a memory cell array, and the memory cell array includes a plurality of memory blocks MBLK0-MBLKm. Each memory block includes a plurality of word lines WL0_k-WLi_k arranged in parallel along the row direction, a plurality of local bit lines LBL0-LBLj arranged in parallel along the column direction, and word lines and bit lines. And a plurality of memory cells MC each arranged at intersection regions of the plurality of memory cells. Bit lines of the memory blocks are connected to corresponding first column select circuits 210_0-210_m. The first column select circuits 210_0-210_m are configured of a plurality of NMOS transistors PTR0a and PRT1a, and are odd-numbered among local bit lines LBL0-LBLj of the corresponding memory blocks MBLK0-MBLKm. Or select even-numbered bit lines and connect the selected local bit lines to corresponding global bit lines, respectively. For example, the first column selection circuit 210_0 may be an odd or even number among the local bit lines LBL0-LBLj of the first memory block MBLk0 in response to the corresponding column selection signals YA0_0 and YA1_0. Select local bit lines and connect the selected local bit lines to corresponding global bit lines (GBL0-GBLn), respectively.
    [33] The global bit lines GBL0-GBLn are connected to a second column select circuit 220, and the second column select circuit 220 includes a plurality of NMOS transistors PRT0b, PRT1b, and PRT2b. Some of the global bit lines GBL0-GBLn are selected in response to column select signals YB0-YB2. The selected global bit lines are connected to the sense amplifier and write driver circuit 230 through corresponding data lines DL0-DLx. Global bit lines GBL0-GBLn are also connected to a discharge circuit 240, which discharges voltages of the global bit lines (or global and local bit lines). The discharge circuit 240 includes NMOS transistors DTR10 and DTR12 connected in series between each global bit line and a ground voltage. One of the two NMOS transistors DTR10 and DTR12 corresponding to each global bit line DTR10 is a high voltage transistor, and the other DTR12 is a low voltage transistor. Gates of the high voltage transistors DTR10 are commonly connected to the high voltage Vpp. Gates of the low voltage transistors DTR12 are connected to corresponding discharge signals BLDIS0, BLDIS1, BLDIS2, respectively.
    [34] Since the bit line discharge operation of the memory device shown in FIG. 4 is performed similarly to that shown in FIG. 2, the description thereof is therefore omitted. It is apparent that the memory device illustrated in FIG. 4 may also have the same effect as described in FIG. 2. That is, as described above, since the high voltage transistor is always turned on, the voltages on the local and global bit lines start to discharge when the predetermined discharge signal reaches the V1 voltage (threshold voltage of the low voltage transistor). . Therefore, the bit line discharge time can be shortened by using the discharge circuit 240 of the present invention.
    [35] In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.
    [36] As described above, by discharging the voltage of the bit line using a high voltage transistor and a low voltage transistor connected in series between the bit line and the ground voltage, the bit line discharge time is shortened under operating conditions of a low power supply voltage. As a result, the operation speed may also be improved in proportion to the shortening of the bit line discharge time.
    权利要求:
    Claims (14)
    [1" claim-type="Currently amended] A bit line coupled to the memory cell;
    A sense amplifier coupled to the bit line through a first transistor; And
    A discharge circuit connected to the bit line and discharging a voltage of the bit line in response to a discharge signal;
    The discharge circuit includes second and third transistors connected in series between the bit line and a first voltage, the gate of the second transistor being connected to a second voltage and the gate of the third transistor being connected to the discharge signal. Connected semiconductor memory device.
    [2" claim-type="Currently amended] The method of claim 1,
    And the first voltage is a ground voltage and the second voltage is a voltage higher than a power supply voltage.
    [3" claim-type="Currently amended] The method of claim 1,
    Each of the first and second transistors comprises a high voltage transistor having a threshold voltage of about 0.9V and the third transistor comprises a low voltage transistor having a threshold voltage of about 0.6V.
    [4" claim-type="Currently amended] The method of claim 1,
    And the memory device operates at a power supply voltage of about 1.8V.
    [5" claim-type="Currently amended] A memory cell array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in a matrix form of the word lines and the bit lines;
    The bit lines are divided into a plurality of input / output groups;
    A row selection circuit for selecting at least one of the word lines in response to row address information;
    A column select circuit for selecting one of bit lines of each input and output grill in response to column select information;
    A sense amplifier circuit for sensing a voltage change of the bit lines selected by said column select circuit;
    A discharge control circuit for generating discharge signals corresponding to the bit lines of each group in response to address transition detection information and the column address information; And
    A discharge circuit for discharging voltages of the bit lines in response to the discharge signals, the discharge circuit including a plurality of bit line discharge units respectively corresponding to input / output groups of the bit lines; Each of the bit line discharge units includes first and second transistors connected in series between a corresponding bit line and a ground voltage; And a gate of the first transistor is connected to a voltage higher than a power supply voltage, and a gate of the second transistor is connected to receive a corresponding discharge signal.
    [6" claim-type="Currently amended] The method of claim 5,
    And the first transistor comprises a high voltage transistor having a threshold voltage of about 0.9V and the second transistor comprises a low voltage transistor having a threshold voltage of about 0.6V.
    [7" claim-type="Currently amended] The method of claim 5,
    And the memory device operates at a power supply voltage of about 1.8V.
    [8" claim-type="Currently amended] The method of claim 5,
    The memory device comprises a NOR flash memory device.
    [9" claim-type="Currently amended] The method of claim 5,
    And each of the first and second transistors comprises an NMOS transistor.
    [10" claim-type="Currently amended] A memory cell array divided into a plurality of memory blocks;
    Each memory block comprises a memory cell array having a plurality of word lines, a plurality of local bit lines, and a plurality of memory cells arranged in a matrix form of the word lines and the local bit lines;
    The bit lines are divided into a plurality of segments;
    A plurality of global bit lines respectively corresponding to bit line segments of each memory block, and divided into a plurality of input / output groups;
    A plurality of first column select circuits respectively corresponding to the memory blocks, each of the plurality of first column selection circuits selecting one of the local bit lines of each segment in the corresponding memory block;
    A second column select circuit for selecting one of the global bit lines in each input / output group and connecting the selected global bit lines to corresponding data lines;
    A discharge control circuit for generating discharge signals in response to address transition detection information and the column address information; And
    A discharge circuit for discharging voltages of the global bit lines in response to the discharge signals, the discharge circuit including a plurality of bit line discharge units respectively corresponding to input / output groups of the global bit lines; Each of the bit line discharge units includes first and second transistors connected in series between a corresponding global bit line and a ground voltage; And a gate of the first transistor is connected to a voltage higher than a power supply voltage, and a gate of the second transistor is connected to receive a corresponding discharge signal.
    [11" claim-type="Currently amended] The method of claim 10,
    And the first transistor comprises a high voltage transistor having a threshold voltage of about 0.9V and the second transistor comprises a low voltage transistor having a threshold voltage of about 0.6V.
    [12" claim-type="Currently amended] The method of claim 10,
    And the memory device operates at a power supply voltage of about 1.8V.
    [13" claim-type="Currently amended] The method of claim 10,
    The memory device comprises a NOR flash memory device.
    [14" claim-type="Currently amended] The method of claim 10,
    And each of the first and second transistors comprises an NMOS transistor.
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    同族专利:
    公开号 | 公开日
    US20030210581A1|2003-11-13|
    KR100423894B1|2004-03-22|
    JP2003331591A|2003-11-21|
    JP4184138B2|2008-11-19|
    US6781904B2|2004-08-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-05-09|Application filed by 삼성전자주식회사
    2002-05-09|Priority to KR20020025515A
    2003-11-15|Publication of KR20030087674A
    2004-03-22|Application granted
    2004-03-22|Publication of KR100423894B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20020025515A|KR100423894B1|2002-05-09|2002-05-09|Low-voltage semiconductor memory device|
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