• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The flip chip package has a substrate made of a material comprising an epoxy resin. The solder mask is one epoxy resin layer disposed on the top surface of the substrate. The solder mask has a plurality of openings that expose the conductive pattern formed on the smooth outer surface and the upper surface. The IC chip includes an active surface having a plurality of electrical contact pads. A plurality of solder bumps are each formed on each pad of the plurality of contact pads on the IC chip. The active surface of the IC chip is firmly attached to the outer surface of the soldering mask so that after the soldering process, each bump has a remainder completely received in each opening of the soldering mask and connected to the conductive pattern in the opening.
    公开号:KR20030085449A
    申请号:KR1020020028990
    申请日:2002-05-24
    公开日:2003-11-05
    发明作者:마아종-렌；치완-구오；차이밍-숭；샨웨이-헹
    申请人:울트라테라 코포레이션；
    IPC主号:
    专利说明:

    Improved flip chip package {AN IMPROVED FLIP CHIP PACKAGE}
    [13] The present invention relates to an encapsulated flip chip, and more particularly to a low cost flip chip package with high package reliability.
    [14] Flip chip technology is well known in the art for electrically connecting an integrated circuit (IC) to a printed circuit board or package. The process of forming a flip chip of one type includes forming a solder bump on an electrical interconnection pad on the active or front surface of the IC chip, attaching the active surface of the chip to the top surface of the substrate, and after the soldering process Using a solder bump to connect the contact pads on the active surface of the respective contact pads formed on the top surface of the substrate. Such flip chip packages described above often have a gap between the chip and the substrate due to the remainder of the solder bumps after the soldering process and bending of the substrate during its fabrication procedure. In order to strengthen the solder joint without affecting the electrical connection, the gap is usually underfilled with a polymeric material, sometimes referred to as an "underfill", which encloses the remainder of the solder bumps and fills all the space in the gap.
    [15] The need for underfill has several disadvantages. As an example, the elevated temperature and temperature cycling needed to cure the underfill can result in mechanical stress in the area of contact between the chip, underfill and the substrate. Many spaces will be formed during the underfilling process. Mechanical stresses and spacing are fatal to chip and solder interconnects. In addition, the underfill can increase the production cost and size, in particular the thickness of the package.
    [16] It is therefore a primary object of the present invention to provide an improved flip chip package without underfill.
    [17] It is yet another object of the present invention to provide an improved flip chip package with good heat dissipation properties and good electrical performance.
    [18] According to the principles of the present invention, the above object of the present invention is achieved by a flip chip package comprising a top and a bottom surface and a substrate member having a conductive pattern on at least one of the top and bottom surfaces. The substrate is made of a material comprising the first resin. The solder mask is made of a material comprising a second resin having a coefficient of thermal expansion substantially the same as the first resin of the substrate. A solder mask is disposed on the top surface of the substrate to have a smooth outer surface and a plurality of openings, each opening exposing a respective area of the conductive pattern of the substrate. The IC chip has an active side, an inactive side, and a plurality of electrical contact pads on the active side. A plurality of lead bumps are each formed on a pad of each of the plurality of contact pads on the IC chip. The active surface of the IC chip is directly attached to the outer surface of the soldering mask, so that after the soldering process, each bump has a remainder which is completely received in each opening of the soldering mask and connected to a conductive pattern in the opening. A molding material encapsulates the top surface of the chip and the substrate.
    [19] The above objects, features, and advantages of the present invention will be more readily understood upon consideration of the following detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings.
    [1] 1 is a side cross-sectional view of a flip chip package constructed in accordance with an embodiment of the invention.
    [2] FIG. 2 is an enlarged side view of a portion of the chip and substrate prior to being glued together according to the package shown in FIG.
    [3] 3 is a side cross-sectional view of a flip chip package constructed in accordance with another embodiment of the present invention.
    [4] 4 illustrates a method of forming a solder mask on a substrate in accordance with the present invention.
    [5] Explanation of symbols on the main parts of the drawings
    [6] 10; Package 12; IC chip
    [7] 14; Substrate 16; Molding material
    [8] 18; Active surface 20; Inactive
    [9] 22; Contact pads 24, 26; Conductive pattern
    [10] 30; Soldering mask 34; Opening
    [11] 36a; Residual portion 301; Metal foil
    [12] 303; Photo-resist layer
    [20] As shown in FIGS. 1 and 2, an embodiment of a package 10 according to the invention is shown. Package 10 includes IC chip 12, substrate 14, and molding material 16 encapsulate the chip and the substrate.
    [21] IC chip 12 has an active surface 18 and an inactive surface 20 that are planar and parallel to each other. A plurality of contact pads 22 are disposed on the active surface 18.
    [22] The substrate 14 has conductive patterns 24 and 26 on its upper and lower surfaces, respectively. The substrate 14 is typically made of a glass fiber reinforced epoxy resin layer. The conductive pattern 24 is electrically connected to the pattern 26 on the bottom surface from the top surface of the substrate 14 by a plurality of conductive vias 28. A plurality of solder balls 29 are each attached to respective regions of the conductive pattern 26 and attached to the circuit system.
    [23] The epoxy resin is applied to the upper surface of the substrate so that the space between the conductive patterns 24 and the conductive vias 28 are filled with an epoxy resin, and one conductive resin layer having a predetermined thickness acts as the solder mask 30. It is formed on (24). The method of forming the solder mask 30 is described in detail below.
    [24] Referring to FIG. 4A, a metal foil 301 (eg, copper or aluminum foil) coated with a partially cured (B-staged) epoxy resin layer 302 on one side Applied to the upper surface of the substrate 14, the layer 302 is sandwiched between the substrate 14 and the metal foil 301.
    [25] The coated metal foil 301 and the substrate 14 were laminated at a pressure of 10-40 kgw / cm 2 and a temperature of 140C o -185C o for 1.5 to 3 hours so that the epoxy resin layer 302 was cured. The substrate 14 is firmly covered.
    [26] The metal foil 301 surface is covered with a photo-resist layer 303 (as shown in FIG. 4 (B)). The photo-resist is photocured using a mask to ensure that only the location to be accessed remains uncured, and then the uncured areas of the photo-resist and the metal foil below it are removed with a suitable solvent to Exposing epoxy resin layer 302 (as shown in FIG. 4C).
    [27] Thereafter, the remaining (cured) portion of the photo-resist is removed with a suitable solvent (as shown in FIG. 4 (D)), and then the underlying epoxy resin 302 is removed by a plasma etching method. The conductive pattern 24a on the substrate is exposed (as shown in Fig. 4E).
    [28] Finally, the etching method is applied to remove the remaining metal foil 301, leaving the fully cured epoxy resin layer 302 as the solder mask 30 (as shown in FIG. 4 (F)).
    [29] The solder mask 30 produced by the method has a smooth outer surface 32, a thickness of 5 μm-30 μm (most preferred thickness is 15 μm), and a connection bump exposed below and exposing the conductive pattern 24a. It has a series of openings 34 for receiving.
    [30] A plurality of solder bumps 36 are each formed on each contact pad 22 of the chip 12. The chip 12 is positioned over the solder mask 30 on the substrate 14 using conventional automatic pick-and place equipment, so that the solder bumps 36 pass through the opening 34 to the substrate ( In contact with the corresponding conductive pattern 24 on the 14, the remaining portion 36a of the solder bump 34 is completely received in the opening 34 after the soldering process, and the outer surface 32 of the solder mask 30 is formed of a chip ( It is firmly attached by the active surface 18 of 12).
    [31] As shown in Fig. 3, a sectional view of an IC chip package 40 according to a second embodiment of the present invention. In this embodiment, the package 40 has molding material 42 around the circumference of the chip 12. The molding material 42 exposes an area of the inactive surface 20 of the chip 12 so that a thermally and electrically conductive layer 44, such as copper paste, may be filled thereon.
    [32] As described above, according to the IC chip package of the present invention, since the active surface of the chip is firmly attached to the smoothly formed outer surface of the soldering mask, that is, a gap between the active surface of the chip and the smoothly formed outer surface of the soldering mask. Since there is no, the prior art underfilling process is omitted. Therefore, the production cost of the IC chip package is significantly reduced and the thinnest IC chip package will be obtained.
    [33] Also, since the remainder of the solder bumps 36 can be fully received in the opening 34 after the soldering process, the tendency of the failure of solder joints between the IC chip and the substrate due to mismatching of the coefficient of thermal expansion will be reduced. . Therefore, the reliability of the IC package according to the present invention will be enhanced. Furthermore, because of having a thermally and electrically conductive layer 44 on the inactive side (top) 20 of the IC chip 12, the package provides more efficient heat dissipation and better electrical performance.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] In an improved flip chip package,
    A substrate member having an upper surface and a lower surface and a conductive pattern on at least one of the upper surface and the lower surface, the substrate member made of a material containing a first resin,
    Made of a material comprising a second resin having a coefficient of thermal expansion substantially the same as the first resin of the substrate, disposed on an upper surface of the substrate to form a smooth outer surface, the outer surface having a plurality of openings, The openings each being a solder mask that exposes each region of the conductive pattern of the substrate,
    An IC chip having an active surface, an inactive surface, and a plurality of electrical contact pads on the active surface,
    A plurality of solder bumps each formed on top of each of the plurality of contact pads on the IC chip, and
    Molding material encapsulating an upper surface of the chip and the substrate
    Including;
    The active surface of the IC chip is directly attached to the outer surface of the soldering mask, so that after the soldering process each of the bumps has a remainder which is completely received in each opening of the soldering mask and connected to a conductive pattern in the opening. .
    [2" claim-type="Currently amended] The method of claim 1,
    Wherein said molding material has an exposed area on an inactive side of an IC chip and a thermally and electrically conductive layer filled within said exposed area.
    [3" claim-type="Currently amended] The method of claim 2,
    And the thermally and electrically conductive layer is a copper paste.
    [4" claim-type="Currently amended] The method of claim 1,
    And a thickness of the solder mask is between 5μm-30μm.
    [5" claim-type="Currently amended] The method of claim 1,
    And a first resin of the substrate and a second resin of the soldering mask are epoxy resins.
    [6" claim-type="Currently amended] The method of claim 5,
    And the conductive vias are filled with an epoxy resin.
    [7" claim-type="Currently amended] The method of claim 1,
    The soldering mask is subjected to the following steps, i.e.
    Applying a metal foil having a partially cured (B-staged) epoxy resin layer on one side of the metal foil to the top surface such that the epoxy resin layer is sandwiched between the substrate and the metal foil,
    Laminating the metal foil and the substrate at a predetermined pressure and temperature for a period of time so that the epoxy resin layer is cured and firmly covers the substrate,
    Covering the photo-resist layer on the other side of the metal foil,
    Photocuring the positions of the photo-resist layer, removing the uncured area of the photo-resist and the metal foil underneath to expose the underlying epoxy resin layer,
    Removing the remaining (cured) portion of the photo-resist,
    Etching away the exposed epoxy resin layer to expose the conductive pattern to be soldered, and
    Removing the remaining metal foil and leaving the cured epoxy resin layer as a soldering mask
    Flip chip package disposed on the upper surface of the substrate by a method comprising a.
    [8" claim-type="Currently amended] The method of claim 7, wherein
    The metal foil is a copper foil flip chip package.
    [9" claim-type="Currently amended] The method of claim 7, wherein
    The metal foil is an aluminum foil flip chip package.
    [10" claim-type="Currently amended] The method of claim 7, wherein
    And a thickness of the solder mask is between 5μm-30μm.
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    同族专利:
    公开号 | 公开日
    TW550717B|2003-09-01|
    US20030201544A1|2003-10-30|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-04-30|Priority to TW91108921
    2002-04-30|Priority to TW091108921A
    2002-05-24|Application filed by 울트라테라 코포레이션
    2003-11-05|Publication of KR20030085449A
    优先权:
    申请号 | 申请日 | 专利标题
    TW91108921|2002-04-30|
    TW091108921A|TW550717B|2002-04-30|2002-04-30|Improvement of flip-chip package|
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