• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    PURPOSE: An output buffer of a semiconductor device is provided, which has good noise characteristics without speed delay by reducing a maximum current during an operation. CONSTITUTION: A control signal generator(100) generates a pulse signal which becomes active only during a constant interval including a time when read data is transferred. And a buffer(200) outputs by buffering the above read data, and is disabled when the above pulse signal is inputted. The buffering unit comprises a data transmission unit(210) buffering the read data according to a control signal being output from the control signal generator and includes an output driver(220) pulling up or pulling down an output signal of the data transfer part to an output port.
    公开号:KR20030084493A
    申请号:KR1020020023241
    申请日:2002-04-27
    公开日:2003-11-01
    发明作者:안흥준
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Output buffer of semiconductor device
    [10] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an output buffer circuit for receiving data and transmitting the same through an output pad.
    [11] 1 is a circuit diagram showing an output buffer according to the prior art.
    [12] Referring to FIG. 1, the output buffer includes a NAND gate NAND1 for receiving the inverted control signal CNTR and data DATA through the inverter INV1 and outputs the result of NAND combining, and a control signal CNTR. It is connected in series between the NOR gate NOR1 for outputting data by combining the NOR and the power supply voltage VDD and the ground, and is turned on according to the output signals of the NAND gate NOR1 and NOR1 NOR1, respectively. It consists of PMOS transistor PM1 and NMOS transistor NM1 which output an output signal at a connection point.
    [13] Referring to FIG. 1, the operation of the above-described output buffer circuit is described. First, the control signal CNTR is applied at a low potential so that the circuit outputs an output signal based on data.
    [14] At this time, when the data DATA is applied at a low potential, the NAND gate NAND1 and the NOR gate NOR1 are output at high potential to turn off the PMOS transistor PM1, turn on the NMOS transistor NM1, and The output signal OUT of the potential is outputted.
    [15] In addition, when the data DATA is shifted to a high potential and output, the output signals of the NAND gate NAND1 and the NOR gate NOR1 are output at a low potential to turn on the PMOS transistor PM1 and the NMOS transistor NM1. Turn off to output the high potential output signal OUT.
    [16] However, there is a case where both the PMOS transistor PM1 and the NMOS transistor NM1 are turned on at any moment when the states of the PMOS transistor PM1 and the NMOS transistor NM1 change, and at this time, the power supply voltage A current path is formed between the VCC and ground to generate noise and increase power consumption.
    [17] In order to solve this problem, a method of delaying the signal on the enabled side so that the NMOS transistor and the PMOS transistor is not turned on at the same time during data output is used to be input to the output buffer.
    [18] 2 is a circuit diagram illustrating an output buffer for reducing noise due to a peak current in the related art.
    [19] Referring to FIG. 2, the improved output buffer further includes first and second delay units 10 and 20 to have a predetermined delay time before the data signal is input to the output buffer of the output buffer of FIG. 1.
    [20] The first delay unit 10 is connected to each other in series, the four inverters (INV2 ~ INV5) for delaying the data (DATA), and the delayed data and non-delayed data (DATA) through the inverter (INV2 ~ INV5) And a NAND gate NAND2 for combining and outputting, and an inverter INV6 for inverting the output signal of the NAND gate NAND2.
    [21] The second delay unit 20 delays through the serially connected inverters INV7 to INV11 for delaying and inverting data DATA, the data DATA inverted through the inverter INV7 and the inverters INV7 to INV11. The NAND gate NAND3 receives the inverted data DATA and outputs the result of NAND combining.
    [22] Looking at the operation of the improved output buffer with reference to Figure 2, when data is input to the output buffer at a high potential, high potential data DATA is applied to one side of the NAND gate (NAND2) of the first delay unit 10 and The output signal of the NAND gate NAND2 changes when a high potential data DATA is delayed and applied through the inverters INV2 to INV5. As a result of the potential of the data DATA applied as described above, the NMOS transistor NM1 starts to be turned off while the PMOS transistor PM1 is turned off. When the operation is almost completed, the PMOS transistor PM1 is turned off. Is turned on.
    [23] In addition, when the data DATA transitions to the low potential again and is applied, the output signal of the NAND gate NAND2 of the first delay unit 10 directly receiving the low potential data DATA is an inverter chain ( Irrespective of the output signals from INV2 to INV5), the potential is changed to a high potential output signal and output. At this time, the high state data DATA inverted by the inverter INV3 is applied to one end of the NAND gate NAND3 of the second delay unit 20, and the previous state is applied through the inverters INV7 to INV11. When the low potential data is applied to the other input terminal to maintain the high potential, which is the output of the previous state, and the delayed high potential data DATA is applied through the inverters INV7 to INV11, the output signal is brought to the low potential. When the PMOS transistor PM1 is turned off, the off operation is started when the NMOS transistor is in an off state, and the NMOS transistor starts the turn-on operation when the off operation is almost completed.
    [24] Therefore, the PMOS transistor PM1 and the NMOS transistor, which form the output buffer by the first delay unit 10 and the second delay unit 2, are turned on at the same time, thereby reducing the time of turning on the PMOS transistor PM1 and the yen. The current caused by the power supply voltage VCC flowing to the ground through the MOS transistor NM1 can be reduced.
    [25] In this case, however, the enabled side is delayed, resulting in a speed delay as much as the delayed delay, resulting in a decrease in performance in the overall operation of the semiconductor device.
    [26] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having an output buffer which has a characteristic of being strong against noise by reducing the maximum current amount during operation and having no speed delay.
    [1] 1 is a circuit diagram showing an output buffer according to the prior art.
    [2] 2 is a circuit diagram showing an output buffer for reducing noise due to a peak current in the related art.
    [3] 3 is a block diagram showing an output buffer of a semiconductor device of a semiconductor device according to a preferred embodiment of the present invention.
    [4] 4 is a block diagram showing the control signal generating means of FIG.
    [5] FIG. 5A is a circuit diagram illustrating an embodiment of a read state detecting unit of FIG. 4. FIG.
    [6] FIG. 5B is a circuit diagram illustrating an embodiment of the pulse signal generator of FIG. 4. FIG.
    [7] Fig. 6 is a circuit diagram showing the pulse generator of Fig. 5B.
    [8] FIG. 7 is a circuit diagram showing a buffer portion of FIG. 3; FIG.
    [9] 8 to 11 are waveform diagrams showing the operation of the output buffer shown in FIG.
    [27] The present invention for achieving the above object is an output buffer control means for generating a pulse signal that is active for a predetermined period including a time point when the read data is transmitted; And a buffering means for buffering and reading the read data, and disabling the pulse data when the pulse signal is input.
    [28] Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.
    [29] 3 is a block diagram showing an output buffer of a semiconductor device according to an embodiment of the present invention.
    [30] Referring to FIG. 3, the output buffer of the semiconductor device according to the present exemplary embodiment includes a control signal generator 100 for generating a pulse signal do_diz that is activated during a predetermined period including a time point at which read data is transmitted. ) And a buffer unit 200 which buffers and reads the read data, and is disabled when a pulse signal do_hiz is input.
    [31] The buffering unit outputs a data transfer unit 210 for buffering the read data (data) in accordance with the control signal do_hiz output from the control signal generator 100 and an output driver for pulling up or pulling down the output signal of the data transfer unit to an output terminal. It consists of 220.
    [32] 4 is a block diagram illustrating a control signal generator of FIG. 3.
    [33] Referring to FIG. 4, the control signal generating means 200 is enabled by the address change detection signal atd_sum generated according to the state of an input address, and is generated when the word line selected by the address is enabled. The read state detection unit 110 outputs the line detection signal sg_sumb and the read signal read to enable the pulse signal do_hiz to the output signal of the read state detection unit 110, and outputs the output buffer. Reference numeral 200 includes a pulse generator 120 for disabling the pulse signal do_hiz by the control signal do_ctrl generated by the enable signal poe.
    [34] FIG. 5A is a circuit diagram illustrating an example of a read state detector of FIG. 4. FIG.
    [35] Referring to FIG. 5A, the read state detecting unit 110 receives a NAND gate I1 receiving the read signal and the reset detection signal reset_nq and an output of the NAND gate as a gate, and one side of which is connected to a power supply voltage. The transistors P1 and MOS transistors P2 and N1 connected to the other side of the PMOS transistor P1 and receiving an address change detection signal atd_sum through a gate and forming an inverter, and a power-up signal pwrup through a gate. Is a PMOS transistor (P3) connecting the node (node1) and the power supply voltage, the inverters (I3, I4) connected to the node (node1) to form a latch, the output of the inverter (I4) to the gate The MOS transistors P5 and N2 and the inverted precharge signal pcg are input to the gate, respectively, and the PMOS transistor P4 connected to one side of the power voltage supply unit and the PMOS transistor P5 is connected to each other. , On node (node2) Inverters (I5, I6) connected to form a latch, a power-up signal (pwrup) is input to the gate, the PMOS transistor (P6) for connecting the node (node2) and the power supply voltage, and the output of the inverter (I6) And a NAND gate I6 receiving the inverted word line detection signal sg_sumb.
    [36] 5B is a circuit diagram illustrating an embodiment of the pulse signal generator of FIG. 4.
    [37] Referring to FIG. 5B, the pulse generator 120 generates the NOR gate I10 receiving the inverted read signal read and the NAND gate I6 and the output of the NOR gate I10 as pulses. A pulse generator 121 for outputting the gate signal, a PMOS transistor P7 having one side connected to a power supply voltage supply terminal receiving an inverted control signal do_ctrl, and an output of the inverted pulse generator 121 as a gate. PMOS that receives the power-up signal (pwrup) through the input and the NMOS throttle (N3) connected to the other side of the PMOS transistor (P7) and the ground power supply, and the gate, and connects the node (4) and the power voltage supply. The transistors P8, inverters I13 and I14 connected to the node node4 to form a latch, and inverters I15 and I16 that buffer and output the output of the inverter I14 are configured.
    [38] FIG. 6 is a circuit diagram illustrating the pulse generator of FIG. 5B. The pulse generator shown in FIG. 6 is a pulse generator commonly used in the prior art. When an input signal A is input high, the NAND gate is in a period where both the signal delayed by the input inverter chains I20 to I80 and the input signal are high. The circuit generates a pulse by (I90).
    [39] FIG. 7 is a circuit diagram illustrating a buffer unit of FIG. 3.
    [40] Referring to FIG. 7, the buffer unit 200 may include a first NAND gate I33 for receiving a pulse signal do_hiz inverted to one side, an output buffer enable signal poe to the other side, and a first inverted side to one side. The output signal of one NAND gate I33, the second NAND gate I55 receiving the data data on the other side, and the output signal of the first NAND gate I33 on one side, and the data on the other side. NOR gate I66 receiving a signal, an output PU of the second NAND gate I55 as a gate, a MOS transistor P0 for transmitting a power supply voltage to an output pad, and an output of the NOR gate I66 It is composed of a MOS transistor (PD) for receiving the input to the gate to transfer the ground voltage to the output pad (PAD).
    [41] 8 to 10 are waveform diagrams showing the operation of the output buffer of FIG. 3 to 10, the operation of another output buffer in the present embodiment will be described.
    [42] 8 is a waveform showing the operation of the above-described output buffer during the read operation.
    [43] Referring to FIG. 8, when an address ADD is input to the semiconductor device, the chip select signal / CS is enabled low, and the storage enable signal / WE is disabled high, an address change detection is detected. The signal atd_sum is output in pulse form. The address change detection signal atd_sum is a signal output when the chip select signal / CS is enabled or an input address is changed. In response to the pulse of the address change detection signal atd_sum, the output of the inverter I6 of the read state detecting unit 110 of 5a changes to high. Here, the output of the inverter I6 remains high even when the address change detection signal atd_sum is inputted as a pulse due to the latch composed of the inverter paths I5 and I6.
    [44] Meanwhile, while the read signal read is high, the word line detection signal sg_sumb is input low and the output of the node node 3 is low, and the output of the north gate I10 is high. The pulse generator generates and outputs a pulse, which causes the final pulse signal do_hiz to be enabled (here high). The word line detection signal sg_sumb is a signal that is output after a state in which one word line selected due to an address input during read or write is enabled.
    [45] Thereafter, the pulse signal do_hiz is disabled by the control signal do_ctrl. The control signal do_ctrl is a signal controlled by the enable signal poe of the buffer unit 100 shown in Fig. 7, and the output buffer starts to export data to the outside from the time when this signal is activated.
    [46] In addition, the control signal reset_nq input to the read state detector 110 is a signal that resets the node node1 high whenever the input address is changed.
    [47] 9 is a waveform diagram showing the operation of the output buffer in the refresh state. In the refresh state, even if the address change detection signal atd_sum is input in a pulse form, the pulse signal do_hiz, which is the output of the pulse generator 120, should not be generated. In this case, even if the address change detection signal atd_sum is input, the pulse signal do_hiz is not generated because the read signal read is not enabled.
    [48] Fig. 10 is a waveform diagram showing the operation of the output buffer in the write state. The pulse signal do_hiz is not generated because the read signal read is not enabled even in the write state.
    [49] 11 is a waveform diagram showing that data is buffered and output in an output buffer of the present invention.
    [50] Referring to FIG. 11, when the pulse signal do_hiz generated by the pulse generation unit 120 is input to the buffer unit 200, even if data is input to the buffer unit 200, the PMOS transistor P0 and the ann The MOS transistor N0 can be turned off at the same time, reducing the current consumption due to the data output. The time for turning off the PMOS transistor and the NMOS transistor N0 is from the time when the word line detection signal sg_sumb is activated until the control signal do_hiz is activated. If the PMOS transistor P0 and the NMOS transistor N0 are turned off at the same time, the pad PAD is in a high impedance state Hi-Z Reaion.
    [51] As a result, the pulsed signal do_hiz prevents the PMOS transistor N0 and the NMOS transistor N0 of the buffer 200 from being turned on at the same time, and since no delay is used in the data path, current consumption is reduced. At the same time, the read operation can be completed without delay.
    [52] The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
    [53] In accordance with the present invention, it is possible to manufacture an output buffer of a semiconductor device without a time delay while reducing noise by reducing a peak current during operation, thereby manufacturing a reliable semiconductor device.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] Control signal generating means for generating a pulse signal that is activated during a predetermined period including a time point at which read data is transmitted; And
    Buffering means for buffering and outputting the read data, which is disabled when the pulse signal is input
    An output buffer of a semiconductor device having a.
    [2" claim-type="Currently amended] The method of claim 1,
    The buffering means
    A data transfer unit for buffering the read data according to a control signal output from the control signal generating unit; And
    And an output driver configured to pull up or pull down the output signal of the data transfer unit to an output terminal.
    [3" claim-type="Currently amended] The method of claim 1,
    The control signal generating means
    A read state detector configured to enable an address change detection signal generated according to a state of an input address and to turn on an output value by a word line detection signal;
    A pulse signal generation unit that is enabled by a read signal, enables the pulse signal by an output value of the read state detection unit, and is controlled by the output buffer enable signal to disable the pulse signal
    Output buffer of the semiconductor device comprising a
    [4" claim-type="Currently amended] The method of claim 1,
    The buffering means,
    A first NAND gate receiving the pulse signal inverted to one side and an output buffer enable signal to the other side;
    A second NAND gate receiving an output signal of the first NAND gate inverted to one side and the data signal to the other side;
    A NOR gate receiving an output signal of the first NAND gate to one side and the data signal to the other side;
    A MOS transistor receiving the output of the second NAND gate as a gate and transferring a power supply voltage to an output pad; And
    And a morph transistor configured to receive the output of the NOR gate as a gate and transfer a ground voltage to an output pad.
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    同族专利:
    公开号 | 公开日
    KR100529397B1|2005-11-17|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-04-27|Application filed by 주식회사 하이닉스반도체
    2002-04-27|Priority to KR10-2002-0023241A
    2003-11-01|Publication of KR20030084493A
    2005-11-17|Application granted
    2005-11-17|Publication of KR100529397B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-2002-0023241A|KR100529397B1|2002-04-27|2002-04-27|Output Buffer of semiconductor device|
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