 Semiconductor device having wiring with holes therein, and manufacturing method thereof
专利摘要:
The semiconductor device according to the present invention includes a first wiring having a first through hole and a first connection member spaced apart from the first wiring to pass through the first through hole. 公开号:KR20030066446A 申请号:KR10-2003-0006732 申请日:2003-02-04 公开日:2003-08-09 发明作者:가지야마다께시 申请人:가부시끼가이샤 도시바； IPC主号:
专利说明:
Semiconductor device provided with wiring with a hole, and its manufacturing method {SEMICONDUCTOR DEVICE HAVING WIRING WITH HOLES THEREIN, AND MANUFACTURING METHOD THEREOF} [36] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having thick wiring with holes and a method of manufacturing the same. [37] In a semiconductor device having a multilayer wiring structure, thick wirings 111 and 112 may be required in order to flow a large current as shown in FIG. 22. Between these thick wirings 111 and 112, these thick wirings 111 and 112 and non-conductive wiring, especially the longitudinal wiring of the via 113 etc., are arrange | positioned. In this case, as shown in FIG. 23, the matching width of the wiring width X of the thick wirings 111 and 112, the width Y of the vias 113, the distance Z of the thick wirings 111 and 112, and the vias 113, and the like. There was a problem in that this overlaps and the area of the semiconductor device increases. [38] In addition, even in a magnetic memory device such as a magnetic random access memory (MRAM) equipped with a MTJ (Magnetic Tunnel Junction) device using a tunneling magneto resistive effect (hereinafter referred to as TMR), a thick wiring is required. The same problem as that of the semiconductor device may occur. [39] That is, as shown in FIG. 24, in the magnetic memory device, the MTJ element 130 serving as the memory element is disposed at the intersection of the bit line 127 and the word line 136, and data is stored in the MTJ element 130. Is written. At the time of this writing, a large current must flow through the bit line 127 and the word line 136. For this reason, the wiring width of the bit line 127 and the word line 136 needs to be thickened to some extent. [40] In addition, as shown in FIG. 25, in general, the bit line 127 and the word line 136, which are write wirings, need to cover the MTJ element 130. As shown in FIG. Here, the MTJ element 130 is often formed long and thin in order to optimize the magnetic domain. Therefore, when the MTJ element 130 is formed long and thin in the extending direction (arrow direction) of the word line 136, the wiring width Q of the bit line 127 is made thick according to the width P of the MTJ element 130. Needs to be. [41] As described above, even in the magnetic memory device, the wiring widths of the bit lines 127 and the word lines 136 become thicker, so that there is a problem that the area of the device increases as in the semiconductor device. [42] A semiconductor device according to a first aspect of the present invention includes a first wiring having a first hole and a first connecting member passing through the first hole spaced apart from the first wiring. [43] According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of forming the first wirings (11, 27, 27a) having the first holes (13, 29), and the first wirings (11, 27, And forming a first connection member 12, 26, 34, 34a passing through the first holes 13, 29 at a distance from 27a). [1] 1 is a perspective view showing a semiconductor device having a multilayer structure according to the first embodiment of the present invention. [2] FIG. 2A is a perspective view showing wiring according to the first embodiment of the present invention, FIG. 2B is a plan view showing the wiring according to the first embodiment of the present invention, and FIG. 2C is a sectional view taken along the line IIC-IIC in FIG. 2B. . [3] 3A is a perspective view showing a wiring and a contact according to the first embodiment of the present invention, FIG. 3B is a plan view showing a wiring and a contact according to the first embodiment of the present invention, and FIG. 3C is a IIIC-IIIC line in FIG. 3B. Cross section taken along. [4] 4 is a plan view showing a wiring in which a recess is formed according to the first embodiment of the present invention. [5] 5 is a perspective view illustrating a semiconductor device having a multilayer structure according to a second embodiment of the present invention. [6] 6A is a perspective view showing wiring according to a second embodiment of the present invention, FIG. 6B is a plan view showing wiring according to a second embodiment of the present invention, and FIG. 6C is a cross-sectional view taken along the VIC-VIC line in FIG. 6B. . [7] Fig. 7A is a perspective view showing a wiring and a contact according to a second embodiment of the present invention. Fig. 7B is a plan view showing a wiring and a contact according to a second embodiment of the present invention. Fig. 7C is a VIIC-VIIC line in Fig. 7B. Cross section taken along. [8] FIG. 8 is a plan view showing wirings including concave portions according to a second embodiment of the present invention; FIG. [9] 9 is a perspective view showing a magnetic memory device according to the third embodiment of the present invention; [10] Fig. 10 is a sectional view showing the magnetic memory device according to the third embodiment of the present invention. [11] Fig. 11 is a perspective view showing a magnetic memory device according to the fourth embodiment of the present invention. [12] 12 is a sectional view showing a magnetic memory device according to the fourth embodiment of the present invention. [13] Fig. 13 is a perspective view showing a magnetic memory device according to the fifth embodiment of the present invention. [14] Fig. 14 is a sectional view showing the magnetic memory device according to the fifth embodiment of the present invention. [15] Fig. 15 is a perspective view showing a magnetic memory device according to the sixth embodiment of the present invention. [16] 16 is a sectional view showing the magnetic memory device according to the sixth embodiment of the present application; [17] Fig. 17 is a perspective view showing another magnetic memory device according to the sixth embodiment of the present invention. [18] Fig. 18 is a sectional view showing another magnetic memory device according to the sixth embodiment of the present invention. [19] Fig. 19 is a perspective view showing a magnetic memory device according to the seventh embodiment of the present invention. [20] 20 is a cross-sectional view showing a magnetic memory device according to the seventh embodiment of the present invention. [21] 21 is a perspective view showing a semiconductor device having a multilayer wiring structure according to another embodiment of the present invention. [22] Fig. 22 is a perspective view showing a semiconductor device having a thick wiring of a multilayer structure according to the prior art. [23] Fig. 23 is a plan view showing a semiconductor device having thick wirings according to the prior art. [24] Fig. 24 is a sectional view showing a magnetic memory device according to the prior art. [25] 25 is a plan view showing a magnetic memory device according to the prior art; [26] <Explanation of symbols for the main parts of the drawings> [27] 11, 27, 27a: first wiring [28] 12, 26, 34, 34a: first connection member [29] 13, 13a, 13b, 13c, 29: hole [30] 14: recess [31] 111, 112: thick wiring [32] 113: Via [33] 127: bit line [34] 130: MTJ element [35] 136: word line [44] Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference numerals throughout the drawings. [45] <First Embodiment> [46] In 1st Embodiment, a hole is formed in a thick wiring and the contact which is not conductive with wiring is passed through this hole. [47] 1 is a perspective view of a semiconductor device having a multilayer structure according to the first embodiment of the present invention. 2A, 2B, and 2C show a perspective view, a plan view, and a sectional view of a wiring according to a first embodiment of the present invention. 3A, 3B, and 3C show a perspective view, a plan view, and a sectional view of a wiring and a contact according to the first embodiment of the present invention. Below, the structure of the semiconductor device which concerns on 1st Embodiment is demonstrated. [48] As shown in FIG. 1, in the semiconductor device of the multilayer structure which concerns on 1st Embodiment, the 1st-3rd wiring 11a, 11b, 11c of wiring width is thick, and these 1st-3rd wiring 11a, In the case where vertical wirings such as the contacts 12 which are not conductive with 11b and 11c exist, holes 13a, 13b and 13c are formed in the first to third wirings 11a, 11b and 11c, respectively. The contact 12 is made to pass through 13a, 13b, and 13c. [49] Specifically, as shown in FIGS. 2A, 2B, and 2C, for example, a plurality of holes 13 are formed in the wiring 11 having a large wiring width in which a large current needs to flow. These holes 13 penetrate the wiring 11 and are spaced apart at equal intervals, for example. In addition, it is not limited to the shape of the hole 13, For example, it is a rectangle or circular shape. [50] 3A, 3B, and 3C, the contact 12 passes through the hole 13 of the wiring 11. Here, since the contact 12 is non-conductive with the wiring 11, the contact 12 and the wiring 11 are spaced apart from each other. An insulating film (not shown) is buried, for example, between the contact 12 and the wiring 11. [51] In addition, since the width of the wiring 11 becomes substantially thin in the hole 13 portion, there is a fear that the wiring resistance becomes high. Therefore, the hole 13 needs to be set to such a magnitude that the rise of the wiring resistance is not a problem. [52] The semiconductor device according to the first embodiment of the present invention is formed by the following method. The manufacturing method of a part of the semiconductor device according to the first embodiment is briefly described below. [53] First, as shown in FIG. 2C, a wiring material for wiring 11 is formed, and the wiring material is formed in the shape of the wiring 11 and the hole 13, for example, using lithography and reactive ion etching (RIE). Is patterned. Next, an insulating film (not shown) is formed in the hole 13 and on the wiring 11. Thereafter, part of the insulating film is removed, and a groove for the contact 12 is formed in the hole 13. Then, as the contact material is filled in the groove, as shown in Fig. 3C, a contact 12 passing through the hole 13 is formed. [54] The multilayer wiring is formed by repeating the above-described steps, and as shown in FIG. 1, the contact 12 passing through the holes 13a, 13b, and 13c in the first to third wirings 11a, 11b, and 11c is shown. ) Is formed. [55] According to the first embodiment, in the case of forming a multilayer wiring requiring a thick wiring width, a hole 13 is formed in the wiring 11 with a large wiring width, and the wiring 11 and the wiring 11 are formed in the hole 13. The contact 12 is spaced apart. For this reason, the device area is determined only by the width of the wiring 11, so that the increase in the device area can be minimized, which is advantageous for miniaturization. [56] In general, the wiring through which a large current flows is increased, so that the exclusive area thereof is increased, and therefore, the wiring is not disposed in the lower layer portion of the multilayer wiring. However, when the structure of 1st Embodiment is used, since the occupation area can be suppressed small, it becomes possible to arrange | position the wiring 11 which flows a large electric current also in the lower layer part of a multilayer wiring. [57] In addition, in 1st Embodiment, the wiring 11 is not limited to the pattern mentioned above, A various deformation | transformation is also possible. For example, as shown in FIG. 4, you may form the recessed part 14 in which the width | variety of the wiring 11 was narrowed between the adjacent holes 13 in the wiring 11. In this case, not only the effect in the first embodiment but also the current path can be adjusted. [58] <2nd embodiment> [59] In the second embodiment, in the wiring according to the first embodiment, a contact fringe is further formed in the hole. In addition, in 2nd Embodiment, only a point different from 1st Embodiment is demonstrated. [60] 5 is a perspective view of a semiconductor device having a multilayer structure according to the second embodiment of the present invention. 6A, 6B, and 6C show a perspective view, a plan view, and a sectional view of a wiring according to a second embodiment of the present invention. 7A, 7B, and 7C show a perspective view, a plan view, and a sectional view of a wiring and a contact according to the second embodiment of the present invention. Below, the structure of the semiconductor device which concerns on 2nd Embodiment is demonstrated. [61] As shown in FIG. 5 to FIG. 7C, a difference from the first embodiment is that the contact fringe 15 is formed in the contact 12 in the hole 13 of the wiring 11. Since this contact fringe 15 is formed of the same material as the wiring 11, the thickness of the contact fringe 15 and the thickness of the wiring 11 are the same. The contact fringe 15 is formed to be spaced apart from the wiring 11. [62] The semiconductor device according to the second embodiment of the present invention is formed by the following method. The manufacturing method of a part of the semiconductor device according to the second embodiment will be briefly described below. [63] First, as shown in Fig. 6C. A wiring material for the wiring 11 is formed, and the wiring material is patterned using, for example, lithography and RIE in the shape of the wiring 11, the holes 13, and the contact fringes 15. Next, an insulating film (not shown) is formed on the gap between the contact fringe 15 and the wiring 11 and on the wiring 11. Thereafter, a part of the insulating film is removed to form a groove for the contact 12 exposing the contact fringe 15. As the contact material is embedded in the groove, as shown in FIG. 7C, a contact 12 for connecting to the contact fringe 15 is formed. [64] Then, by repeating the above steps, a multilayer wiring is formed, and as shown in FIG. 5, through the holes 13a, 13b, 13c in the first to third wirings 11a, 11b, 11c, the contact fringes are formed. A contact 12 with a 15 is formed. [65] According to the said 2nd Embodiment, not only the effect similar to 1st Embodiment can be acquired, but the following effects can be acquired further. [66] In the first embodiment, since the contact 12 is formed to pass through the hole 13, the depth of the groove for the contact 12 is obtained by adding the distance between the thickness of the wiring 11 and the upper and lower wirings. On the other hand, in the second embodiment, since the contact 12 is formed on the contact fringe 15, the depth of the groove for the contact 12 is only the distance between the upper and lower wirings. Therefore, in the second embodiment, it is not necessary to form the deep contact 12 as in the first embodiment, and the second embodiment can be formed at the same depth as the contacts for connecting the normal wirings. This makes it possible not only to use a normal contact process, but also to prevent the generation of voids that may occur in the formation of deep contacts. [67] In addition, in 2nd Embodiment, the wiring 11 is not limited to the pattern mentioned above, It is also possible to deform | transform variously. For example, as shown in FIG. 8, the concave portion 14 may be formed between the adjacent holes 13 in the wiring 11. In this case, not only the effect in the second embodiment, but also the current path can be adjusted. [68] Third Embodiment [69] In the third embodiment, the structure of the semiconductor device according to the second embodiment is applied to a magnetic memory device. This magnetic memory device is, for example, an MRAM (Magnetic Random Access Memory) equipped with a MTJ (Magnetic Tunnel Junction) element using a tunneling magneto resistive effect (hereinafter referred to as TMR). In the structure of the MRAM according to the third embodiment, the MTJ element is arranged at the intersection of the bit line and the write word line. [70] 9 is a perspective view of a magnetic memory device according to the third embodiment of the present invention. 10 is a sectional view of a magnetic memory device according to the third embodiment of the present invention. The structure of the magnetic memory device according to the third embodiment will be described below. [71] 9 and 10, in the magnetic memory device according to the third embodiment, the bit lines 27 and the write word lines 36 intersect each other, and these bit lines 27 and the write word lines are arranged. The MTJ element 30 is disposed on the bit line 27 at the intersection of 36. A hole 29 is formed in the bit line 27, and a contact fringe 28 is formed in the hole 29. The upper wiring 35 connected to the MTJ element 30 is connected to the contact 34, and the contact 34 is connected to the contact fringe 28, and the contact fringe 28 is connected to the contact 26. This contact 26 is connected to the source / drain diffusion layer 23 of the MOS transistor 24. Therefore, the MTJ element 30 is connected to the data reading MOS transistor 24 through the hole 29 of the bit line 27. [72] The magnetic memory device according to the third embodiment of the present invention is formed by the following method. The manufacturing method of the magnetic memory device according to the third embodiment will be briefly described below. [73] First, the gate electrode 22 is selectively formed on the semiconductor substrate 21, and the source / drain diffusion layer 23 is formed in the semiconductor substrate 21 on both sides of the gate electrode 22. As a result, the MOS transistor 24 is formed. The gate electrode 22 of this MOS transistor 24 becomes a read word line. [74] Next, a contact 26 is formed in the insulating film 25 to connect to the source / drain diffusion layer 23. Next, the wiring material which consists of the bit line 27 and the contact fringe 28 is formed, and this wiring material is patterned. As a result, a bit line 27 having a hole 29 is formed, and a contact fringe 28 is formed in the hole 29. Here, a gap is formed between the bit line 27 and the contact fringe 28 so that the bit line 27 and the contact fringe 28 are not electrically conductive. [75] Next, the MTJ element 30 is formed on the bit line 27. The MTJ element 30 is composed of a magnetization fixing layer 31, a magnetic recording layer 33, and a tunnel junction layer 32 between these magnetization fixing layer 31 and the magnetic recording layer 33. [76] Next, a contact 34 is formed on the contact fringe 28, and an upper wiring 35 is formed on the contact 34 and the MTJ element 30. Next, the word line 36 is formed on the upper side of the MTJ element 30 by being spaced apart from the upper wiring 35. [77] The magnetic memory device according to the third embodiment of the present invention as described above writes and reads data in the following operation. The following describes the writing and reading operations of the magnetic memory device according to the third embodiment. [78] When data is written to the MTJ element 30, the bit lines 27 and the write word lines 36 are selected, and currents flow through the bit lines 27 and the write word lines 36, respectively, to form a current magnetic field. Generate. As a result, the composite magnetic field of the current magnetic field generated in each of the bit line 27 and the write word line 36 is applied to the MTJ element 30 so that data of "1" or "0" is written to the MTJ element 30. . [79] When reading data written to the MTJ element 30, the MOS transistor 24 connected to the MTJ element 30 is turned on, and the MTJ element 30 to the upper wiring 35 to the contact 34 to A current flows through the contact fringes 28 through 26 through the source / drain diffusion layer 23. In this way, the resistance value of the MTJ element 30 is read, and data of "1" or "0" is determined. [80] According to the third embodiment, the device area can be reduced as in the first embodiment, which is advantageous for miniaturization. That is, in the magnetic memory device, the write wirings (bit lines 27 and word lines 36) used when writing data to the MTJ element 30 become thicker for flowing a large current. Also in this case, a hole 29 is formed in the bit line 27, and the contacts 34 and 26 are passed through the hole 29 while being spaced apart from the bit line 27. For this reason, the occupation area of the memory cell portion can be reduced by the amount of the occupation area of the contacts 34 and 26, the matching margin, and the like. [81] In addition, since the contact fringes 28 are formed as in the second embodiment, not only a normal contact process can be used but also generation of voids that may occur in the formation of deep contacts can be prevented. [82] In the magnetic memory device according to the third embodiment, the write word line 36 is disposed above the MTJ element 30. For this reason, it is unlikely that other wirings or contacts will be located around the write word line 36. Therefore, compared with the conventional structure shown in FIG. 24, the positional restriction of the position of the write word line 36 is less, and the write word line 36 can be made thicker. [83] Also. 3rd Embodiment can also be applied to the structure without the contact fringe 28 like 1st Embodiment. [84] Also. A plurality of holes 29 may be formed in the bit line 27 in the direction in which current flows. In this case, the recessed part 14 as shown in FIG. 4, FIG. 8 may be formed between the hole 29 which the bit line 27 adjoins. Here, the recess 14 is preferably formed in a region other than directly below the MTJ element 30. [85] <4th embodiment> [86] In the fourth embodiment, the structure of the semiconductor device according to the second embodiment is applied to a magnetic memory device, in which an MTJ element is disposed at an intersection of a contact fringe and a write word line. [87] 11 is a perspective view of a magnetic memory device according to the fourth embodiment of the present invention. 12 is a sectional view of a magnetic memory device according to the fourth embodiment of the present invention. The structure of the magnetic memory device according to the fourth embodiment will be described below. [88] 11 and 12, in the magnetic memory device according to the fourth embodiment, a hole 29 is formed in the write bit line 27a, and a contact fringe 28 is formed in the hole 29. It is. A write word line 36 intersecting with the write bit line 27a is disposed above the contact fringe 28. The MTJ element 30 is disposed between the contact fringe 28 and the write word line 36. In addition, contacts 26 and 34 are respectively connected to the contact fringe 28, and the contact 26 is connected to the source / drain diffusion layer 23 of the MOS transistor. The contact 34 is connected to the MTJ element 30 via the lower wiring 37, and a read bit line 27b is disposed on the MTJ element 30. Therefore, the MTJ element 30 disposed above the contact fringe 28 is connected to the MOS transistor 24 through the hole 29 of the write bit line 27a. [89] The magnetic memory device according to the fourth embodiment of the present invention is formed by the following method. The manufacturing method of the magnetic memory device according to the fourth embodiment will be briefly described below. [90] First, the gate electrode 22 is selectively formed on the semiconductor substrate 21, and the source / drain diffusion layer 23 is formed in the semiconductor substrate 21 on both sides of the gate electrode 22. As a result, the MOS transistor 24 is formed. The gate electrode 22 of this MOS transistor 24 becomes a read word line. [91] Next, a contact 26 is formed in the insulating film 25 to connect to the source / drain diffusion layer 23. Next, the wiring material which consists of the write bit line 27a and the contact fringe 28 is formed, and this wiring material is patterned. As a result, a write bit line 27a having a hole 29 is formed, and a contact fringe 28 is formed in the hole 29. Here, a gap is formed between the write bit line 27a and the contact fringe 28, and the write bit line 27a and the contact fringe 28 are not conductive. [92] Next, a contact 34 is formed on the contact fringe 28, and a lower wiring 37 is formed on the contact 34. The MTJ element 30 is formed on the lower wiring 37, and the read bit line 27b is formed on the MTJ element 30. Next, the write word line 36 is formed on the MTJ element 30 above the read bit line 27b. [93] In the magnetic memory device according to the fourth embodiment of the present invention as described above, data is written and read in the following operation. The following describes the write and read operations of the magnetic memory device according to the fourth embodiment. [94] In the case of writing data to the MTJ element 30, the write bit line 27a and the write bit line 36 are selected, and a current flows through the write bit line 27a and the write word line 36, respectively. Generate a current magnetic field. Accordingly, the composite magnetic field of the current magnetic field generated in each of the write bit line 27a and the write word line 36 is applied to the MTJ element 30, so that data of "1" or "0" is stored in the MTJ element 30. Is written. [95] When reading the data written to the MTJ element 30, the MOS transistor 24 connected to the MTJ element 30 is turned on, and the read bit lines 27b to MTJ elements 30 to the lower wiring 37 are turned on. A current flows through the contact 34 to the contact fringe 28 to the contact 26 to the source / drain diffusion layer 23. As a result, the resistance value of the MTJ element 30 is read, and data of "1" or "0" is determined. [96] In the fourth embodiment, the MTJ element 30 is disposed above the hole 29 of the write bit line 27a. For this reason, when writing data to the MTJ element 30, it is thought that the current magnetic field from the write bit line 27a becomes small, but the write bit line 27a is sufficient for the extension direction of the write word line 36. It has a width and can generate a current magnetic field having a sufficient magnitude from the write bit line 27a around the hole 29. [97] According to the fourth embodiment, the same effects as in the third embodiment can be obtained. [98] In the fourth embodiment, the MTJ element 30 is disposed above the contact fringe 28. For this reason, compared with 3rd Embodiment, the area of the horizontal direction of a memory cell part can be reduced. [99] Moreover, like 4th Embodiment, it is also possible to apply to the structure which does not have the contact fringe 28 like 1st Embodiment. [100] Further, a plurality of holes 29 may be formed in the write bit line 27a in the direction in which current flows. In this case, the concave portion 14 as shown in Figs. 4 and 8 may be formed between the adjacent holes 29 in the write bit line 27a. [101] The read bit line 27b does not extend like the write bit line 27a but is shortened like the upper wiring 35 in FIG. 10 and connected to the write bit line 27a on one side of the MTJ element 30. You may also [102] <Fifth Embodiment> [103] In the fifth embodiment, the structure of the semiconductor device according to the second embodiment is applied to a magnetic memory device. A plurality of MTJ elements are connected in parallel with upper and lower wirings to form a so-called ladder structure. [104] 13 is a perspective view of a magnetic memory device according to the fifth embodiment of the present invention. 14 is a sectional view of a magnetic memory device according to the fifth embodiment of the present invention. The structure of the magnetic memory device according to the fifth embodiment will be described below. [105] As shown in FIGS. 13 and 14, in the magnetic memory device according to the fifth embodiment, a plurality of MTJ elements 30 are arranged in parallel above the bit line 27. The magnetic recording layer 33 of each MTJ element 30 is connected to the upper wiring 35, and the magnetization fixing layer 31 of each MTJ element 30 is connected to the lower wiring 37, so-called ladder structure. It is. A write word line 36 is arranged above the MTJ element 30 so as to be spaced apart from the upper wiring 35. In addition, a hole 29 is formed in the bit line 27, and a contact fringe 28 is formed in the hole 29. The contact 34a connected to the lower wiring 37 and the contact 34b connected to the upper wiring 35 are connected to the contact fringe 28. Therefore, the plurality of ladder-shaped MTJ elements 30 are connected to the contacts 26 through the holes 29 of the bit lines 27. The contact 26 is connected to, for example, a MOS transistor which is a data readout switching element. [106] The magnetic memory device according to the fifth embodiment of the present invention is formed by the following method. The manufacturing method of the magnetic memory device according to the fifth embodiment will be briefly described below. [107] First, a MOS transistor (not shown) is formed on a semiconductor substrate (not shown), and a contact 26 for connecting to a source / drain diffusion layer (not shown) of the MOS transistor is formed. [108] Next, the wiring material which consists of the bit line 27 and the contact fringe 28 is formed, and this wiring material is patterned. As a result, a bit line 27 having a hole 29 is formed, and a contact fringe 28 is formed in the hole 29. Here, a gap is formed between the bit line 27 and the contact fringe 28 so that the bit line 27 and the contact fringe 28 are not electrically conductive. [109] Next, a contact 34a is formed to connect to the contact fringe 28. Next, the lower wiring 37 is formed to be spaced apart from the bit line 27, and the lower wiring 37 and the contact 34a are connected. Then, a plurality of MTJ elements 30 are formed on the lower wiring 37. The MTJ element 30 is composed of a magnetization fixing layer 31, a magnetic recording layer 33, and a tunnel junction layer 32 between these magnetization fixing layer 31 and the magnetic recording layer 33. [110] Next, a contact 34b for connecting to the contact fringe 28 is formed. Next, an upper wiring 35 is formed on the MTJ element 30, and the upper wiring 35 is connected to the contact 34b. The write word line 36 is formed on the MTJ element 30 above the upper wiring 35. [111] The magnetic memory device according to the fifth embodiment of the present invention as described above writes and reads data in the following operation. The following describes the write and read operations of the magnetic memory device according to the fifth embodiment. [112] When writing data to any MTJ element 30 among the plurality of MTJ elements 30 connected in parallel, the bit line 27 and the write word line 36 are selected, and these bit lines 27 and the write are made. A current flows through each of the word lines 30 to generate a current magnetic field. As a result, the composite magnetic field of the current magnetic field generated in each of the bit line 27 and the write word line 36 is applied to the MTJ element 30, and data of " 1 " or " 0 " Enter. [113] Reading of the data written to any MTJ element 30 is performed as follows. [114] In the first cycle, the read-out MOS transistors connected to the plurality of MTJ elements 30 connected in parallel are turned on, and the first read current is passed through the plurality of MTJ elements 30 connected in parallel. The first read current value at this time is stored by the sensing circuit. Thereafter, the read-out MOS transistor is turned off to turn off the first read current. [115] Next, in the second cycle, a current flows through the bit line 27 and the write word line 36 again, and data of "1" or "0" is written into an arbitrary MTJ element 30. Thereafter, the read-out MOS transistor is turned off to turn off the write current. [116] Next, in the third cycle, the readout MOS transistors connected to the plurality of MTJ elements 30 connected in parallel again are turned on, and the second read current is flowed through the plurality of MTJ elements 30 connected in parallel. The second read current value at this time is stored by the sensing circuit. [117] Thereafter, the first read current value and the second read current value are compared. Here, when writing the expected value "1" at the time of writing, if the first and second read current values do not change, "1", if the first and second read current values are increasing, "0" is originally written. It shall be. On the other hand, when the expected value "0" is written at the time of writing, "0" is originally written if the first and second read current values are not changed, and "1" is originally written if the first and second read current values are increasing. do. In this manner, data written in the original cell can be read. [118] Finally, in the fourth cycle, a current flows through the bit line 27 and the word line 36 so that the same data as the initial (initial) state is written again, and the read operation is completed. [119] According to the fifth embodiment, the same effects as in the third embodiment can be obtained. [120] In the fifth embodiment, a readout MOS transistor may be provided for each of the plurality of MTJ elements 30 connected in parallel. Therefore, the area of the memory cell portion can be reduced as compared with the structure in which the readout MOS transistor is provided for each MTJ element 30. [121] In addition, like 5th Embodiment, it is also possible to apply to the structure which does not have the contact fringe 28 like 1st Embodiment. [122] Moreover, you may form the recessed part 14 as shown in FIG. 4, FIG. 8 between the adjacent holes 29 of the bit line 27. As shown in FIG. In this case, the recess 14 is preferably formed below the MTJ elements 30 rather than below the MTJ elements 30 connected in parallel. [123] Sixth Embodiment [124] In the sixth embodiment, the structure of the semiconductor device according to the second embodiment is applied to a magnetic memory device, in which a plurality of MTJ elements are stacked in a stacking direction to connect these MTJ elements. [125] 15 is a perspective view of a magnetic memory device according to the sixth embodiment of the present invention. 16 is a sectional view of a magnetic memory device according to the sixth embodiment of the present invention. The structure of the magnetic memory device according to the sixth embodiment will be described below. [126] 15 and 16, in the magnetic memory device according to the sixth embodiment, the first bit line 27 and the first write word line 36 intersect each other. A hole 29 is formed in the first bit line 27, and a contact fringe 28 is formed in the hole 29. The first MTJ element 30 is spaced apart from the first bit line 27 and the first write word line 36 at the intersection of the first bit line 27 and the first write word line 36. It is arranged. The first lower wiring 37 is connected to the magnetization fixing layer 31 of the first MTJ element 30, and the first upper wiring 35 is connected to the magnetic recording layer 33 of the first MTJ element 30. Connected. [127] Further, above the first write word line 36, the second bit line 27 'and the second write word line 36' cross each other. A hole 29 'is formed in the second bit line 27', and a contact fringe 28 'is formed in the hole 29'. The second MTJ is spaced apart from the second bit line 27 'and the second write word line 36' at the intersection of the second bit line 27 'and the second write word line 36'. The element 30 'is arrange | positioned. A second lower wiring 37 'is connected to the magnetization fixing layer 31' of the second MTJ element 30 ', and a second upper portion is connected to the magnetic recording layer 33' of the second MTJ element 30 '. The wiring 35 'is connected. [128] The second upper wiring 35 ′ is connected to the first MTJ element 30 through the contact 40, the contact fringe 28 ′, the contact 39, and the first upper wiring 35. The second lower wiring 37 'is connected to the first MTJ element 30 via the contact 34', the contact fringe 28 ', the contact 38, and the first lower wiring 37. . The first MTJ element 30 is connected to the source / drain diffusion layer 23 of the MOS transistor 24 through the first lower wiring 37, the contact 34, the contact fringe 28, and the contact 26. It is. In this manner, the first and second MTJ elements 30 and 30 'are connected through the holes 29' of the second bit line 27 ', and the first and second MTJ elements 30 and 30' are connected to each other. Is connected to the MOS transistor 24 through the hole 29 of the first bit line 27. [129] The magnetic memory device according to the sixth embodiment of the present invention is formed by the following method. The manufacturing method of the magnetic memory device according to the sixth embodiment is briefly described below. [130] First, the gate electrode 22 is selectively formed on the semiconductor substrate 21, and the source / drain diffusion layer 23 is formed in the semiconductor substrate 21 on both sides of the gate electrode 22. As a result, the MOS transistor 24 is formed. The gate electrode 22 of this MOS transistor 24 becomes a read word line. [131] Next, a contact 26 is formed in the insulating film 25 to connect to the source / drain diffusion layer 23. Next, the wiring material which becomes the 1st bit line 27 and the contact fringe 28 is formed, and this wiring material is patterned. As a result, a first bit line 27 having a hole 29 is formed, and a contact fringe 28 is formed in the hole 29. Here, a gap is formed between the first bit line 27 and the contact fringe 28 so that the first bit line 27 and the contact fringe 28 are not electrically conductive. [132] Next, a contact 34 is formed on the contact fringe 28, and a lower wiring 37 is formed on the contact 34. The first MTJ element 30 is formed on the lower wiring 37. The first MTJ element 30 is composed of a magnetization fixing layer 31, a magnetic recording layer 33, and a tunnel junction layer 32 between these magnetization fixing layer 31 and the magnetic recording layer 33. As shown in FIG. [133] Next, an upper wiring 35 is formed on the first MTJ element 30, and spaced apart from the upper wiring 35, the first write word line 36 is disposed above the first MTJ element 30. Is formed. [134] Next, a contact 38 for connecting to the lower wiring 37 and a contact 39 for connecting to the upper wiring 35 are formed. [135] Next, the wiring material which becomes the 2nd bit line 27 'and the contact fringe 28' is formed, and this wiring material is patterned. As a result, a second bit line 27 'having a hole 29' is formed, and a contact fringe 28 'is formed in the hole 29'. Here, a gap is formed between the second bit line 27 'and the contact fringe 28' so that the second bit line 27 'and the contact fringe 28' are not conductive. [136] Next, a contact 34 'is formed on the contact fringe 28', and a lower wiring 37 'is formed on the contact 34'. The second MTJ element 30 'is formed on the lower wiring 37'. The second MTJ element 30 'includes a magnetization fixing layer 31', a magnetic recording layer 33 ', and a tunnel junction layer between the magnetization fixing layer 31' and the magnetic recording layer 33 '. 32 '). [137] Next, a contact 40 is formed that connects to the contact fringe 28 '. Next, an upper wiring 35 'is formed on the contact 40 and the second MTJ element 30', spaced apart from the upper wiring 35 ', and above the second MTJ element 30'. The second write word line 36 'is formed. [138] In the magnetic memory device according to the sixth embodiment of the present invention as described above, data is written and read in the same operation as in the fifth embodiment. [139] According to the sixth embodiment, the same effects as in the third embodiment can be obtained. [140] In the sixth embodiment, the readout MOS transistor 24 may be formed for each of the plurality of connected MTJ elements 30 and 30 '. Therefore, as in the fifth embodiment, the area of the memory cell portion can be reduced as compared with the structure in which read-out MOS transistors are formed for each MTJ element 30. [141] In addition, in 6th Embodiment, the connection of 1st and 2nd MTJ elements 30 and 30 'is not limited to the said structure. For example, as shown in Figs. 17 and 18, the upper wiring 35 'and the lower wiring 37' of the second MTJ element 30 'have the same structure as the above structure, and thus the first MTJ element 30 The pattern of the upper wiring 35 and the lower wiring 37 of the () may be reversed from the pattern of the upper wiring 35 'and the lower wiring 37' of the second MTJ element 30 '. [142] In addition, like the first embodiment, the sixth embodiment can be applied to a structure without the contact fringe 28. [143] In addition, between the adjacent holes 29 of the first bit line 27 and between the adjacent holes 29 'of the second bit line 27', the concave portions as shown in Figs. 14) may be formed. In this case, the recess 14 is preferably formed in a region other than below the MTJ elements 30 and 30 '. [144] Seventh Embodiment [145] In the seventh embodiment, the structure of the semiconductor device according to the second embodiment is applied to a magnetic memory device. A plurality of MTJ elements are stacked in a stacking direction, and these MTJ elements are connected in series. [146] 19 is a perspective view of a magnetic memory device according to the seventh embodiment of the present invention. 20 is a sectional view of a magnetic memory device according to the seventh embodiment of the present invention. The structure of the magnetic memory device according to the seventh embodiment will be described below. [147] 19 and 20, in the magnetic memory device according to the seventh embodiment, the first bit line 27 and the first write word line 36 intersect each other. A hole 29 is formed in the first bit line 27, and a contact fringe 28 is formed in the hole 29. The first MTJ element 30 is spaced apart from the first bit line 27 and the first write word line 36 at the intersection of the first bit line 27 and the first write word line 36. It is arranged. The first lower wiring 37 is connected to the magnetization fixing layer 31 of the first MTJ element 30, and the first upper wiring 35 is connected to the magnetic recording layer 33 of the first MTJ element 30. Connected. [148] Further, above the first write word line 36, the second bit line 27 'and the second write word line 36' are arranged to cross each other. A hole 29 'is formed in the second bit line 27', and a contact fringe 28 'is formed in the hole 29'. The second MTJ is spaced apart from the second bit line 27 'and the second write word line 36' at the intersection of the second bit line 27 'and the second write word line 36'. The element 30 'is arrange | positioned. The second lower wiring 37 'is connected to the magnetization fixing layer 31' of the second MTJ element 30 ', and the second upper portion is connected to the magnetic recording layer 33' of the second MTJ element 30 '. The wiring 35 'is connected. [149] The second lower wiring 37 'is connected to the first MTJ element 30 through the contact 34', the contact fringe 28 ', the contact 39, and the first upper wiring 35. The first MTJ element 30 is connected to the source / drain diffusion layer 23 of the MOS transistor 24 through the first lower wiring 37, the contact 34, the contact fringe 28, and the contact 26. It is. In this manner, the first and second MTJ elements 30 and 30 'are connected in series through the holes 29' of the second bit line 27 ', and the first and second MTJ elements 30 and 30' are connected in series. 30 'is connected to the MOS transistor 24 through the hole 29 of the first bit line 27. [150] The magnetic memory device according to the seventh embodiment of the present invention is formed by the following method. The manufacturing method of the magnetic memory device according to the seventh embodiment will be briefly described below. [151] First, the gate electrode 22 is selectively formed on the semiconductor substrate 21, and the source / drain diffusion layer 23 is formed in the semiconductor substrate 21 on both sides of the gate electrode 22. As a result, the MOS transistor 24 is formed. The gate electrode 22 of this MOS transistor 24 becomes a read word line. [152] Next, a contact 26 is formed in the insulating film 25 to connect to the source / drain diffusion layer 23. Next, the wiring material which becomes the 1st bit line 27 and the contact fringe 28 is formed, and this wiring material is patterned. As a result, a first bit line 27 having a hole 29 is formed, and a contact fringe 28 is formed in the hole 29. Here, a gap is formed between the first bit line 27 and the contact fringe 28 so that the first bit line 27 and the contact fringe 28 are not electrically conductive. [153] Next, a contact 34 is formed on the contact fringe 28, and a lower wiring 37 is formed on the contact 34. The first MTJ element 30 is formed on the lower wiring 37. The first MTJ element 30 is composed of a magnetization fixing layer 31, a magnetic recording layer 33, and a tunnel junction layer 32 between these magnetization fixing layer 31 and the magnetic recording layer 33. As shown in FIG. [154] Next, an upper wiring 35 is formed on the first MTJ element 30, and spaced apart from the upper wiring 35, the first write word line 36 is disposed above the first MTJ element 30. Is formed. Next. The contact 39 which connects to the lower wiring 37 is formed. [155] Next, the wiring material which becomes the 2nd bit line 27 'and the contact fringe 28' is formed, and this wiring material is patterned. As a result, a second bit line 27 'having a hole 29' is formed, and a contact fringe 28 'is formed in the hole 29'. Here, a gap is formed between the second bit line 27 'and the contact fringe 28' so that the second bit line 27 'and the contact fringe 28' are not conductive. [156] Next, a contact 34 'is formed on the contact fringe 28, and a lower wiring 37' is formed on the contact 34 '. The second MTJ element 30 'is formed on the lower wiring 37'. The second MTJ element 30 'includes a magnetization fixing layer 31', a magnetic recording layer 33 ', and a tunnel junction layer between the magnetization fixing layer 31' and the magnetic recording layer 33 '. 32 '). [157] Next, an upper wiring 35 'is formed on the second MTJ element 30', spaced apart from the upper wiring 35 ', and a second write word line above the second MTJ element 30'. 36 'is formed. [158] In the magnetic memory device according to the seventh embodiment of the present invention as described above, data is written and read in the same operation as that of the fifth embodiment. [159] According to the seventh embodiment, the same effects as in the third embodiment can be obtained. [160] In the seventh embodiment, the readout MOS transistor 24 may be formed for each MTJ element 30, 30 'connected in series. Therefore, as in the fifth and sixth embodiments, the area of the memory cell portion can be reduced as compared with the structure in which the readout MOS transistors are formed for each MTJ element 30. [161] In addition, like the first embodiment, the seventh embodiment can be applied to a structure without the contact fringe 28. [162] Further, recesses 14 as shown in FIGS. 4 and 8 are formed between the adjacent holes 29 of the bit line 27 and between the adjacent holes 29 'of the bit line 27'. You may also In this case, the recess 14 is preferably formed in a region other than below the MTJ elements 30 and 30 '. [163] The above-described embodiments are to be considered in all respects only as illustrative and not restrictive. It is intended that the scope of the invention be defined not by the foregoing description of the embodiments, but rather by the claims, and shall include such modifications as come within the meaning and range equivalent to the claims. [164] For example, as shown in FIG. 21, the structure of the wiring according to the second embodiment can also be applied to a semiconductor device having a multilayer wiring such as DRAM. Also in this case, holes 68, 72, and 76 are formed in each of the wirings 66, 70, and 74, and the contacts having contact fringes 67, 71, and 75 in the holes 68, 72, and 76 ( 65, 69, 73). Each of the wirings 66, 70, and 74 is, for example, a current wiring having a directionality through which a large current flows. [165] For example, in the third to seventh embodiments, the MTJ element is used as the storage element in the magnetic memory device. Instead of the MTJ element, the GMR (consisting of two magnetic layers and a conductor layer positioned between these magnetic layers) It is also possible to use Giant Magneto Resistivc devices. [166] For example, in the third to seventh embodiments, although the MTJ element of the single junction structure composed of one tunnel junction layer was used as the memory element, the double junction structure composed of two tunnel junction layers was used. MTJ elements may also be used. [167] For example, in the third to seventh embodiments, although the MOS transistor 24 is used as the data reading switching element, the present invention is not limited thereto, and a diode may be used, for example. [168] Therefore, according to the present invention, since a hole is formed in the wiring having a large wiring width, and the contact is passed through the hole at a distance from the wiring, the device area is determined only by the wiring width, so that the area increase can be minimized, thereby miniaturizing. It is advantageous to
权利要求:
Claims (48) [1" claim-type="Currently amended] A first wiring having a first through hole, A first connecting member spaced apart from the first wiring and passing through the first through hole A semiconductor device comprising a. [2" claim-type="Currently amended] The method of claim 1, And a recess formed in the first wiring and having a narrow width of the first wiring. [3" claim-type="Currently amended] The method of claim 1, And a contact fringe spaced apart from the first wiring in the first through hole. [4" claim-type="Currently amended] The method of claim 3, A semiconductor device, wherein the thickness of the contact fringe is the same as that of the first wiring. [5" claim-type="Currently amended] The method of claim 1, And a magnetoresistive element connected to said first connection member. [6" claim-type="Currently amended] The method of claim 5, And the first wiring is a bit line. [7" claim-type="Currently amended] The method of claim 5, And the magnetoresistive element is an MTJ element formed of at least a first magnetic layer, a second magnetic layer and a nonmagnetic layer. [8" claim-type="Currently amended] The method of claim 7, wherein The MTJ element has a single junction structure or a double junction structure. [9" claim-type="Currently amended] The method of claim 5, And a contact fringe spaced apart from the first wiring in the first through hole. [10" claim-type="Currently amended] The method of claim 9, A semiconductor device, wherein the thickness of the contact fringe is the same as that of the first wiring. [11" claim-type="Currently amended] The method of claim 5, And a concave portion formed in the first wiring and having a narrow width of the first wiring. [12" claim-type="Currently amended] The method of claim 5, And a transistor or diode connected to said first connection member. [13" claim-type="Currently amended] The method of claim 1, A second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; A third wiring disposed spaced apart from the first wiring and the second wiring between the first wiring and the second wiring, and connected to the first connection member; Magnetoresistive elements disposed at intersections of the first and second wirings between the first and third wirings and connected to the first and third wirings. The semiconductor device further comprising. [14" claim-type="Currently amended] The method of claim 13, The first wiring is a bit line, and the second wiring is a write word line. [15" claim-type="Currently amended] The method of claim 13, And a contact fringe spaced apart from the first wiring in the first through hole. [16" claim-type="Currently amended] The method of claim 1, A second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; A third wiring disposed to be spaced apart from the first and second wirings between the first and second wirings; Magnetoresistive elements disposed at the intersections of the first and second wirings between the first and third wirings and connected to the third wirings and the first connection members. The semiconductor device further comprising. [17" claim-type="Currently amended] The method of claim 16, And the first wiring is a write bit line, the second wiring is a write word line, and the third wiring is a read bit line. [18" claim-type="Currently amended] The method of claim 16, And a contact fringe spaced apart from the first wiring in the first through hole. [19" claim-type="Currently amended] The method of claim 1, A plurality of second wirings disposed in a spaced apart from the first wiring extending in a first direction, and extending in a second direction different from the first direction, wherein the first wirings include the first through hole and the second through hole. Achievement, A plurality of magnetoresistive effects disposed at intersections of the first and second wirings between the first and second wirings, respectively, and having one end portion facing the first wiring and the other end portion facing the second wiring; Element, Third wirings connected to the one end of the magnetoresistive element, spaced apart from the first wiring, and connected to the first connecting member, Fourth wirings connected to the other end of the magnetoresistive element, and spaced apart from the second wiring; A second connecting member connected to the fourth wiring and spaced apart from the first wiring to pass through the second through hole; The semiconductor device further comprising. [20" claim-type="Currently amended] The method of claim 19, And the first wiring is a bit line, and the second wiring is a write word line. [21" claim-type="Currently amended] The method of claim 19, A first contact fringe spaced apart from the first wiring in the first through hole; A second contact fringe spaced apart from the first wiring in the second through hole The semiconductor device further comprising. [22" claim-type="Currently amended] The method of claim 1, A second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; A first magnetoresistive element disposed at the intersection of the first and second wirings between the first and second wirings, the first magnetoresistive element having one end and the other end; A third wiring connected to said one end of said first magnetoresistive element and said first connecting member and spaced apart from said first wiring; A fourth wiring connected to the other end of the first magnetoresistive element and spaced apart from the second wiring; A fifth wiring disposed to be spaced apart from the second wiring, extending in the first direction, and having second and third through holes; A sixth wiring spaced apart from the fifth wiring and extending in the second direction; A second magnetoresistive element disposed at the intersection of the fifth and sixth wirings between the fifth and sixth wirings and having one end portion and the other end portion; A seventh wiring connected to said one end of said second magnetoresistive element and spaced apart from said fifth wiring; An eighth wiring connected to said other end of said second magnetoresistive element and spaced apart from said sixth wiring; A second connecting member connected to the third and seventh wirings and spaced apart from the fifth wirings and passing through the second through hole; A third connecting member connected to the fourth and eighth wiring lines and spaced apart from the fifth wiring line and passing through the third through hole; The semiconductor device further comprising. [23" claim-type="Currently amended] The method of claim 22, And the first wiring is a first bit line, the second wiring is a first write word line, the fifth wiring is a second bit line, and the sixth wiring is a second write word line. [24" claim-type="Currently amended] The method of claim 22, A first contact fringe spaced apart from the first wiring in the first through hole; A second contact fringe spaced apart from the fifth wiring in the second through hole; A third contact fringe spaced apart from the fifth wiring in the third through hole The semiconductor device further comprising. [25" claim-type="Currently amended] The method of claim 1, A second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; A first magnetoresistive element disposed at the intersection of the first and second wirings between the first and second wirings, the first magnetoresistive element having one end and the other end; A third wiring connected to said one end of said first magnetoresistive element and said first connecting member and spaced apart from said first wiring; A fourth wiring connected to the other end of the first magnetoresistive element and spaced apart from the second wiring; A fifth wiring disposed spaced apart from the second wiring, extending in the first direction, and having a second through hole; A sixth wiring spaced apart from the fifth wiring and extending in the second direction; A second magnetoresistive element disposed at the intersection of the fifth and sixth wirings between the fifth and sixth wirings and having one end portion and the other end portion; A seventh wiring connected to said one end of said second magnetoresistive element and spaced apart from said fifth wiring; An eighth wiring connected to said other end of said second magnetoresistive element and spaced apart from said sixth wiring; A second connecting member connected to the fourth and seventh wirings and spaced apart from the fifth wirings and passing through the second through hole; The semiconductor device further comprising. [26" claim-type="Currently amended] The method of claim 25, And the first wiring is a first bit line, the second wiring is a first write word line, the fifth wiring is a second bit line, and the sixth wiring is a second write word line. [27" claim-type="Currently amended] The method of claim 25, A first contact fringe spaced apart from the first wiring in the first through hole; A second contact fringe spaced apart from the fifth wiring in the second through hole The semiconductor device further comprising. [28" claim-type="Currently amended] Forming a first wiring having a first through hole; Forming a first connection member spaced apart from the first wiring and passing through the first through hole Method for manufacturing a semiconductor device comprising a. [29" claim-type="Currently amended] The method of claim 28, And forming a concave portion in which the width of the first wiring becomes thin in the first wiring. [30" claim-type="Currently amended] The method of claim 28, And forming a contact fringe spaced apart from the first wiring in the first through hole. [31" claim-type="Currently amended] The method of claim 30, And the contact fringe and the first wiring are formed of the same material. [32" claim-type="Currently amended] The method of claim 28, A method of manufacturing a semiconductor device, further comprising the step of forming a magnetoresistive element connected to the first connection member. [33" claim-type="Currently amended] 33. The method of claim 32, The magnetoresistive element is a method of manufacturing a semiconductor device which is an MTJ element formed of at least a first magnetic layer, a second magnetic layer, and a nonmagnetic layer. [34" claim-type="Currently amended] The method of claim 33, wherein The MTJ element is a method of manufacturing a semiconductor device having a single junction structure or a double junction structure. [35" claim-type="Currently amended] 33. The method of claim 32, And forming a contact fringe spaced apart from the first wiring in the first through hole. [36" claim-type="Currently amended] 36. The method of claim 35 wherein And the contact fringe and the first wiring are formed of the same material. [37" claim-type="Currently amended] 33. The method of claim 32, And forming a concave portion in which the width of the first wiring is thinned in the first wiring. [38" claim-type="Currently amended] 33. The method of claim 32, And forming a transistor or diode connected to said first connection member. [39" claim-type="Currently amended] The method of claim 28, Forming a second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; Forming a third wiring connected to the first connection member while being spaced apart from the first and second wiring between the first and second wirings; Forming a magnetoresistive element connected to the first and third wirings at an intersection point of the first and second wirings between the first and third wirings; The method of manufacturing a semiconductor device further comprising. [40" claim-type="Currently amended] The method of claim 39, And forming a contact fringe in the first through hole to be spaced apart from the first wiring. [41" claim-type="Currently amended] The method of claim 28, Forming a second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; Forming a third wiring between the first wiring and the second wiring so as to be spaced apart from the first wiring and the second wiring; Forming a magnetoresistive element connected to the third wiring and the first connection member at an intersection of the first and second wirings between the first and third wirings; The method of manufacturing a semiconductor device further comprising. [42" claim-type="Currently amended] The method of claim 41, wherein And forming a contact fringe in the first through hole to be spaced apart from the first wiring. [43" claim-type="Currently amended] The method of claim 28, Forming a plurality of second wirings spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction, wherein the first wiring includes the first through hole and the second through hole. With- A plurality of magnetoresistive elements each having one end portion facing the first wiring and the other end portion facing the second wiring are formed at intersections of the first and second wirings between the first and second wirings. Process to do, Forming a third wiring connected to said one end of said magnetoresistive element and said first connecting member spaced apart from said first wiring; Forming a fourth wiring connected to the other end of the magnetoresistive element at a distance from the second wiring; Forming a second connecting member connected to the fourth wiring, wherein the second connecting member is spaced apart from the first wiring and passes through the second through hole; The manufacturing method of the semiconductor device which further contains. [44" claim-type="Currently amended] The method of claim 43, Forming a first contact fringe in the first through hole spaced apart from the first wiring; Forming a second contact fringe in the second through hole to be spaced apart from the first wiring. The method of manufacturing a semiconductor device further comprising. [45" claim-type="Currently amended] The method of claim 28, Forming a second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; Forming a first magnetoresistive effect element having one end and the other end at an intersection point of the first and second wirings between the first and second wirings; Forming a third wiring connected to said one end of said first magnetoresistive element and said first connecting member spaced apart from said first wiring; Forming a fourth wiring connected to the other end of the first magnetoresistive element with a distance from the second wiring; Forming a fifth wiring spaced apart from the second wiring and extending in the first direction, wherein the fifth wiring has second and third through holes; Forming a sixth wiring spaced apart from the fifth wiring and extending in the second direction; Forming a second magnetoresistive effect element having one end and the other end at an intersection point of the fifth and sixth wirings between the fifth and sixth wirings; Forming a seventh wiring connected to the one end of the second magnetoresistive element apart from the fifth wiring; Forming an eighth interconnection connected to the other end of the second magnetoresistive element apart from the sixth interconnection; Forming a second connecting member connected to the third and seventh wirings, wherein the second connecting members are spaced apart from the fifth wirings and pass through the second through holes; Forming a third connecting member connected to the fourth and eighth wirings, wherein the third connecting members are spaced apart from the fifth wirings and pass through the third through holes. . [46" claim-type="Currently amended] The method of claim 45, Forming a first contact fringe in the first through hole spaced apart from the first wiring; Forming a second contact fringe in the second through hole spaced apart from the fifth wiring; Forming a third contact fringe spaced apart from the fifth wiring in the third through hole. The method of manufacturing a semiconductor device further comprising. [47" claim-type="Currently amended] The method of claim 28, Forming a second wiring spaced apart from the first wiring extending in a first direction and extending in a second direction different from the first direction; Forming a first magnetoresistive effect element having one end and the other end at an intersection point of the first and second wirings between the first and second wirings; Forming a third wiring connected to said one end of said first magnetoresistive element and said first connecting member spaced apart from said first wiring; Forming a fourth wiring connected to the other end of the first magnetoresistive element with a distance from the second wiring; Forming a fifth wiring spaced apart from the second wiring and extending in the first direction, wherein the fifth wiring has a second through hole; and Forming a sixth wiring spaced apart from the fifth wiring and extending in the second direction; Forming a second magnetoresistive effect element having one end and the other end at an intersection point of the fifth and sixth wirings between the fifth and sixth wirings; Forming a seventh wiring connected to the one end of the second magnetoresistive element apart from the fifth wiring; Forming an eighth wiring connected to the other end of the second magnetoresistive element apart from the sixth wiring; Forming a second connection member connected to the fourth and seventh wirings, wherein the second connection members are spaced apart from the fifth wirings and pass through the second through holes. . [48" claim-type="Currently amended] The method of claim 47, Forming a first contact fringe in the first through hole spaced apart from the first wiring; Forming a second contact fringe spaced apart from the fifth wiring in the second through hole. The method of manufacturing a semiconductor device further comprising.
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同族专利:
公开号 | 公开日 US20030146515A1|2003-08-07| EP1333486A3|2008-02-20| CN1444274A|2003-09-24| JP2003229546A|2003-08-15| KR100466561B1|2005-01-17| JP3875568B2|2007-01-31| US6861752B2|2005-03-01| TWI224379B|2004-11-21| CN100359683C|2008-01-02| TW200401399A|2004-01-16| EP1333486A2|2003-08-06|
引用文献:
公开号 | 申请日 | 公开日 | 申请人 | 专利标题
法律状态:
2002-02-05|Priority to JP2002028561A 2002-02-05|Priority to JPJP-P-2002-00028561 2003-02-04|Application filed by 가부시끼가이샤 도시바 2003-08-09|Publication of KR20030066446A 2005-01-17|Application granted 2005-01-17|Publication of KR100466561B1
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申请号 | 申请日 | 专利标题 JP2002028561A|JP3875568B2|2002-02-05|2002-02-05|Semiconductor device and manufacturing method thereof| JPJP-P-2002-00028561|2002-02-05| 相关专利
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