• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An internal circuit, a period of time after the internal circuit is changed from a standby state to an active state, a transition state voltage drop circuit generating an internal power supply voltage supplied from the external power supply voltage to the internal circuit, and a period during which the internal circuit is in the standby state and the active state And a steady state voltage drop circuit for generating an internal power supply voltage from an external power supply voltage.
    公开号:KR20030025882A
    申请号:KR1020020057301
    申请日:2002-09-19
    公开日:2003-03-29
    发明作者:다까기와데루오；마스다마사미
    申请人:가부시끼가이샤 도시바；
    IPC主号:
    专利说明:

    Semiconductor Integrated Circuits and Semiconductor Memory {SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY}
    [24] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a semiconductor memory, and more particularly, to a semiconductor integrated circuit and a semiconductor memory having a voltage drop circuit for dropping an external power supply voltage to an internal power supply voltage and supplying it to an internal circuit.
    [25] In recent years, with the improvement of the microfabrication technique, the technique which sets the internal power supply voltage supplied to an internal circuit lower than an external power supply voltage, and realizes high integration, high speed, etc. is actively researched. As a means for dropping the external power supply voltage supplied from the power supply terminal on the semiconductor chip to the internal power supply voltage, a voltage drop circuit is an essential technical element.
    [26] The voltage drop circuit includes a comparison circuit section and a p-type MOS transistor driven by an external power supply voltage. The comparison circuit section controls the gate voltage of the p-type MOS transistor. By the gate control by the comparison circuit section, an internal power supply voltage is output from the drain of the p-type MOS transistor. An internal capacitance is disposed between the internal power supply voltage and the ground potential. The internal power supply voltage is supplied to an internal circuit, which consumes current.
    [27] As shown in Fig. 1, when the clock signal CLK is changed from the standby state 10 to which the clock signal CLK is supplied to the active state 11 to which the clock signal CLK is supplied, the consumption current IDD of the internal circuit changes greatly. The change in the current consumption IDD causes the internal power supply voltage VINT to fluctuate, interfering with the high speed operation of the internal circuit. The variation of the internal power supply voltage VINT is greatest immediately after the change from the standby state 10 to the active state 11, and gradually decreases.
    [28] In order to reduce the fluctuation of the internal power supply voltage VINT, the internal capacitance must be increased, or the comparison circuit section and the p-type MOS transistor need to be enlarged. However, due to the limitation of the chip area, it is not easy to increase the internal capacity. The scale-up of the comparison circuit portion and the p-type MOS transistor leads to an increase in the current consumption of the voltage drop circuit itself, which is undesirable.
    [29] In terms of the stable supply of the internal power supply voltage VINT, a plurality of voltage drop circuits are evenly distributed in the semiconductor chip, and some voltage drop circuits are stopped in a standby state to reduce current consumption of the entire voltage drop circuit. The technique called is used. However, the stop clock can reduce the current consumption of the voltage drop circuit in the standby state, but cannot reduce the current consumption of the voltage drop circuit in the active state.
    [1] 1 is a time chart illustrating a time change of a clock signal, a current consumption of an internal circuit, and an internal power supply voltage according to a related art.
    [2] Fig. 2 is a block diagram showing a semiconductor integrated circuit according to the first embodiment of the present invention.
    [3] 3 is a circuit diagram showing first to third transition state voltage drop circuits and first and second steady state voltage drop circuits shown in FIG.
    [4] 4 is a circuit diagram showing first to fourth circuit parts included in the transition detection circuit shown in FIG.
    [5] FIG. 5 is a time sequence showing a time change of major signals in the operation of the transition detection circuit shown in FIG. 4; FIG.
    [6] 6 is a block diagram showing a semiconductor integrated circuit according to a modification of the first embodiment of the present invention.
    [7] FIG. 7 is a circuit diagram showing first to fourth circuit parts included in the transition detection circuit shown in FIG. 6. FIG.
    [8] 8 is a block diagram showing a semiconductor integrated circuit according to the second embodiment of the present invention.
    [9] FIG. 9 is a circuit diagram showing first to fourth circuit parts included in the transition detection circuit shown in FIG. 8. FIG.
    [10] 10 is a time sequence showing a time change of a major signal in the operation of the transition detection circuit shown in FIG. 9;
    [11] 11 is a block diagram showing a semiconductor integrated circuit according to a modification of the second embodiment of the present invention.
    [12] FIG. 12 is a circuit diagram showing first to fourth circuit parts included in the transition detection circuit shown in FIG. 11. FIG.
    [13] Fig. 13 is a block diagram showing a semiconductor memory having a semiconductor integrated circuit according to the first embodiment of the present invention.
    [14] <Explanation of symbols for the main parts of the drawings>
    [15] 1: internal circuit
    [16] 2a: first transition state voltage drop circuit
    [17] 2b: second transition state voltage drop circuit
    [18] 2c: third transition state voltage drop circuit
    [19] 3a: first steady state voltage drop circuit
    [20] 3b: second steady state voltage drop circuit
    [21] 21: capacitor
    [22] VDD: external power supply voltage
    [23] VINT: Internal Supply Voltage
    [30] A first aspect of the present invention provides an internal circuit, a transition state voltage drop circuit that generates an internal power supply voltage supplied from an external power supply voltage to an internal circuit only for a predetermined period after the internal circuit is changed from a standby state to an active state, and an internal circuit. It is a semiconductor integrated circuit having at least a steady state voltage drop circuit which generates an internal power supply voltage from an external power supply voltage, in a period during which the circuit is in a standby state and an active state.
    [31] A second aspect of the invention is a memory circuit, a transition state voltage drop circuit that generates an internal power supply voltage supplied from an external power supply voltage to a memory circuit only for a predetermined period after the memory circuit is changed from a standby state to an active state, and a memory It is a semiconductor memory having at least a steady state voltage drop circuit which generates an internal power supply voltage from an external power supply voltage, while the circuit is in a standby state and an active state.
    [32] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the drawings, the same or similar parts will be denoted by the same reference numerals, and repeated descriptions of the same or similar parts and elements will be omitted.
    [33] <First Embodiment>
    [34] As shown in FIG. 2, the semiconductor integrated circuit according to the first embodiment includes an internal circuit 1 in which the semiconductor integrated circuit realizes a main function, and an internal power supply supplied from the external power supply voltage VDD to the internal circuit 1. The first to third transition state voltage drop circuits 2a to 2c, the first and second steady state voltage drop circuits 3a and 3b for generating the voltage VINT, and the capacitor 21 are provided.
    [35] The first to third transition state voltage drop circuits 2a to 2c operate only for a predetermined period after the internal circuit 1 changes from the standby state to the active state. The first and second steady state voltage drop circuits 3a and 3b operate during the period in which the internal circuit 1 is in a standby state and an active state. Here, "operating" means generating the internal power supply voltage VINT from the external power supply voltage VDD. "Active state" indicates a state in which the clock signal CLK is supplied to the internal circuit 1, and "active state" indicates a state in which the clock signal CLK is not supplied to the internal circuit 1.
    [36] The semiconductor integrated circuit detects the change from the standby state to the active state and transfers the pulse signal PLSST having the pulse width corresponding to the above-described "constant period" to the first to third transition state voltage drop circuits 2a to 2c. It further includes a transition detecting circuit 4 for transmitting.
    [37] The first to third transition state voltage drop circuits 2a to 2c, and the first and second steady state voltage drop circuits 3a and 3b are output terminals 23a to 23c, 23d and 23e for outputting an internal power supply voltage VINT. ) Each. The first to third transition state voltage drop circuits 2a to 2c and the output terminals 23a to 23c, 23d and 23e of the first and second steady state voltage drop circuits 3a and 3b are connected in parallel. The internal power supply voltage VINT generated by the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b is supplied to the internal circuit 1. A capacitor 21 is connected between the internal power supply voltage VINT and the ground potential, and a predetermined internal capacitance is applied to the internal power supply voltage VINT.
    [38] The first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b have control terminals 22a to 22c, 22d and 22e, respectively. The pulse signals PLSST are input to the control terminals 22a to 22c of the first to third transition state voltage drop circuits 2a to 2c. An external power supply voltage VDD is applied to the control terminals 22d and 22e of the first and second steady state voltage drop circuits 3a and 3b. The transition detection circuit 4 is supplied with the clock signal CLK similarly to the internal circuit 1.
    [39] The first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b each have the same circuit configuration. As shown in Fig. 3, the first to third transition state voltage drop circuits 2a to 2c, and the first and second steady state voltage drop circuits 3a and 3b are the comparison circuit section 9 and the p-type. The MOS transistor M7, the n-type MOS transistor M8, the first resistor 24, and the second resistor 25 are provided. The comparison circuit section 9 includes first and second p-type MOS transistors M1 and M2, and first and second n-type MOS transistors M3 and M4. The first and second p-type MOS transistors M1 and M2 form a current mirror circuit.
    [40] The reference voltage VREF that is not dependent on the external power supply voltage VDD is applied to the gate electrode of the first n-type MOS transistor M3. The drain electrode of the first n-type MOS transistor M3 is connected to the gate electrode of the p-type MOS transistor M7. The p-type MOS transistor M7, the first resistor 24, the second resistor 25 and the n-type MOS transistor M8 are connected in series. The external power supply voltage VDD is applied to the source electrode of the p-type MOS transistor M7. The ground potential is applied to the source electrode of the n-type MOS transistor M8. The gate electrode of the second n-type MOS transistor M4 is connected between the first resistor 24 and the second resistor 25.
    [41] The comparison circuit section 9 drives the p-type MOS transistor M7 so that the gate voltage of the second n-type MOS transistor M4 matches the reference voltage VREF applied to the gate electrode of the first n-type MOS transistor M3. The output terminal 23 is connected to the drain electrode of the p-type MOS transistor M7. Therefore, the internal power supply voltage VINT may be represented by VINT = (1 + R1 / R2) VREF. Here, "R1" and "R2" represent the resistance values of the resistor 24 and the resistor 25, respectively. The internal power supply voltage VINT is applied to the internal circuit 1, and the internal circuit 1 consumes a current 40. The control terminal 22 is connected to the gate electrodes of the n-type MOS transistors M6 and M8, respectively. By controlling on and off of the n-type MOS transistors M6 and M8 at the potential of the control terminal 22, the first to third transition state voltage drop circuits 2a to 2c including the comparison circuit 9, and the first and The operation of the entire second steady state voltage drop circuits 3a and 3b is controlled.
    [42] As shown in Fig. 4, the transition detection circuit 4 has first to fourth circuit portions 12 to 14 and 15a. The first circuit section 12 has a first NAND circuit (hereinafter referred to as "NAND1") and first to sixth inverter circuits (hereinafter referred to as "INV1 to 6"). The clock signal CLK is directly input to one input terminal of NAND1. The other input terminal of NAND1 is input via a delay stage consisting of INV1 to 5 in which clock signals CLK are connected in series. The output of NAND1 is input to INV6. The first detection signal P1 is output from INV6.
    [43] The second circuit section 13 partitions a plurality of (m stage) delay circuits connected in series. The plurality of delay circuits are referred to as first to mth NOR circuits (hereinafter referred to as "NOR1 to m") and seventh to (3m + 6) inverter circuits (hereinafter referred to as "INV7 to (3m + 6)"). Is provided). In the delay circuit of the first stage, the first detection signal P1 is directly input to one input terminal of the NOR1. The other input terminal of the NOR1 is input via a delay stage consisting of INV7 and INV8 in which the first detection signal P1 is connected in series. The output signal of NOR1 is input to INV9.
    [44] The output signal of INV9 is input to one input terminal of NOR2 in the delay circuit of the next stage through the delay stage consisting of INV10 and INV11 connected in series. The first detection signal P1 is directly input to the other input terminal of the NOR2. Similarly, a plurality of delay circuits are connected in series below. The active signal PLSEN is output from INV (3m + 6) in the delay circuit of the last stage.
    [45] The third circuit portion 14 includes a second NAND circuit (hereinafter referred to as "NAND2") and (3m + 7) to (3m + 12) inverter circuits (hereinafter, "INV (3m + 7)-(3m) +12)). The active signal PLSEN is directly input to one input terminal of NAND2. The other input terminal of NAND2 is input via a delay stage consisting of INV (3m + 7) to (3m + 11) in which the active signal PLSEN is connected in series. The output signal of NAND2 is input to INV (3m + 12). The second detection signal P2 is output from INV (3m + 12).
    [46] Similar to the second circuit portion 13, the fourth circuit portion 15a includes a plurality of (n stage) delay circuits connected in series. The plurality of delay circuits include (m + 1) to (m + n) NOR circuits (hereinafter referred to as "NOR (m + 1) to (m + n)") and (3m + 13) to (3m + 3n + 12) -th inverter circuit (henceforth "INV (3m + 13)-(3m + 3n + 12)"). In the delay circuit of the first stage, the second detection signal P2 is directly input to one input terminal of NOR (m + 1). The second detection signal P2 is input to the other input terminal of the NOR (m + 1) via a delay stage consisting of INV (3m + 13) and INV (3m + 14) connected in series. The output signal of NOR (m + 1) is input to INV (3m + 15). The output signal of INV (3m + 15) is input to one of NOR (m + 2) in the delay circuit of the next stage through a delay stage consisting of INV (3m + 17) connected in series (3m + 16). It is input to the terminal. The second detection signal P2 is directly input to the other input terminal of NOR (m + 2). Similarly, a plurality of delay circuits are connected in series below. The pulse signal PLSST is output from INV (3m + 3n + 12) in the delay circuit of the last stage.
    [47] Next, the operation of the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIG.
    [48] The first circuit portion 12 in FIG. 4 detects the rise of the clock signal CLK and outputs the first detection signal P1. The second circuit section 13 in FIG. 4 delays the period from the rising to the falling of the first detection signal P1, and outputs the active signal PLSEN during the period in which the internal circuit 1 is at least active state 11. The third circuit unit 14 of FIG. 4 detects the rise of the active signal PLSEN and outputs the second detection signal P2. 4th circuit part 15a of FIG. 4 outputs pulse signal PLSST by delaying the period from the rising to falling of 2nd detection signal P2. The pulse signal PLSST has a pulse width (indicated by "tST" in FIG. 5) corresponding to the "constant period" in which the first to third transition state voltage drop circuits 2a to 2c in FIG. 2 operate. In this way, the transition detection circuit 4 of FIG. 2 detects the standby state 10 because the clock signal CLK has not changed for a certain period of time. The transition detection circuit 4 detects the change from the standby state 10 to the active state 11 by the clock signal CLK starting to change, and at the same time as the clock signal CLK starts to be supplied to the internal circuit 1, the pulse signal Send PLSST.
    [49] The first to third transition state voltage drop circuits 2a to 2c in Fig. 2 operate only during the period of receiving the pulse signal PLSST. That is, the first to third transition state voltage drop circuits 2a to 2c supply the internal power supply voltage VINT to the internal circuit 1 only for a predetermined period after the internal circuit 1 changes from the standby state 10 to the active state 11. do. An external power supply voltage VDD is applied to the control terminals 22d and 22e of the first and second steady state voltage drop circuits 3a and 3b. Accordingly, the first and second steady state voltage drop circuits 3a and 3b operate regardless of whether the internal circuit 1 is in the active state 10 or the standby state 11. That is, the first and second steady state voltage drop circuits 3a and 3b supply the internal power supply voltage VINT to the internal circuit 1 during the period in which the internal circuit 1 is in the standby state 10 and the active state 11.
    [50] As described with reference to FIG. 1, as the change from the standby state 10 to the active state 11, the consumption current of the internal circuit 1 greatly changes, causing variation in the internal power supply voltage VINT. The change in the internal power supply voltage VINT is the largest immediately after the change from the standby state 10 to the active state 11, and gradually decreases. Therefore, the pulse width tST of the pulse signal PLSST shown in FIG. 2 matches with the internal power supply voltage VINT in a fixed period immediately after the change from the standby state 10 to the active state 11. That is, by operating the first to third transition state voltage drop circuits 2a to 2c only for a period of time during which a large fluctuation occurs in the internal power supply voltage VINT, the current supply capability to the internal circuit 1 can be temporarily increased. Therefore, the fluctuation of the internal power supply voltage VINT can be suppressed.
    [51] Next, operations of the first to fourth circuit units 12 to 14 and 15a shown in FIG. 4 will be described in detail. As the clock signal CLK rises, the first detection signal P1 also rises. Then, the rising of the clock signal CLK is inputted to the NAND1 through the INV1 to the 5, so that the first detection signal P1 falls. Therefore, the pulse width of the first detection signal P1 corresponds to the time required for the clock signal CLK to pass through INV1 to 5. The number of stages of the delay stages connected in series to the other input terminal of the NAND1 may not only be five but also other odd numbers such as one, three, seven, or the like. By increasing the number of delay stages, the pulse width of the first detection signal P1 becomes wider.
    [52] Since the first detection signal P1 is directly input to one input terminal of the NOR1, the output of the INV9 also rises at the same time as the first detection signal P1 rises. Thereafter, the rise of the first detection signal P1 is inputted to the other input terminal of the NOR1 through the INV7 and 8. The falling of the first detection signal P1 is directly input to one input terminal of the NOR1, but is input to the other input terminal of the NOR1 after passing through INV7 and 8. Therefore, the fall of the output signal of INV9 is delayed by the period in which the first detection signal P1 passes through INV7 and INV8 rather than falling. Therefore, the rise of the output signal of INV9 is substantially coincident with the rise of the first detection signal P1, but the fall of the output signal of INV9 is delayed more than the fall of the first detection signal P1.
    [53] By connecting the plurality of delay circuits described above in series, the INV (3m + 6) in the delay circuit of the last stage can output the active signal PLSEN at least during the period in which the clock signal CLK is supplied. In addition, NOR1, 2,... Since the first detection signal P1 is directly input to one input terminal of 3m, the rise of the active signal PLSEN is not delayed with respect to the rise of the first detection signal P1. In addition, it is preferable to form a fuse in the second circuit portion 13 in which a metal option or a laser blowable fuse can be freely set by the user in the number of delay circuits included in the second circuit portion 13. In addition, the number of stages of the delay stages in each delay circuit may be not only two but also other even numbers such as four, six, eight, or the like. By increasing the number of delay stages, the pulse width of the active signal PLSEN is widened.
    [54] Since the active signal PLSEN is directly input to one input terminal of the NAND2, the second detection signal P2 also rises at the same time as the active signal PLSEN rises. Then, the rising of the active signal PLSEN is inputted to NAND2 through INV (3m + 7) to (3m + 11), whereby the second detection signal P2 falls. Therefore, the pulse width of the second detection signal P2 corresponds to the time required for the active signal PLSEN to pass through INV (3m + 7) to (3m + 11). In addition, the number of stages of the delay stages connected in series to the other input terminal of the NAND2 may not only be five but also other odd numbers such as one, three, seven, and the like. By increasing the number of delay stages, the pulse width of the second detection signal P2 becomes wider.
    [55] Since the second detection signal P2 is directly input to one input terminal of NOR (m + 1), the output signal of INV (3m + 15) also rises almost simultaneously with the rise of the second detection signal P2. Thereafter, the rise of the second detection signal P2 is input to the other input terminal of the NOR (m + 1) through the INV (3m + 13) and the INV (3m + 14). The fall of the second detection signal P2 is directly input to one input terminal of the NOR (m + 1), but the INV (3m + 13) and INV (3m + 14) are input to the other input terminal of the NOR (m + 1). It is entered after passing. Therefore, the fall of the output signal from INV (3m + 15) is delayed by the period passing through INV (3m + 13) and INV (3m + 14) rather than the fall of the second detection signal P2. Therefore, the rise of the output signal of INV (3m + 15) is substantially coincident with the rise of the second detection signal P2, but the fall of the output signal of INV (3m + 15) is delayed rather than the fall of the second detection signal P2.
    [56] By connecting the plurality of delay circuits described above in series, the INV (3m + 3n + l2) in the delay circuit of the last stage is in the first to third transition states of FIG. 2 for a predetermined period from the rise of the second detection signal P2. The pulse signal PLSST for operating the voltage drop circuits 2a to 2c can be output. In addition, since the second detection signal P2 is directly input to one of the input terminals of NOR (m + 1) to NOR (m + n), the rise of the pulse signal PLSST is delayed with respect to the rise of the second detection signal P2. It doesn't work. In addition, it is preferable to form a fuse in the fourth circuit portion 15a which allows blow by a metal option or a laser or the like so that the user can freely set the number of delay circuits of the fourth circuit portion 15a. In addition, the number of stages of the delay stage of the delay circuit may not only be two but also other even numbers such as four, six, eight, or the like. By increasing the number of delay circuits, the pulse width of the pulse signal PLSST becomes wider.
    [57] As described above, according to the first embodiment, even when the current consumption of the internal circuit 1 changes with the change from the standby state 10 to the active state 11, the variation in the internal power supply voltage VINT can be reduced. Therefore, stable high speed operation of the internal circuit 1 can be realized.
    [58] The first to third transition state voltage drop circuits 2a to 2c are operated only for a predetermined period tST immediately after the change in the internal power supply voltage VINT changes from the standby state 10 with the largest change to the active state 11. Therefore, it is not necessary to enlarge the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b, and the first to third transition state voltage drop circuits. (2a to 2c) and the increase in current consumption of the first and second steady state voltage drop circuits 3a and 3b are not caused.
    [59] In addition, since the first to third transition state voltage drop circuits 2a to 2c are not operated in the active state 11 after tST has elapsed for a certain period, the first to third transition state voltage drops in the active state 11. Current consumptions of the circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b may be reduced.
    [60] In addition, there is no need to increase the internal capacitance 21 connected to the internal power supply voltage VINT.
    [61] The maximum variation in the internal power supply voltage VINT is a case in which the current consumption of the internal circuit 1 is greatly changed, that is, a change from the standby state 10 to the active state 11. In order to reduce the fluctuation of the internal power supply voltage VINT, the p-type MOS transistors M7 in the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b are compared. It is necessary to enlarge the circuit part 9. However, after the change from the standby state 10 to the active state 11, the change in the current consumption of the internal circuit 1 in the active state 11 is generally small. Therefore, the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b require a large p-type MOS transistor M7 or a comparison circuit 9. You will not. Therefore, only when the state changes from the standby state 10 to the active state 11, the first to third transition state voltage drop circuits 2a to 2c are operated for a predetermined time tST, and in the subsequent active state 11, the first and second steady state Only the voltage drop circuits 3a and 3b are operated. As a result, the current consumption of the internal circuit 1 in the active state 11 can be reduced.
    [62] (Modification of the first embodiment)
    [63] As shown in Fig. 6, the semiconductor integrated circuit according to the modification of the first embodiment includes the first to third transition state voltage drop circuits 2a to 2c, the first steady state voltage drop circuit 3a, The active state voltage drop circuit 7a, the transition detection circuit 6, and the capacitor 21 are provided. The active state voltage drop circuit 7a has the same circuit configuration as the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b shown in FIG. Has The active signal PLSEN transmitted from the transition detection circuit 6 is input to the control terminal 22f of the active state voltage drop circuit 7a. The internal power supply voltage VINT generated by the active state voltage drop circuit 7a is connected to the internal circuit 1 similarly to the first to third transition state voltage drop circuits 2a to 2c and the first steady state voltage drop circuit 3a. It is authorized.
    [64] The transition detection circuit 6 shown in FIG. 7 has a structure substantially the same as the transition detection circuit 4 shown in FIG. 4. The difference from the transition detection circuit 4 shown in FIG. 4 is that the active signal PLSEN output from the second circuit section 13 is not only input to the third circuit section 14 but also to the outside of the transition detection circuit 6. It is also extracted. The other structure of the transition detection circuit 6 of FIG. 7 is the same as the transition detection circuit 4 of FIG. 4.
    [65] As shown in Fig. 5, the active signal PLSEN is outputted while the internal circuit 1 is at least in an active state 11. Accordingly, the active state voltage drop circuit 7a operates during the period in which the active signal PLSEN is received, that is, the period in which the internal circuit 1 is at least in the active state 11, and the period in the standby state 10 does not operate. By changing a part of the first and second steady state voltage drop circuits 3a and 3b shown in FIG. 2 to the active state voltage drop circuit 7a, the active state voltage drop circuit 7a in the standby state 10 is changed. Current consumption can be reduced.
    [66] As described above, in the semiconductor integrated circuit according to the modification of the first embodiment, the current supply capability in the active state 11 is increased, and the first to third transition state voltage drop circuits 2a to 2c in the standby state 10, The current consumption of the first steady state voltage drop circuit 3a and the active state voltage drop circuit 7a can be reduced.
    [67] The period tEN in which the active signal PLSEN is output after the change from the active state 11 to the standby state 10 again is attributable to the delay time formed by the second circuit unit 13 in FIG. The period tEN can be shortened by reducing the number of delay circuits included in the second circuit section 13. However, in order for the active signal PLSEN to be one signal which is continuously output during the period in which the internal circuit 1 is at least active state 11, the period tEN must be somewhat long. On the other hand, if the period tEN becomes too long, the first to third transition state voltage drop circuits 2a to 2c, the first steady state voltage drop circuit 3a, and the active state voltage drop circuit 7a in the standby state 10 are shown. Current consumption cannot be reduced.
    [68] (2nd Example)
    [69] As shown in FIG. 8, the semiconductor integrated circuit according to the second embodiment includes an internal circuit 1, first to third transition state voltage drop circuits 2a to 2c, and first and second steady state voltages. The falling circuits 3a and 3b, the transition detection circuit 5, and the capacitor 21 are provided. The first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b output terminals 23a to 23c, 23d and 23e for outputting an internal power supply voltage VINT. And control terminals 22a to 22c, 22d, and 22e, respectively. The first to third transition state voltage drop circuits 2a to 2c and the output terminals 23a to 23c, 23d and 23e of the first and second steady state voltage drop circuits 3a and 3b are connected in parallel. The internal power supply voltage VINT generated by the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b is supplied to the internal circuit 1. The first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b have the same circuit configuration as in FIG.
    [70] The transition detection circuit 5 outputs the first to third pulse signals PLSST1, PLSST2, and PLSST3 having different pulse widths. The first pulse signal PLSST1 is input to the control terminal 22a of the first transition state voltage drop circuit 2a. The second pulse signal PLSST2 is input to the control terminal 22b of the second transition state voltage drop circuit 2b. The third pulse signal PLSST3 is input to the control terminal 22c of the third transition state voltage drop circuit 2c. An external power supply voltage VDD is applied to the control terminals 22d and 22e of the first and second steady state voltage drop circuits 3a and 3b. The transition detection circuit 4 is supplied with the clock signal CLK similarly to the internal circuit 1.
    [71] As shown in FIG. 9, the transition detection circuit 5 has the 1st-4th circuit parts 12-14, 15b. The first to third circuit portions 12 to 14 each have the same circuit configuration as in FIG. 4. The fourth circuit section 15b includes a plurality (n stage) of delay circuits connected in series. The plurality of delay circuits include (m + 1) to (m + n) NOR circuits (hereinafter referred to as "NOR (m + 1) to (m + n)") and (3m + 13). To (3m + 3n + 12) inverter circuits (hereinafter referred to as &quot; INV (3m + 13) to (3m + 3n + 12) &quot;). The configuration of the delay circuit is the same as the delay circuit in the fourth circuit section 15a shown in FIG. The first pulse signal P LSST1 is extracted from INV (3m + 3n1 + 12) in the delay circuit located in the middle of the fourth circuit section 15b. The second pulse signal PLSST2 is extracted from the INV (3m + 3n2 + 12) in the delay circuit located after the INV (3m + 3n1 + 12). The third pulse signal PLSST3 is extracted from the INV (3m + 3n + 12) in the delay circuit located after the INV (3m + 3n2 + 12).
    [72] Next, the operation of the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG.
    [73] The first circuit portion 12 in FIG. 9 detects the rise of the clock signal CLK and outputs the first detection signal P1. The second circuit unit 13 delays the period from the rising to the falling of the first detection signal P1, and outputs the active signal PLSEN during the period in which the internal circuit 1 is at least active state 11. The third circuit unit 14 detects the rise of the active signal PLSEN and outputs the second detection signal P2. The fourth circuit unit 15b outputs the first to third pulse signals PLSST1 to PLSST3 by delaying the period from the rising to the falling of the second detection signal P2. The first to third pulse signals PLSST1 to PLSST3 are pulse widths corresponding to "constant periods" in which the first to third transition state voltage drop circuits 2a to 2c of FIG. 8 operate ("tST1 to tST3 in FIG. 10"). ”). The pulse width tST1 of the first pulse signal PLSST1 is shortest. The pulse width tST2 of the second pulse signal PLSST2 is longer than the pulse width tST1 of the first pulse signal PLSST1. The pulse width tST3 of the third pulse signal PLSST3 is longer than the pulse width tST2 of the second pulse signal PL SST2.
    [74] The first to third transition state voltage drop circuits 2a to 2c in Fig. 8 operate during periods of receiving the first to third pulse signals PLSST1 to PLSST3, respectively. That is, the first to third transition state voltage drop circuits 2a to 2c are internal power supply voltages to the internal circuit 1 only for a predetermined period tST1 to tST3 after the internal circuit 1 is changed from the standby state to the active state. Supply VINT. The first and second steady state voltage drop circuits 3a and 3b supply the internal power supply voltage VINT to the internal circuit 1 while the internal circuit 1 is in the standby state 10 and the active state 11.
    [75] As described above, in the first embodiment, tST, the first to third transition state voltage drop circuits 2a to 2c are operated for a predetermined period after the change from the standby state 10 to the active state 11, and thereafter, the first to the third embodiments are operated. The three transition state voltage drop circuits 2a to 2c were simultaneously stopped. However, since the first to third transition state voltage drop circuits 2a to 2c are stopped at the same time, the internal power supply voltage VINT may change. That is, the variation of the internal power supply voltage VINT due to the change from the standby state 10 to the active state 11 can be reduced, and the internal power supply voltage when the first to third transition state voltage drop circuits 2a to 2c thereafter are stopped. VINTs can sometimes fluctuate.
    [76] Thus, the second embodiment starts the operations of the first to third transition state voltage drop circuits 2a to 2c immediately after the change from the standby state 10 to the active state 11, and thus the first to third pulse signals having different pulse widths. The operations of the first to third transition state voltage drop circuits 2a to 2c are stopped in sequence by PLSST1 to PLSST3. Therefore, according to the second embodiment, not only exhibit the same operational effects as those of the semiconductor integrated circuit according to the first embodiment, but also stop the operation of the first to third transition state voltage drop circuits 2a to 2c. It is also possible to suppress fluctuations in the internal power supply voltage VINT.
    [77] Moreover, it is preferable to form a fuse which can blow by a metal option or a laser etc. so that a user can freely set the number of steps of the delay circuit contained in the 4th circuit part 15b. The degree of freedom in design for the pulse widths of the first to third pulse signals PLSST1 to PLSST3 is improved.
    [78] (Modification of the second embodiment)
    [79] As shown in Fig. 11, a semiconductor integrated circuit according to a modification of the second embodiment includes first to third transition state voltage drop circuits 2a to 2c, first steady state voltage drop circuit 3a, The active state voltage drop circuit 7a, the transition detection circuit 8, and the capacitor 21 are provided. The active state voltage drop circuit 7a has the same circuit configuration as the first to third transition state voltage drop circuits 2a to 2c and the first and second steady state voltage drop circuits 3a and 3b shown in FIG. Has The internal power supply voltage VINT generated from the active state voltage drop circuit 7a is similar to the first to third transition state voltage drop circuits 2a to 2c and the first steady state voltage drop circuit 3a. Is applied. The transition detection circuit 8 outputs the first to third pulse signals PLSST1 to PLSST3 and the active signal PLSEN having different pulse widths.
    [80] The first to third pulse signals PLSST1 to PLSST3 are input to the control terminals 22a to 22c of the first to third transition state voltage drop circuits 2a to 2c, respectively. The active signal PLSEN is input to the control terminal 22f of the active state voltage drop circuit 7a.
    [81] The transition detection circuit 8 shown in FIG. 12 has a structure substantially the same as the transition detection circuit 5 shown in FIG. The difference from the transition detection circuit 5 shown in FIG. 9 is that the active signal PLSEN output from the second circuit section 13 is not only input to the third circuit section 14, but also external to the transition detection circuit 8. It is also extracted. The other structure of the transition detection circuit 8 of FIG. 12 is the same as that of the transition detection circuit 5 of FIG. 9.
    [82] As shown in Fig. 10, the active signal PLSEN is outputted while the internal circuit 1 is at least active state 11. Therefore, the active state voltage drop circuit 7a operates during the period of receiving the active signal PLSEN. By changing a part of the first and second steady state voltage drop circuits 3a and 3b shown in FIG. 8 into the active state voltage drop circuit 7a, the active state voltage drop circuit 7a in the standby state 10 is changed. Current consumption can be reduced.
    [83] As described above, the semiconductor integrated circuit according to the modification of the second embodiment increases the current supply capability in the active state 11, and thus the first to third transition state voltage drop circuits 2a to 2c in the standby state 10, The current consumption of the one steady state voltage drop circuit 3a and the active state voltage drop circuit 7a can be reduced.
    [84] As described above, the present invention has been described with reference to the first and second embodiments, and variations thereof, but the description and drawings which form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and operational techniques will be apparent to those skilled in the art from this disclosure.
    [85] For example, in the first and second embodiments and modifications thereof, the case where the number of the first to third transition state voltage drop circuits 2a to 2c is three has been described. It is not limited to this, The number of transition state voltage drop circuits may be 1, 2, or 4 or more. Similarly, the first and second steady state voltage drop circuits 3a and 3b may not only be two or one, but three or more. The same applies to the active state voltage drop circuit 7a.
    [86] Further, the present invention can also be implemented as a semiconductor memory having the semiconductor integrated circuits described in the first and second embodiments of the present invention, such as a static RAM (SRAM) in which memory contents are held as long as a power supply voltage is applied. . As shown in Fig. 13, the semiconductor memory 102 includes a memory circuit 100 that realizes the main functions of the semiconductor memory, such as writing, reading, and holding data, and the memory circuit 100 is active from the standby state 10. Only for a certain period after the change to 11, the first to third transition state voltage drop circuits 2a to 2c for generating the internal power supply voltage VINT supplied from the external power supply voltage VDD to the memory circuit 100 and the memory circuit 100. Is the standby state 10 and the active state 11, the first and second steady state voltage drop circuits (3a, 3b) for generating the internal power supply voltage VINT from the external power supply voltage VDD, and changes from the standby state 10 to the active state 11 And a transition detecting circuit 4 which detects and transmits the pulse signal PLSST having a pulse width corresponding to a predetermined period to the first to third transition state voltage drop circuits 2a to 2c.
    [87] The memory circuit 100 includes a memory array 121 having a plurality of memory cells arranged in a matrix shape, a row decoder 122 and a column selector 123 for selecting a desired memory cell, a sense amplifier 124, The address buffer circuit 127 connected to the write buffer 125, the address terminal 126 to which address data is input, the address terminal 126, the row decoder 122, and the column selector 123, respectively, Timing for controlling the operation timing at the time of writing or reading with the input / output terminal 105, the input buffer circuit 128 and the output buffer circuit 108 connected to the input / output terminal 105, and the control terminal 130. The control circuit 129 and the clock terminal 131 to which the clock signal CLK is input are provided.
    [88] The clock signal CLK includes the row decoder 122, the column selector 123, the sense amplifier 124, the write buffer 125, the address buffer circuit 127, the input buffer circuit 128, the output buffer circuit 108, The control circuit 129 and the transition detection circuit 4 are respectively supplied. In addition, the internal power supply voltage VINT includes the memory array 121, the row decoder 122, the column selector 123, the sense amplifier 124, the write buffer 125, the address buffer circuit 127, and the input buffer circuit 128. To the output buffer circuit 108 and the control circuit 129, respectively.
    [89] The address data is input from the address terminal 126 and supplied to the row decoder 122 and the column selector 123 through the address buffer circuit 127. By the address data, a desired write memory cell or read memory cell in the memory array 121 is selected. At the time of writing, the write data input from the input / output terminal 105 is given to the write buffer 125 via the input buffer circuit 128 and written to the desired write cell of the memory array 121. On the other hand, at the time of reading, read data read from the selected read cell is given to the output buffer circuit 108 through the sense amplifier 124, and the semiconductor memory 102 from the output buffer circuit 108 through the input / output terminal 105. Is driven out of the.
    [90] The timing control signal input from the control terminal 130 is supplied from the timing control circuit 129 to the row decoder 122, the column selector 123, the sense amplifier 124, and the write buffer 125, respectively, and writes. Control of the operation timing at the time of reading or reading is performed.
    [91] The above-described embodiments are to be considered in all respects only as illustrative and not restrictive. It is intended that the scope of the invention be defined not by the foregoing description of the embodiments, but rather by the claims, and shall include such modifications as come within the meaning and range equivalent to the claims.
    [92] According to the present invention, even if the current consumption of the internal circuit changes with the change from the standby state to the active state, the fluctuation of the internal power supply voltage can be reduced, and stable high-speed operation of the internal circuit can be realized.
    权利要求:
    Claims (20)
    [1" claim-type="Currently amended] With internal circuits,
    A transition state voltage drop circuit for generating an internal power supply voltage supplied from the external power supply voltage to the internal circuit only for a predetermined period after the internal circuit is changed from a standby state to an active state;
    And a steady state voltage drop circuit generating the internal power supply voltage from the external power supply voltage, while the internal circuit is in the standby state and the active state.
    [2" claim-type="Currently amended] The method of claim 1,
    A transition detection circuit for detecting a change from the standby state to the active state and transmitting a pulse signal having a pulse width corresponding to the predetermined period to the transition state voltage drop circuit,
    And the transition state voltage drop circuit generates the internal power supply voltage from the external power supply voltage during the period of receiving the pulse signal.
    [3" claim-type="Currently amended] The method of claim 1,
    And an active state voltage drop circuit for generating the internal power supply voltage from the external power supply voltage, at least during the period in which the internal circuit is in the active state.
    [4" claim-type="Currently amended] The method of claim 3,
    A change in the standby state to the active state is detected, and a pulse signal having a pulse width corresponding to the predetermined period is transmitted to the transition state voltage drop circuit, and at least the internal circuit is in the active state, active A transition detection circuit for transmitting a signal to the active state voltage drop circuit;
    The transition state voltage drop circuit generates the internal power supply voltage from the external power supply voltage during the period of receiving the pulse signal, and the active state voltage drop circuit generates the internal power supply voltage from the external power supply voltage during the reception of the active signal. And a semiconductor integrated circuit for generating said internal power supply voltage.
    [5" claim-type="Currently amended] The method of claim 1,
    A plurality of the transition state voltage drop circuits,
    And wherein the predetermined period is different for each of the transition state voltage drop circuits.
    [6" claim-type="Currently amended] The method of claim 5,
    A transition detection circuit for detecting a change from the standby state to the active state and transmitting a plurality of pulse signals having different pulse widths to the plurality of transition state voltage drop circuits, respectively,
    And the plurality of transition state voltage drop circuits respectively generate the internal power supply voltage from the external power supply voltage during the period of receiving the pulse signal.
    [7" claim-type="Currently amended] The method of claim 5,
    And an active state voltage drop circuit for generating the internal power supply voltage from the external power supply voltage, at least during the period in which the internal circuit is in the active state.
    [8" claim-type="Currently amended] The method of claim 7, wherein
    A period in which the change from the standby state to the active state is detected and each pulse signal having a different pulse width is transmitted to the plurality of transition state voltage drop circuits, and at least the internal circuit is in the active state, And a transition detection circuit for transmitting an active signal to the active state voltage drop circuit.
    The plurality of transition state voltage drop circuits generate the internal power supply voltage from the external power supply voltage, respectively, during the period of receiving the pulse signal, and the active state voltage drop circuit, the period of receiving the active signal, the external And generate said internal power supply voltage from a power supply voltage.
    [9" claim-type="Currently amended] The method of claim 1,
    And wherein the active state is a state in which a clock signal is being supplied to the internal circuit, and the standby state is a state in which the clock signal is not supplied to the internal circuit.
    [10" claim-type="Currently amended] The method of claim 2,
    The transition detection circuit includes first to fourth circuit portions connected in series,
    The first circuit unit detects the rise of the clock signal and outputs the first detection signal.
    The second circuit unit delays the period from the rising to the falling of the first detection signal, and outputs an active signal during the period when the internal circuit is at least in the active state,
    The third circuit unit detects the rising of the active signal and outputs a second detection signal,
    And said fourth circuit portion outputs a pulse signal by delaying a period from rising to falling of said second detection signal.
    [11" claim-type="Currently amended] Memory circuits,
    A transition state voltage drop circuit for generating an internal power supply voltage supplied from the external power supply voltage to the memory circuit only for a predetermined period after the memory circuit is changed from a standby state to an active state;
    And a steady state voltage drop circuit that generates the internal power supply voltage from the external power supply voltage, while the memory circuit is in the standby state and the active state.
    [12" claim-type="Currently amended] The method of claim 11,
    A transition detection circuit for detecting a change from the standby state to the active state and transmitting a pulse signal having a pulse width corresponding to the predetermined period to the transition state voltage drop circuit,
    And the transition state voltage drop circuit generates the internal power supply voltage from the external power supply voltage during the period of receiving the pulse signal.
    [13" claim-type="Currently amended] The method of claim 11,
    And an active state voltage drop circuit for generating said internal power supply voltage from said external power supply voltage, at least during said memory circuit being in said active state.
    [14" claim-type="Currently amended] The method of claim 13,
    A change in the standby state to the active state is detected, and a pulse signal having a pulse width corresponding to the predetermined period is transmitted to the transition state voltage drop circuit, and at least the memory circuit is in the active state. And a transition detection circuit for transmitting a signal to the active state voltage drop circuit.
    The transition state voltage drop circuit generates the internal power supply voltage from the external power supply voltage during the period of receiving the pulse signal, and the active state voltage drop circuit generates the internal power supply voltage from the external power supply voltage during the reception of the active signal. And a semiconductor memory generating the internal power supply voltage.
    [15" claim-type="Currently amended] The method of claim 11,
    A plurality of the transition state voltage drop circuits,
    And said predetermined period is different for each of said transition state voltage drop circuits.
    [16" claim-type="Currently amended] The method of claim 15,
    A transition detection circuit for detecting a change from the standby state to the active state and transmitting a plurality of pulse signals having different pulse widths to the plurality of transition state voltage drop circuits, respectively,
    And the plurality of transition state voltage drop circuits respectively generate the internal power supply voltage from the external power supply voltage during the period of receiving the pulse signal.
    [17" claim-type="Currently amended] The method of claim 15,
    And an active state voltage drop circuit for generating said internal power supply voltage from said external power supply voltage, at least during said memory circuit being in said active state.
    [18" claim-type="Currently amended] The method of claim 17,
    A period in which the change from the standby state to the active state is detected and each pulse signal having a different pulse width is transmitted to the plurality of transition state voltage drop circuits, and at least the memory circuit is in the active state, And a transition detection circuit for transmitting an active signal to the active state voltage drop circuit.
    The plurality of transition state voltage drop circuits generate the internal power supply voltage from the external power supply voltage, respectively, during the period of receiving the pulse signal, and the active state voltage drop circuit, the period of receiving the active signal, the external And generating the internal power supply voltage from a power supply voltage.
    [19" claim-type="Currently amended] The method of claim 11,
    The active state is a state in which a clock signal is supplied to the memory circuit, and the standby state is a state in which the clock signal is not supplied to the memory circuit.
    [20" claim-type="Currently amended] The method of claim 12,
    The transition detection circuit includes first to fourth circuit portions connected in series,
    The first circuit unit detects the rise of the clock signal and outputs the first detection signal.
    The second circuit unit delays the period from the rising to the falling of the first detection signal, and outputs an active signal during the memory circuit being at least in the active state,
    The third circuit unit detects the rising of the active signal and outputs a second detection signal,
    And said fourth circuit portion outputs a pulse signal by delaying a period from rising to falling of said second detection signal.
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    同族专利:
    公开号 | 公开日
    KR100506108B1|2005-08-05|
    JP2003101396A|2003-04-04|
    US20030058032A1|2003-03-27|
    JP3892692B2|2007-03-14|
    US6759896B2|2004-07-06|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-09-21|Priority to JPJP-P-2001-00290131
    2001-09-21|Priority to JP2001290131A
    2002-09-19|Application filed by 가부시끼가이샤 도시바
    2003-03-29|Publication of KR20030025882A
    2005-08-05|Application granted
    2005-08-05|Publication of KR100506108B1
    优先权:
    申请号 | 申请日 | 专利标题
    JPJP-P-2001-00290131|2001-09-21|
    JP2001290131A|JP3892692B2|2001-09-21|2001-09-21|Semiconductor integrated circuit|
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