Semiconductor device having a shallow trench isolation and method of fabricating the same

专利摘要:
A semiconductor device having shallow trench isolation is provided and a method of manufacturing the same. The apparatus includes an element isolation film disposed in a predetermined region of a semiconductor substrate to define an active region. A gate electrode is disposed across the active region. An oxide layer pattern is interposed between the active region and the edge of the gate electrode along an edge of the gate electrode. The oxide layer pattern defines a channel region under the gate electrode. A low concentration diffusion layer exists in the active region under the oxide film pattern and on both sides of the gate electrode, and a high concentration diffusion layer shallower than the low concentration diffusion layer exists in the predetermined active region on both sides of the gate electrode. In the manufacturing method of this device, a trench isolation layer is formed in a predetermined region of a semiconductor substrate to define an active region. In the active region, a pair of preliminary low concentration diffusion layers are formed to cross the active region side by side. Subsequently, an oxide film pattern covering at least the upper portion of each of the preliminary low concentration diffusion layers is formed. The oxide film pattern defines a channel region. Subsequently, a gate oxide film is formed on the channel region, and a gate electrode covering the channel region and crossing the active region is formed. The edge of the gate electrode overlaps the oxide film pattern. Subsequently, a low concentration diffusion layer and a high concentration diffusion layer shallower than the low concentration diffusion layer are formed in the active regions on both sides of the gate electrode.
公开号:KR20030018677A
申请号:KR1020010052924
申请日:2001-08-30
公开日:2003-03-06
发明作者:김명수
申请人:삼성전자주식회사；
IPC主号:

专利说明:

A semiconductor device having shallow trench isolation and a method for manufacturing the same {SEMICONDUCTOR DEVICE HAVING A SHALLOW TRENCH ISOLATION AND METHOD OF FABRICATING THE SAME}
[10] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a trench region for device isolation and a LOCOS region for reducing leakage current.
[11] In the operation of the semiconductor device, leakage current causes a malfunction of the semiconductor device. One of the leakage currents is a gate induced drain leakage current (GIDL current). The GIDL current is generated in the drain region overlapping the gate electrode.
[12] 1 is a plan view for explaining a conventional semiconductor device.
[13] FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device taken along line II ′ in FIG. 1.
[14] 1 and 2, in a general semiconductor device, an isolation layer 102 is disposed in a predetermined region of a semiconductor substrate 100 to define an active region 104. The gate electrode 124 crosses the upper portion of the active region 104. A gate insulating layer 122 is interposed between the gate electrode 124 and the active region 104, and a shallow channel diffusion layer 106a is present in the active region 104 under the gate insulating layer 122. The source region 130 and the drain region 132 exist in the active region 104 adjacent to the channel diffusion layer 106a. The source region 130 and the drain region 132 have a region overlapping the gate electrode 124.
[15] FIG. 3 is a view illustrating portion A of FIG. 2 to describe gate induced drain leakage of a semiconductor device.
[16] Referring to FIG. 3, gate induced drain leakage is caused by band to band tunneling due to a high electric field between gate electrode 124 and drain region 132. Accordingly, a leakage current in which charge flows out toward the semiconductor substrate 200 having a lower potential than the drain region 132 is generated.
[17] Another leakage current is a subthreshold leakage current in which the transistor is turned on at a voltage lower than the operating voltage and current flows under the gate electrode.
[18] 4 is a cross-sectional view taken along the line II-II 'of FIG. 1 in order to explain the subthreshold leakage current of the semiconductor device.
[19] Referring to FIG. 4, when the shallow trench isolation device is applied, an inverse narrow effect due to the thin gate insulating layer 122 existing at the boundary B between the active region 104 and the device isolation layer 102 is applied. width effect) may occur. Accordingly, the transistor is turned on at a gate voltage below the operating voltage, and a subthreshold leakage current is generated across the lower portion of the gate electrode 124.
[20] SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having a structure capable of preventing gate induced drain leakage and a method of manufacturing the same.
[21] Another object of the present invention is to provide a semiconductor device having a structure capable of reducing a subthreshold leakage current flowing between an active region and a device isolation layer, and a method of manufacturing the same.
[22] Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same having excellent operating characteristics at high operating voltages.
[1] 1 is a plan view for explaining a conventional semiconductor device.
[2] FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device taken along line II ′ in FIG. 1.
[3] FIG. 3 is a view illustrating portion A of FIG. 2 to describe gate induced drain leakage of a semiconductor device.
[4] 4 is a cross-sectional view taken along the line II-II 'of FIG. 1 in order to explain the subthreshold leakage current of the semiconductor device.
[5] 5 is a perspective view for explaining the structure of a semiconductor device according to an embodiment of the present invention.
[6] 6A through 10A are process plan views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
[7] 6B through 10B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, taken along III-III ′ of FIGS. 6A through 10A, respectively.
[8] 11A through 11B and 15 are process plan views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
[9] 11B through 14B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, taken along line IV-IV ′ of FIGS. 11A through 14A, respectively.
[23] In order to achieve the above objects, the present invention provides a semiconductor device having a thick oxide film pattern at least under the gate electrode edge. The apparatus includes a trench device isolation film disposed in a squeezed region of a semiconductor substrate to define an active region. Gate electrodes intersecting the active region are disposed, and first and second conductive regions are formed in the active regions on both sides of the gate electrode and have regions overlapping edges of the gate electrodes. An oxide film pattern is interposed between at least each of the first and second conductive regions and the gate electrode. A gate insulating film is interposed between the active region and the gate electrode. Each of the first and second conductive regions includes a high concentration diffusion layer and a low concentration diffusion layer. The high concentration diffusion layer may be on the low concentration diffusion layer and exist in the active region at predetermined intervals from the oxide layer pattern, or may be present in the active region in contact with the oxide layer pattern. The oxide layer pattern may be interposed on each of the first and second conductive regions and the gate electrode in parallel with the gate electrode. Alternatively, both ends of the oxide layer pattern may extend below the gate electrode to further cover a boundary between the device isolation layer and the active region. That is, the oxide layer pattern may have a closed shape.
[24] In order to achieve the above objects, the present invention provides a method of manufacturing a semiconductor device. This method includes forming a thick oxide film pattern in a region where the gate electrode and the drain overlap each other. To this end, first, a trench isolation layer is formed in a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary low concentration diffusion layers are formed in the active region. The preliminary low concentration diffusion layer crosses the active area side by side. Subsequently, an oxide film pattern covering at least an upper portion of each of the preliminary low concentration diffusion layers and defining a channel region in a predetermined region of the active region is formed. A gate oxide film is formed on the channel region. Subsequently, the gate oxide layer covers the entire surface of the gate oxide layer and crosses the active region, and an edge thereof forms a gate electrode overlapping the oxide layer pattern. Impurities are implanted into the active region using the gate electrode as an ion implantation mask to form a low concentration diffusion layer including the preliminary low concentration diffusion layer, and a high concentration diffusion layer shallower than the low concentration diffusion layer is formed on the low concentration diffusion layer. The oxide layer patterns have a thickness greater than that of the gate oxide layer.
[25] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, if it is mentioned that the layer is on another layer or substrate, it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.
[26] 5 is a perspective view for explaining the structure of a semiconductor device according to an embodiment of the present invention.
[27] Referring to FIG. 5, a trench isolation layer 202 is disposed in a predetermined region of the semiconductor substrate 200. The trench isolation layer 202 defines an active region 204. Gate electrodes 224 and 324 are disposed across the active region 204. First conductive regions 230 and 330 and second conductive regions 232 and 332 exist in the active regions 204 of both gate electrodes 224 and 324. The first conductive regions 230 and 330 and the second conductive regions 232 and 332 respectively correspond to source and drain regions of the transistor. Oxide layer patterns 218 and 318 are interposed between the source regions 230 and 330 and the drain regions 232 and 332 and the gate electrodes 224 and 324, respectively. Both ends of the oxide layer patterns 218 and 318 may extend below the gate electrodes 218 and 318 to be connected to each other to further cover a boundary between the active region 204 and the device isolation layer 202. Shallow channel diffusion layers 206a and 306a exist in the active region 204 under the gate electrodes 224 and 324. The channel diffusion layers 206a and 306a may extend to the lower portions of the oxide patterns 218 and 318 to contact the source regions 230 and 330 and the drain regions 232 and 332. Gate insulating layers 222 and 322 are interposed between the channel diffusion layers 206a and 306a and the gate electrodes 224 and 324. The oxide layer patterns 218 and 318 may have a thickness greater than that of the gate insulating layer. At least the drain regions 232 and 332 are preferably formed of a DDD structure including the low concentration diffusion layers 226 and 326 and the high concentration diffusion layers 228 and 328. The low concentration diffusion layers 226 and 326 are present under the oxide patterns 218 and 318 and in the active region 204 outside the oxide patterns 218 and 318. The high concentration diffusion layers 228 and 328 are disposed on the low concentration diffusion layers 226 and 326 outside the oxide layer patterns 218 and 318. That is, the high concentration diffusion layers 228 and 328 exist at a shallower depth than the low concentration diffusion layers 226 and 326. The high concentration diffusion layers 228 and 328 may be present in the active region 204 at predetermined intervals from the oxide layer patterns 218 and 318. Alternatively, the high concentration diffusion layers 228 and 328 may be formed in the active region 204 adjacent to the oxide layer patterns 218 and 318. The low concentration diffusion layers 226 and 326 contact the channel diffusion layers 206a and 306a under the oxide pattern 218 and 318. Alternatively, the low concentration diffusion layers 226 and 326 may be formed to be spaced apart from the channel diffusion layers 206a and 306a by a predetermined distance.
[28] As shown, according to the present invention, oxide patterns 218 and 318 are interposed between the gate electrode 224 and the drain regions 232 and 332. Therefore, a low electric field is applied between the gate electrode 224 and the drain regions 232 and 332. Accordingly, the GIDL current is prevented from flowing between the drain regions 232 and 332 adjacent to the gate electrodes 224 and 324 and the semiconductor substrate 200 by band-to-band tunneling.
[29] In addition, when the oxide layer patterns 218 and 318 cover a boundary between the active region 204 and the trench isolation layer 202 under the gate electrodes 224 and 324, an inverse narrow width effect ) To prevent subthreshold current from flowing.
[30] 6A through 10A are process plan views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
[31] 6B through 10B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, taken along III-III ′ of FIGS. 6A through 10A, respectively.
[32] 6A and 6B, an isolation region 202 is formed in a predetermined region of the semiconductor substrate 200 to define the active region 204. A shallow impurity diffusion layer 206 is formed in the active region 204. The device isolation layer 202 is formed using a shallow trench isolation technology.
[33] 7A and 7B, a buffer oxide film and an anti-oxidation film are formed on the entire surface of the semiconductor substrate 200 on which the shallow impurity diffusion layer 206 is formed. The buffer oxide film is preferably formed of a thermal oxide film. The antioxidant film is preferably formed of a silicon nitride film. Subsequently, a first photoresist pattern 214 is formed on the antioxidant layer. The first photoresist pattern 214 covers the upper portion of the device isolation layer 202 and has a pair of side-by-side exposed regions 212 that expose a predetermined region of the antioxidant layer across the active region 204. Subsequently, at least the antioxidant layer and the buffer oxide layer are etched using the first photoresist pattern 214 as an etching mask to form a buffer oxide layer pattern 218 and an oxide layer pattern 210 which are sequentially stacked. The stacked buffer oxide layer pattern 218 and the antioxidant layer pattern 210 cover the isolation layer 202 and expose a predetermined active region 204.
[34] 8A and 8B, a pair of preliminary low concentration diffusion layers 216 parallel to each other in one direction are formed in the active region 204 using the first photoresist pattern 214 as an ion implantation mask. Subsequently, the first photoresist pattern 214 is removed and a thermal oxidation process is applied to the semiconductor substrate 200 to form a pair of oxide layer patterns 218 that cross the active region 204. During the thermal oxidation process, the active region 204 under the antioxidant pattern 210 is not oxidized, and only the exposed active region is oxidized. That is, the oxide layer patterns 218 cover the upper portions of the preliminary low concentration diffusion layers 216. In this case, it is preferable that the preliminary low concentration diffusion layers 216 remain under the oxide layer patterns 218 and 318. A channel region 220 is defined between the oxide layer patterns 218. The shallow impurity diffusion layer present in the channel region 220 corresponds to the channel diffusion layer 206a. Subsequently, the anti-oxidation layer pattern 210 and the buffer oxide layer pattern 218 are sequentially removed to expose the active region 204 and the device isolation layer 202.
[35] 9A and 9B, a gate oxide film is formed on at least the entire surface of the active region 204 and a gate conductive film is formed on the entire surface of the semiconductor substrate 200 on which the gate oxide film is formed. The gate conductive film is preferably formed of polysilicon or polyside. Subsequently, at least the gate conductive layer is patterned to form a gate electrode 224 crossing the active region 204. As shown, the gate electrode 224 covers the upper portion of the channel diffusion layer 206a, and the edge of the gate electrode 224 is positioned on the oxide layer patterns 218. A gate oxide layer is interposed between the gate electrode 224 and the channel region 220.
[36] 10A and 10B, a low concentration diffusion layer 226 including the preliminary low concentration diffusion layer 216 is formed by implanting impurities into the active region 204 using the gate electrode 224 as an etching mask. . The low concentration diffusion layer 226 is present under the oxide patterns 218 and in the active region 204 outside the oxide patterns 218. Subsequently, a high concentration diffusion layer 228 is formed in the active region 204 exposed on both sides of the gate electrode 224. The high concentration diffusion layer 228 has a shallower depth than the low concentration diffusion layer 226. That is, the high concentration diffusion layer 228 is present on the low concentration diffusion layer 226. The high concentration diffusion layer 228 may be formed to be surrounded by the low concentration diffusion layer 226a in a predetermined active region on both sides of the gate electrode 224 using a photolithography process. In addition, the gate electrode 224 and the oxide layer patterns 218 may be formed on the entire surface of the active region on both sides of the gate electrode 224 using the ion implantation mask.
[37] 11A through 11B and 15 are process plan views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
[38] 11B through 14B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, taken along line IV-IV ′ of FIGS. 11A through 14A, respectively.
[39] The second embodiment of the present invention provides a method of preventing subthreshold leakage current at the edge of the active region in addition to the first embodiment described above.
[40] 11A and 11B, an isolation layer 202 is formed in a predetermined region of the semiconductor substrate 200 to define the active region 204. The device isolation layer 202 is formed using a shallow trench isolation technique. Next, a shallow impurity diffusion layer 306 is formed in the active region 204.
[41] 12A and 12B, a buffer oxide film and an anti-oxidation film are formed on the entire surface of the semiconductor substrate 200 on which the shallow impurity diffusion layer 306 is formed. The process of forming the buffer oxide film and the antioxidant film is the same as in the first embodiment described above. Subsequently, at least the antioxidant layer and the buffer oxide layer are patterned in order to form a buffer oxide layer pattern 308 and an antioxidant layer pattern 310 which are sequentially stacked. The stacked buffer oxide layer pattern 308 and the antioxidant layer pattern 310 have an opening 312 surrounding the predetermined active region 204. The opening 312 may include the active region 204 and the device isolation layer 202 between the pair of first openings 312a and the first openings 312a that cross the active region 204 side by side. ) And a pair of side-by-side second openings 312b exposed. Next, a photoresist pattern 314 is formed to cover a boundary between the active region 204 and the device isolation layer 202 exposed in the second opening 312b.
[42] 13A and 13B, the photoresist pattern 314 and the stacked buffer oxide pattern 218 and the antioxidant pattern 310 are used as ion implantation masks to be parallel to each other in the active region 204. A pair of preliminary low concentration diffusion layers 316 is formed. Each of the preliminary low concentration diffusion layers 316 is formed along each of the first openings 312a. Subsequently, the photoresist pattern 314 is removed and a thermal oxidation process is applied to the semiconductor substrate 200. As a result, an oxide film pattern 318 surrounding the predetermined active region is formed. At this time, the preliminary low concentration diffusion layer 326a remains under the oxide film pattern 318. The region surrounded by the oxide layer pattern 318 corresponds to the channel region 220. The shallow impurity diffusion layer present in the channel region 220 corresponds to the channel diffusion layer 306a. The oxide layer pattern 318 covers a boundary between the active region 204 adjacent to the channel diffusion layer 306a and the device isolation layer 202. Accordingly, the boundary between the active region 204 adjacent to the channel region 220 is oxidized so that the boundary between the active region 204 and the device isolation layer 202 has a gentle structure. Subsequently, the stacked oxide film pattern 310 and the buffer oxide film pattern 308 are removed to expose the active region 204.
[43] 14A and 14B, a gate insulating film 322 is formed on at least the exposed active region 204, and a gate conductive film is formed on the entire surface of the semiconductor substrate 200 on which the gate insulating film is formed. At least the gate conductive layer is patterned to form a gate electrode 324 crossing the active region 204. The gate electrode 324 covers the entire surface of the channel region 320. A gate insulating layer 322 is interposed between the gate electrode 324 and the channel region 320. An edge of the gate electrode 324 is positioned on the oxide layer pattern 318.
[44] Referring to FIG. 15, impurities are implanted into the active region using the gate electrode 324 as an ion implantation mask. As a result, a low concentration diffusion layer 326 including the preliminary low concentration diffusion layer 326 is formed in the active region 304 on both sides of the gate electrode 324. The low concentration diffusion layer 326 is present under the oxide patterns 318 positioned at the edge of the gate electrode 324 and in the active region 204 outside the oxide patterns 318. Like the first embodiment described above, the low concentration diffusion layer 326 may be in contact with the channel diffusion layer 306 and the oxide pattern 318 below or spaced a predetermined distance.
[45] Subsequently, a high concentration diffusion layer 328 is formed in the active region 204 on both sides of the gate a electrode 324 in the same manner as in the first embodiment. The high concentration diffusion layer 328 is formed to have a shallower depth than the low concentration diffusion layer 326. In addition, the high concentration diffusion layer 328 may be formed to be spaced apart from the device isolation layer 202 and the gate electrode 324 to be surrounded by the low concentration diffusion layer 326. The high concentration diffusion layer 328 and the low concentration diffusion layer 326 constitute a source region 330 and a drain region 332 at both sides of the gate electrode 324.
[46] As a result, in the second embodiment of the present invention, a thick oxide film pattern exists between the drain region overlapping the gate electrode, and an oxide film pattern exists on the boundary between the active region and the device isolation film. Thus, as in the first embodiment described above, the gate induced drain leakage current can be prevented, and further, the subthreshold leakage current flowing along the active region boundary can be reduced.
[47] As described above, according to the present invention, the gate induced drain leakage can be prevented by forming a thick oxide film pattern between the gate electrode and the drain region.
[48] In addition, by forming a thick oxide film at the boundary between the active region existing below the gate electrode and the device isolation film, it is possible to prevent the subthreshold leakage current caused by the reverse narrowing effect.

权利要求:
Claims (17)
[1" claim-type="Currently amended] A trench isolation layer disposed in the bottom region of the semiconductor substrate to define an active region;
A gate electrode crossing the active region;
First and second conductive regions formed in active regions on both sides of the gate electrode and having regions overlapping edges of the gate electrode;
An oxide film pattern interposed between at least each of the first and second conductive regions and the gate electrode; And
And a gate insulating layer interposed between the active region and the gate electrode, wherein the oxide layer pattern is thicker than the gate insulating layer.
[2" claim-type="Currently amended] According to claim 1,
Wherein each of the first and second conductive regions comprises a high concentration diffusion layer and a low concentration diffusion layer, wherein the high concentration diffusion layer is on top of the low concentration diffusion layer.
[3" claim-type="Currently amended] The method of claim 2,
And the high concentration diffusion layer is formed in the active region at a predetermined distance from the oxide film pattern.
[4" claim-type="Currently amended] The method of claim 2,
And the high concentration diffusion layer is formed in the active region in contact with the oxide layer pattern.
[5" claim-type="Currently amended] According to claim 1,
And a channel diffusion layer in an active region under the gate electrode.
[6" claim-type="Currently amended] According to claim 1,
And the oxide layer pattern is interposed between an edge of the gate electrode and the active region to cross the active region side by side in one direction.
[7" claim-type="Currently amended] According to claim 1,
And both ends of the oxide layer patterns extend under the gate electrode to further cover a boundary between the active region and the device isolation layer below the gate electrode.
[8" claim-type="Currently amended] Forming a trench isolation layer in a predetermined region of the semiconductor substrate to define an active region;
Forming a pair of preliminary low concentration diffusion layers that cross the active area in one direction in the active area;
Forming an oxide film pattern covering at least an upper portion of each of the preliminary low concentration diffusion layers and defining a channel region in a predetermined active region;
Forming a gate oxide film on the channel region;
Forming a gate electrode covering the entire surface of the gate oxide layer in a direction parallel to the preliminary low concentration diffusion layer and crossing the active region, the edge of which overlaps the oxide pattern;
Implanting impurities into the active region using the gate electrode as an ion implantation mask to form a low concentration diffusion layer including the preliminary low concentration diffusion layer in the active regions on both sides of the gate electrode; And
And forming a high concentration diffusion layer shallower than the low concentration diffusion layer in the active regions on both sides of the gate electrode, wherein the thickness of the oxide pattern is thicker than the thickness of the gate oxide layer.
[9" claim-type="Currently amended] The method of claim 8,
Before forming the preliminary low concentration diffusion layers,
And implanting impurities into at least the regions between the preliminary low concentration diffusion layers to form a shallow impurity diffusion layer.
[10" claim-type="Currently amended] The method of claim 8,
Forming the preliminary low concentration diffusion layer,
Sequentially forming a buffer oxide film and an antioxidant film on the entire surface of the semiconductor substrate;
Forming a photoresist pattern having a pair of exposed areas on the antioxidant film, wherein the exposed areas are formed to expose the antioxidant film on the active area side by side in one direction;
Using at least one of the photoresist pattern as an etch mask to etch at least the antioxidant layer and the buffer oxide layer to form a buffer oxide layer pattern and an oxide layer pattern that are sequentially stacked to expose a predetermined active region;
Implanting a low concentration of impurities into the active region using the photoresist pattern as an ion implantation mask; and
Removing the photoresist pattern.
[11" claim-type="Currently amended] The method of claim 10,
Forming the oxide pattern and the gate oxide film,
Performing a thermal oxidation process on the semiconductor substrate from which the photoresist pattern has been removed to form an oxide layer pattern in the exposed active region, wherein the preliminary low concentration diffusion layer remains under the oxide layer pattern; and
Removing the antioxidant film to expose the buffer oxide film, wherein the buffer oxide film in a region defined by the oxide film pattern corresponds to a gate oxide film.
[12" claim-type="Currently amended] The method of claim 11, wherein
Forming the oxide pattern and the gate oxide film,
Performing a thermal oxidation process on the semiconductor substrate from which the photoresist pattern has been removed to form an oxide layer pattern in the exposed active region, wherein the preliminary low concentration diffusion layer remains under the oxide layer pattern;
Removing the antioxidant film and the buffer oxide film; and
Forming a gate oxide film over the active region from which the anti-oxidation film and the buffer oxide film are removed.
[13" claim-type="Currently amended] The method of claim 8,
Forming the preliminary low concentration diffusion layer,
Sequentially forming a buffer oxide film and an antioxidant film on the entire surface of the semiconductor substrate;
The antioxidant film and the buffer oxide film are sequentially patterned to form a buffer oxide film pattern and an antioxidant pattern, which are sequentially stacked, wherein the stacked buffer oxide pattern and the antioxidant pattern are a pair of first exposed sidewalls of the active region in one direction. Forming openings having second openings and having second openings in which boundaries between the device isolation layer and the active region between the first openings are exposed;
Forming a photoresist pattern covering the second openings and exposing at least the first openings;
Implanting impurities into the active region using the photoresist pattern as an ion implantation mask; and
Removing the photoresist pattern.
[14" claim-type="Currently amended] The method of claim 13,
Forming the oxide pattern and the gate oxide film,
Performing an annealing process on the semiconductor substrate from which the photoresist pattern has been removed to form an oxide film pattern in the first and second openings, but leaving the preliminary low concentration diffusion layer under the oxide film pattern; And
And removing the antioxidant film to expose the buffer oxide film, wherein the buffer oxide film in a region defined by the oxide film pattern corresponds to a gate oxide film.
[15" claim-type="Currently amended] The method of claim 13,
Forming the oxide pattern and the gate oxide film,
Performing a thermal oxidation process on the semiconductor substrate from which the photoresist pattern has been removed to form an oxide film pattern in the first and second regions, but leaving the preliminary low concentration diffusion layer under the oxide film pattern;
Removing the antioxidant film and the buffer oxide film; and
And forming a gate oxide film over the active region from which the antioxidant film and the buffer oxide film are removed.
[16" claim-type="Currently amended] The method of claim 8,
And the high concentration diffusion layer is formed to be surrounded by the low concentration diffusion layer at a predetermined distance from the oxide film pattern.
[17" claim-type="Currently amended] The method of claim 8,
Forming the high concentration diffusion layer;
Using the gate electrode and the oxide film pattern as an ion implantation mask to implant impurities into the active region to form a high concentration diffusion layer that is shallower than the low concentration diffusion layer.

类似技术:

---

公开号 | 公开日 | 专利标题

---

KR100515061B1|2005-09-14|Semiconductor devices having a fin field effect transistor and methods for forming the same

---

KR100190757B1|1999-06-01|Method of forming mosfet

---

US8188542B2|2012-05-29|Field effect transistors including variable width channels and methods of forming the same

---

KR100511045B1|2005-08-30|Integration method of a semiconductor device having a recessed gate electrode

---

JP3462301B2|2003-11-05|Semiconductor device and manufacturing method thereof

---

EP0370809B1|1994-03-02|Thin-film soi mosfet and method of manufacturing thereof

---

US7214591B2|2007-05-08|Method of fabricating high-voltage MOS device

---

US5565368A|1996-10-15|High density integrated semiconductor device and manufacturing method thereof

---

US5405795A|1995-04-11|Method of forming a SOI transistor having a self-aligned body contact

---

JP3854363B2|2006-12-06|Manufacturing method of SOI transistor

---

US7582533B2|2009-09-01|LDMOS device and method for manufacturing the same

---

US6538275B2|2003-03-25|Nonvolatile semiconductor memory device and method for fabricating the same

---

US7186618B2|2007-03-06|Power transistor arrangement and method for fabricating it

---

US6476444B1|2002-11-05|Semiconductor device and method for fabricating the same

---

US6613633B2|2003-09-02|Method for manufacturing a high power semiconductor device having a field plate extendedly disposed on a gate

---

KR100373665B1|2003-05-01|Process for selectively thickening gate oxide regions

---

JP4486032B2|2010-06-23|Method for manufacturing memory element

---

US7541642B2|2009-06-02|Semiconductor device with a gate electrode including a pair of polysilicon layers

---

JP4797265B2|2011-10-19|Semiconductor device and manufacturing method of semiconductor device

---

KR100905209B1|2009-07-01|Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region

---

JP4195293B2|2008-12-10|MOS gate power device having doped polysilicon body and manufacturing method thereof

---

US7166514B2|2007-01-23|Semiconductor device and method of manufacturing the same

---

JP3543117B2|2004-07-14|Double gate field effect transistor

---

US6924529B2|2005-08-02|MOS transistor having a recessed gate electrode and fabrication method thereof

---

US6867106B2|2005-03-15|Semiconductor device and method for fabricating the same

同族专利:

---

公开号 | 公开日

---

US7041563B2|2006-05-09|

---

US20030042544A1|2003-03-06|

---

US20040171202A1|2004-09-02|

---

US6727568B2|2004-04-27|

---

KR100395879B1|2003-08-25|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

法律状态:
2001-08-30|Application filed by 삼성전자주식회사

---

2001-08-30|Priority to KR20010052924A

---

2003-03-06|Publication of KR20030018677A

---

2003-08-25|Application granted

---

2003-08-25|Publication of KR100395879B1

优先权:

---

申请号 | 申请日 | 专利标题

---

KR20010052924A|KR100395879B1|2001-08-30|2001-08-30|Semiconductor device having a shallow trench isolation and method of fabricating the same|