• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In response to the self-refresh test mode signal, the control of the period of the external refresh pulse applied from the outside of the DRAM can be directly controlled to efficiently test the characteristics of the memory cell test, the refresh-related logic, and the self-refresh oscillator according to the change of the period of the external refresh pulse. A refresh circuit is disclosed. The DRAM self refresh circuit includes a refresh enable signal generation circuit for generating a refresh enable signal in response to a test mode signal or a power off signal, a pulse generation circuit for generating a refresh pulse in response to the refresh enable signal, and the test. And a selection circuit for selecting the refresh pulse or an external pulse input from the outside of the DRAM in response to a mode signal, wherein the DRAM performs self refresh in response to an output signal of the selection circuit and the refresh enable signal. . The self-refresh circuit of the DRAM further includes an output buffer for outputting the refresh pulse to the outside of the DRAM in response to the test mode signal, and may preferably vary the period or width of the external pulse.
    公开号:KR20030001826A
    申请号:KR1020010037633
    申请日:2001-06-28
    公开日:2003-01-08
    发明作者:신동학；한규한
    申请人:삼성전자 주식회사；
    IPC主号:
    专利说明:

    Self refresh circuit and self refresh method for semiconductor memory device
    [6] TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly, to a self refresh circuit and a method of a DRAM.
    [7] In general, a self refresh operation is used as a method of preserving data stored in the DRAM when the power supplied to the DRAM is interrupted. The cell refresh operation refreshes DRAM while sequentially changing an internal address in response to an externally input command signal.
    [8] 1 is a block diagram of a self refresh circuit of a conventional semiconductor memory device. Referring to FIG. 1, the refresh circuit 10 includes a power mode controller 1, a self refresh oscillator 3, a bank and row address counter 7, a RAS controller 5 and a core 9. do.
    [9] FIG. 2 shows a self refresh timing diagram of the refresh circuit 10 of FIG. 1. Hereinafter, the self refresh operation will be described in detail with reference to FIGS. 1 and 2.
    [10] The power mode controller 1 activates the refresh enable signal Refresh-en in response to the activation (eg, logic 'high') of the DRAM power supply stop signal PwrDn. The self refresh oscillator 3 generates a refresh pulse RFSH in response to the refresh enable signal Refresh-en.
    [11] The bank and row address counter 7 generates a counting address RRAdd which sequentially increases the bank and row address to be refreshed in response to the refresh enable signal Refresh-en and the refresh pulse RFSH.
    [12] The RAS controller 5 controls a signal related to a row address strobe signal (hereinafter, referred to as RAS), and includes a counting address (RRAdd), a refresh pulse (RFSH), and a refresh. Bit line sense amplifier enable signal (Bsense) for activating the bit line sense amplifier of the core 9 in response to the enable signal (Refresh-en), and precharge signal (Prech) and DRAM memory for precharging the bit line. A row address (Row Addr) that is counted sequentially is output for the cell refresh.
    [13] The core 9 is an area in which memory cells and a sense amplifier for sensing and amplifying data of the memory cells are disposed, and the bit line sense amplifier enable signal Bsense, precharge signal Prech, and low during a power supply interruption time. Self-refresh of the memory cells is performed in response to the address Row Addr.
    [14] However, since the conventional self refresh circuit 10 cannot vary the refresh pulse RFSH, which is the output signal of the self refresh oscillator 3, the interval between the bit line sense amplifier enable signal Bsense and the precharge signal Prech. Could not be changed. Therefore, there is a problem in that the memory cell test of the core 9 cannot be performed while the refresh cycle is changed.
    [15] In addition, as a logic test, whether the bank and row addresses RRAdd generated within the memory device change normally during the self-refresh operation, for example, when the refresh pulse RFSH toggles 10 times, the bank and row addresses RRAdd The problem is that you can't test exactly 10 toggles.
    [16] In addition, since there is no device that can output the refresh pulse RFSH to the outside, there is a problem in that the cycle of the refresh pulse RFSH cannot be tested.
    [17] The technical problem to be achieved by the present invention is to provide a refresh circuit that can test the characteristics of the cells of the memory, the self-refresh logic and the self-refresh cycle characteristics according to the refresh cycle while changing the refresh period to a predetermined value and a method thereof. It is.
    [1] The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.
    [2] 1 is a block diagram of a self refresh circuit of a conventional semiconductor memory device.
    [3] FIG. 2 illustrates the self refresh timing diagram of FIG. 1.
    [4] 3 is a block diagram of a self-refresh circuit of a semiconductor memory device according to an embodiment of the present invention.
    [5] 4 illustrates the self refresh timing diagram of FIG. 3.
    [18] Accordingly, the self-refresh circuit of the DRAM for achieving the above technical problem is a refresh enable signal generation circuit for generating a refresh enable signal in response to a test mode signal or a power off signal, and generates a refresh pulse in response to the refresh enable signal. And a selection circuit for selecting the refresh pulse or an external pulse input from the outside of the DRAM in response to the test mode signal, wherein the DRAM is connected to an output signal of the selection circuit and the refresh enable signal. Perform self refresh in response.
    [19] The self-refresh circuit of the DRAM further includes an output buffer for outputting the refresh pulse to the outside of the DRAM in response to the test mode signal, and may preferably vary the period or width of the external pulse.
    [20] In addition, the self-refresh method of DRAM for achieving the technical problem of the present invention comprises the steps of (a) generating a refresh enable signal in response to a test mode signal or a power-off signal, (b) refresh in response to the refresh enable signal Generating a pulse, (c) selecting the refresh pulse or an external pulse input from outside of the DRAM in response to the test mode signal, and (d) an output signal of the selection circuit and the refresh enable signal And in response to performing self refresh of the DRAM.
    [21] The self-refreshing method of the DRAM may further include outputting the refresh pulse to the outside of the DRAM in response to the test mode signal. The method of claim 4, wherein the period or width of the external pulse is variable. desirable.
    [22] In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.
    [23] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
    [24] 3 is a block diagram of a self refresh circuit 100 of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 3, the self refresh circuit 100 may include a power mode controller 11, a self refresh oscillator 13, a selection circuit 15, a transmission circuit 17, and a RAS controller. 19, a bank and row address counter 21, a core 23 and an output buffer 25 are provided.
    [25] 4 illustrates the self refresh timing diagram of FIG. 3. Since the self refresh operation is well known in the art, the following describes only the self refresh circuit 100 and its operation according to an embodiment of the present invention with reference to FIGS. 3 and 4.
    [26] The self refresh circuit 100 may operate the DRAM in the self refresh mode when the supply of the power supply voltage is momentarily interrupted or according to a user's selection.
    [27] The power supply mode controller 11 includes a logic circuit 11a, and the logic circuit 11a may operate the DRAM in the self refresh mode according to the interruption signal Pwrdn of the power supply voltage supplied to the DRAM or a user's selection. The refresh enable signal Refresh-en is output to the self refresh oscillator 13, the RAS controller 19, and the bank and row address counter 21 in response to the self refresh test mode signal SR TestMode. In the present invention, a description will be given of a case where the DRAM is operated in the self refresh mode according to a user's selection.
    [28] The self refresh oscillator 13 generates a refresh pulse RFSH having a predetermined pulse period and a pulse width in response to the refresh enable signal Refresh-en.
    [29] The selection circuit 15 may be configured as a multiplexer. The selection circuit 15 may include a refresh pulse RFSH or an external refresh pulse RFSH-EXT in response to the self refresh test mode signal SR TestMode and the RAS controller 19 and the bank and row addresses. Output to the counter 21. The external refresh pulse RFSH-EXT is a pulse having a predetermined period and pulse width by using a predetermined input means (for example, an input pin) outside the DRAM. The external refresh pulse RFSH-EXT period and the pulse width are DRAMs. Can be variable from outside.
    [30] For example, when the self-refresh test mode signal SR TestMode electrically connected to the selection terminal of the selection circuit 15 is activated, the selection circuit 15 receives the external refresh pulse RFSH-EXT input to the terminal A. Select to output the internal refresh signal RFSH_INT.
    [31] However, when the self refresh test mode signal S.R TestMode is deactivated, the selection circuit 15 selects the refresh pulse RFSH input to the terminal B and outputs the internal refresh signal RFSH_INT. In addition, the refresh pulse RFSH or the external refresh pulses RFSH-EXT, which are the output signals RFSH_INT of the selection circuit 15, perform the same function as the refresh pulse RFSH of FIG. 1.
    [32] The transfer circuit 17 is a transmission gate composed of MOS transistors, and the transfer circuit 17 transfers the refresh pulse RFSH to the output buffer 25 when the self refresh test mode signal SR TestMode is activated. The output buffer 25 is a predetermined output buffer provided in the DRAM and is used to test the refresh pulse RFSH outside the DRAM.
    [33] The bank and row address counter 21 generates a counting address RRAdd which sequentially increases the bank and row address to be refreshed in response to the refresh enable signal Refresh-en and the internal refresh pulse RFSH_INT.
    [34] The RAS controller 19 activates the bit line sense amplifier in response to the counting address RRAdd, the refresh enable signal Refresh-en, and the internal refresh pulse RFSH_INT, which is an output signal of the selection circuit 15. The bit line sense amplifier enable signal Bsense and the precharge signal Prech for precharging the bit line and the row address Row Addr sequentially counted for self refresh are output.
    [35] The core 23 is an area in which memory cells and a sense amplifier for sensing and amplifying data of the memory cells are disposed, and while the power supply stop signal PwrDn is activated or the self refresh test mode signal SR TestMode is activated. The self refresh is performed in response to the bit line sense amplifier enable signal Bsense, the precharge signal Prech, and the row address Row Addr.
    [36] Accordingly, the present invention activates the self-refresh test mode signal SR TestMode and directly controls the period of the external refresh pulse RFSH-EXT applied from the outside of the DRAM to test the operation of the bank and the row address counter 21. As it can be controlled, it is possible to test the characteristics of the memory cell according to the change of the period of the external refresh pulse (RFSH-EXT).
    [37] In addition, since the user can directly control the number and width of the external refresh pulses RFSH-EXT applied from the outside of the DRAM, the bank and row addresses for self refresh according to the change of the number of external refresh pulses RFSH-EXT. The change in the counting address RRAdd, which is an output signal of the counter 21, and the output address Row Addr of the RAS controller 19 can be tested.
    [38] In addition, by testing the output buffer output using the transmission circuit 17 and the output buffer 25, the cycle of the refresh pulse RFSH can be tested outside the DRAM. Therefore, the self-refresh cycle characteristics of the DRAM during normal operation can be tested. There are advantages to it.
    [39] Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
    [40] As described above, the refresh circuit according to the present invention activates the self refresh test mode signal SR TestMode to directly control the external refresh pulse RFSH-EXT applied from the outside of the DRAM to test the bank and row address counters. Since the operation of 21 can be controlled, there is an advantage in that the characteristics of the memory cell according to the cycle change of the external refresh pulse RFSH-EXT can be tested.
    [41] In addition, since the user can directly control the number and width of the external refresh pulses RFSH-EXT applied from the outside of the DRAM, the bank and row addresses for self refresh according to the change of the number of external refresh pulses RFSH-EXT. The change in the counting address RRAdd, which is an output signal of the counter 21, and the output address Row Addr of the RAS controller 19 can be tested.
    [42] In addition, by testing the output buffer output using the transmission circuit 17 and the output buffer 25, the cycle of the refresh pulse RFSH can be tested outside the DRAM. Therefore, the self-refresh cycle characteristics of the DRAM during normal operation can be tested. There are advantages to it.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] In the self-refresh circuit of DRAM,
    A refresh enable signal generation circuit configured to generate a refresh enable signal in response to a test mode signal or a power off signal;
    A pulse generation circuit for generating a refresh pulse in response to the refresh enable signal;
    A selection circuit for selecting an external pulse input from the outside of the refresh pulse or the DRAM in response to the test mode signal,
    And the DRAM performs self refresh in response to an output signal of the selection circuit and the refresh enable signal.
    [2" claim-type="Currently amended] The method of claim 1, wherein the self-refresh circuit of the DRAM,
    And an output buffer configured to output the refresh pulse to the outside of the DRAM in response to the test mode signal.
    [3" claim-type="Currently amended] 2. The self-refresh circuit of claim 1, wherein the period or width of the external pulses can be varied.
    [4" claim-type="Currently amended] In the self-refresh method of DRAM,
    (a) generating a refresh enable signal in response to a test mode signal or a power down signal;
    (b) generating a refresh pulse in response to the refresh enable signal;
    (c) selecting an external pulse input from the outside of the refresh pulse or the DRAM in response to the test mode signal; And
    and (d) performing self-refresh of the DRAM in response to an output signal of the selection circuit and the refresh enable signal.
    [5" claim-type="Currently amended] The method of claim 4, wherein the self-refresh method of the DRAM,
    And outputting the refresh pulse to the outside of the DRAM in response to the test mode signal.
    [6" claim-type="Currently amended] 5. The method of claim 4, wherein the period or width of the external pulses can be varied.
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    同族专利:
    公开号 | 公开日
    KR100712492B1|2007-05-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-06-28|Application filed by 삼성전자 주식회사
    2001-06-28|Priority to KR1020010037633A
    2003-01-08|Publication of KR20030001826A
    2007-05-02|Application granted
    2007-05-02|Publication of KR100712492B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020010037633A|KR100712492B1|2001-06-28|2001-06-28|Self refresh circuit and self refresh method for dynamic random access memory|
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