• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A data output buffer operated at a supply voltage of a wide range and a semiconductor memory device using the same are provided to output rapidly cell data to the outside in a memory reading process by improving a structure of the data output buffer. CONSTITUTION: A data output portion is formed with the first PMOS transistor(101) having a gate for receiving a gate driving voltage generated by input data, a drain connected selectively with a power terminal, and a source connected with an output terminal of a data output buffer. An intermediate voltage generation portion(203) generates an intermediate voltage of a supply voltage applied from the power terminal. The first switch(205) is used for connecting selectively the intermediate voltage with the gate of the first PMOS transistor(101). The second switch(207) is used for connecting selectively a gate driving voltage with the gate of the first PMOS transistor(101). A control portion(209) applies the intermediate voltage to the gate of the first PMOS transistor(101) by controlling the first switch(205). In addition, the control portion(209) applies the gate driving voltage to the gate of the first PMOS transistor(101) by controlling the second switch(207).
    公开号:KR20030000845A
    申请号:KR1020010036999
    申请日:2001-06-27
    公开日:2003-01-06
    发明作者:김태경
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    A data output buffer that operates over a wide range of supply voltages and a semiconductor memory device using the same {A DATA OUTPUT BUFFER OPERATING ON WIDE SOURCE VOLTAGE AND A SEMICONDUCTOR MEMORY DEVICE USING THIS BUFFER}
    [8] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer and a semiconductor memory device using the same, and more particularly, to a data output buffer improved to quickly output cell data to the outside in a memory read operation. The present invention can be applied to non-memory devices as well as memory devices such as slow SRAM.
    [9] The conventional data output buffer is controlled by a buffer enable signal Poe to output cell data, as shown in FIG. 1, and has a large size when outputting high level data. It outputs by turning on the PMOS transistor 101. However, since the PMOS transistor 101 has a high threshold voltage Vtp for operation under low Vcc, low temperature, and the like, the current driving capability of the PMOS transistor 101 is reduced, resulting in a drop in speed during data output. have.
    [10] Accordingly, an object of the present invention is to provide a data output buffer capable of operating at high speed even when outputting high-level cell data via a large sized PMOS transistor.
    [11] Another object of the present invention is to provide a data output buffer capable of outputting high-level cell data at high speed even for a wide range of power supply voltages Vcc.
    [1] 1 is a circuit diagram of a conventional data output buffer.
    [2] 2 is a block diagram of a data output buffer according to the present invention;
    [3] 3 is a block diagram of an intermediate voltage generation circuit according to the present invention;
    [4] 4 is a circuit diagram of a data output buffer according to an embodiment of the present invention.
    [5] Fig. 5 is a circuit diagram of a Vcc level detecting means according to the present invention.
    [6] 6 is a circuit diagram of control signal generating means.
    [7] 7 is a signal timing diagram in a data output buffer according to the present invention;
    [12] In order to achieve the above object, the present invention provides a data output buffer in which a gate driving voltage generated by input data is applied to a gate, a drain is selectively connected to a power supply terminal, and a source of the data output buffer is provided. A first PMOS transistor connected to an output terminal, an intermediate voltage generator for generating an intermediate voltage of a power supply voltage applied from the power supply terminal, and a first voltage for selectively applying the intermediate voltage to a gate of the first PMOS transistor A switch, a second switch for selectively applying the gate driving voltage to the gate of the first PMOS transistor, and after controlling the first switch to allow the intermediate voltage to be applied to the gate of the first PMOS transistor, The gate driving voltage is controlled to control the second switch so that the gate of the first PMOS transistor And a control unit to be applied to the gate.
    [13] Before the gate driving voltage is applied to the first PMOS transistor, the drain and the power terminal of the first PMOS transistor are disconnected. When the gate driving voltage is applied to the first PMOS transistor, It is preferable to further include a third switch for connecting the power supply terminal. The gate driving voltage is applied to a gate, a drain is connected to the power supply terminal, a source is connected to an output terminal of the data output buffer, and a second PMOS transistor having a smaller size than the first PMOS transistor is formed. It is preferable to further provide. The second switch consists of a transmission gate.
    [14] The intermediate voltage generating unit includes means for detecting the level of the power supply voltage, power supply voltage dropping means connected to the power supply terminal, and outputting a plurality of dropping voltages differently dropped from the power supply voltage, and the power supply voltage level detecting means. It is controlled by an output signal, and is provided with a switching means for providing a dropping voltage lowered more from the power supply voltage to the output terminal of the intermediate voltage generating unit as the power supply voltage is larger.
    [15] In another aspect, the present invention provides a data output buffer, wherein a gate driving voltage generated by input data is applied to a gate, a drain is selectively connected to a power supply terminal, and a source is connected to an output terminal of the data output buffer. A transistor, an intermediate voltage generator for generating an intermediate voltage having a predetermined magnitude dropped from the power supply voltage according to a level of the power supply voltage, and a first voltage for selectively applying the intermediate voltage to a gate of the first PMOS transistor; A switch, a second switch for selectively applying the gate driving voltage to the gate of the first PMOS transistor, and after controlling the first switch to allow the intermediate voltage to be applied to the gate of the first PMOS transistor, The gate switch voltage is controlled to control the second switch so that the gate of the first PMOS transistor And a drain and the power terminal of the first PMOS transistor before the gate driving voltage is applied to the first PMOS transistor, and the gate driving voltage is applied to the first PMOS transistor. A third switch connecting the drain of the first PMOS transistor and the power supply terminal, the gate driving voltage is applied to a gate, the drain is connected to the power supply terminal, and a source is connected to an output terminal of the data output buffer. And a second PMOS transistor having a smaller size than that of the first PMOS transistor.
    [16] According to another aspect of the present invention, there is provided a semiconductor memory device, comprising: a memory unit for storing data and a data output buffer for outputting data stored in the memory unit, wherein the data output buffer includes a gate driving voltage generated by input data. And a drain is selectively connected to a power supply terminal, and a source is a first PMOS transistor connected to an output terminal of the data output buffer, and an intermediate voltage having a predetermined magnitude drop from the power supply voltage according to a power supply voltage level. An intermediate voltage generator configured to generate a voltage, a first switch to selectively apply the intermediate voltage to a gate of the first PMOS transistor, and a gate drive voltage to be selectively applied to a gate of the first PMOS transistor And a second switch to control the first switch so that the intermediate voltage is A control unit for controlling the second switch to apply the gate driving voltage to the gate of the first PMOS transistor after being applied to the gate of the PMOS transistor, and before the gate driving voltage is applied to the first PMOS transistor A third switch connecting the drain and the power terminal of the first PMOS transistor when the drain and the power terminal of the first PMOS transistor are disconnected and the gate driving voltage is applied to the first PMOS transistor; A voltage is applied to the gate, a drain is connected to the power supply terminal, a source is connected to the output terminal of the data output buffer, and includes a second PMOS transistor having a relatively smaller size than the first PMOS transistor. do.
    [17] In addition, the present invention provides a method of driving a data output buffer comprising a PMOS transistor, the gate driving voltage generated by the input data is selectively applied to the gate, the drain is selectively connected to the power supply terminal, the source is connected to the output terminal. The method according to claim 1, wherein the intermediate voltage of the power supply voltage applied from the power supply terminal is generated while the gate driving voltage is not applied to the gate of the PMOS transistor, and the intermediate voltage is applied to the gate of the PMOS transistor. And applying the gate driving voltage to the gate of the PMOS transistor in a state in which it is not applied to the gate of the PMOS transistor.
    [18] Before the gate driving voltage is applied to the gate of the PMOS transistor, the drain and the power terminal of the PMOS transistor are disconnected. When the gate driving voltage is applied to the PMOS transistor, the drain of the PMOS transistor and the power terminal are connected. It is preferable to further comprise the step.
    [19] The generating of the intermediate voltage may include generating a level control signal by detecting a level of the power supply voltage, outputting a plurality of falling voltages differently dropped from the power supply voltage, and generating the level control signal according to the level control signal. The larger the power supply voltage is, the more the voltage drops from the power supply voltage.
    [20] According to the present invention having the configuration features as described above, when outputting high-level cell data, a voltage lower than Vcc / 2 is applied to the gate of the PMOS transistor having a large size before outputting the data. Conventionally, the gate voltage of the PMOS transistor varies from Vcc to GND. However, according to the present invention, the speed of turning on the PMOS transistor is improved since the voltage varies from Gcc to GND at a voltage lower than Vcc. When a high level data is output even at a high level Vcc or a low level Vcc, a voltage lower than Vcc / 2 is applied to the gate of the PMOS transistor before data output, thereby enabling high-speed operation even in a wide range of Vcc.
    [21] Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; Like reference numerals in the drawings indicate the same or similar components.
    [22] 2 is a block diagram of a data output buffer according to the present invention. As illustrated in FIG. 2, the data output buffer 200 according to the present invention includes a data output unit 201, an intermediate voltage generator 203, a first switch 205, a second switch 207, and a controller ( 209, a third switch, and the like. In FIG. 2, the PMOS transistor 101 is illustrated as being located outside the data output unit 201, but the actual PMOS transistor 101 is a component of the data output unit 201. Since the present invention is to improve the performance of the PMOS transistor 101 is shown separately.
    [23] In FIG. 2, sodin indicates a data signal output from a memory cell or the like. The first control signal Peq is a pulse having a short width when the address is changed, when the write enable signal / WE is disabled, or when the chip select signal / CS is enabled. It is generated externally to control the opening and closing of the first switch 205 and is input to the controller 209 and used to generate the second control signal Poe and the third control signal Poeb1. The second control signal Poe is a signal for operating the data output unit 201 and is generated by the controller 209 using the first control signal Peq. The second control signal Poe has a shape in which the first control signal Peq is delayed and sagging. The third control signal Poeb1 is a short pulse that detects the end of the second control signal Poe as described above with reference to FIG. 5.
    [24] First, the gate of the PMOS transistor 101 is connected to the gate driving terminal gd of the data output unit 201 via the second switch 207. The voltage output from the gate driving terminal gd to drive the gate of the PMOS transistor 101 is hereinafter referred to as "gate driving voltage". The gate driving voltage Vgd is generated at the data output unit 201 by the input data sodin and the second control signal Poe and selectively applied to the gate of the PMOS transistor 101. Whether it is applied or not is controlled by the opening and closing of the second switch 207. The drain of the PMOS transistor 101 is connected to the power supply terminal via the third switch 211. Therefore, the power supply voltage provided from the power supply terminal is selectively applied to the drain of the PMOS transistor 101 by opening and closing the third switch 211. The source of the PMOS transistor 101 is connected to the output terminal dout of the data output buffer 200.
    [25] The intermediate voltage generation unit 203 generates a voltage about the middle of the level of the power supply voltage Vcc and selectively provides the voltage to the gate G1 of the PMOS 101 by opening and closing the first switch 205. A detailed configuration will be described in detail with reference to FIG. 3.
    [26] Before the gate driving voltage Vgd is applied to the gate of the first PMOS transistor 101, the third switch 211 cuts off the drain D and the power supply terminal of the first PMOS transistor 101. When Vgd is applied to the gate G of the first PMOS transistor 101, the drain D and the power supply terminal of the first PMOS transistor 101 are connected. The third switch 211 is controlled by the second control signal Poe, and charges accumulated in the gate G of the PMOS transistor 101 by the intermediate voltage applied from the intermediate voltage generator 203 are stored in the PMOS transistor. It serves to prevent the flow toward the power supply terminal via 101.
    [27] The PMOS transistor 213 has a gate driving voltage Vgd applied to its gate G2, a drain D2 of which is connected to a power supply terminal, and a source S2 of which is connected to an output terminal dout. . The PMOS transistor 213 is relatively smaller in size than the PMOS transistor 101. Since the voltage output from the source S1 of the PMOS transistor 101 does not become Vcc due to the voltage drop by the third switch 211, the PMOS transistor 213 in order to make the voltage output from the output terminal dout become Vcc. ) Is required.
    [28] The controller 209 generates a second control signal Poe and a third control signal Poeb1 having an appropriate width and timing by using the first control signal Peq applied from the outside, and applies the data to each part. The operation of the entire buffer 200 is controlled. The point of the control performed by the controller 209 is to control the first switch 205 so that the intermediate voltage generated from the intermediate voltage generator 203 is first applied to the gate of the PMOS transistor 101, and then next. By controlling the second switch 207 so that the gate driving voltage Vgd is applied to the gate of the PMOS transistor 101, the input data sodin is buffered.
    [29] 3 is a block diagram of an intermediate voltage generation circuit according to the present invention. As illustrated in FIG. 3, the intermediate voltage generation circuit 203 according to the present invention includes a power supply voltage level detection unit 301, a switch unit 303, and a power supply voltage dropping unit 305. The specific circuit configuration of this component and the connection relationship between the components will be described in detail with reference to FIGS. 4 and 5. The intermediate voltage generating circuit 203 generates an approximately intermediate voltage of the power supply voltage Vcc and selectively provides the intermediate voltage to the gate G1 of the PMOS 101 by opening and closing the first switch 205. The power supply voltage level detector 301 detects the level of the power supply voltage Vcc and outputs the power supply voltage level detection signals vref1, vref2, and vref3. The power supply voltage dropping means 305 is connected to a power supply terminal for supplying a Vcc power supply voltage, and outputs a plurality of dropping voltages Vm1, Vm2, and Vm3 that are differently dropped from Vcc. The switching unit 303 is controlled by the output signals vref1, vref2, and vref3 of the power supply voltage level detecting means, and as the power supply voltage Vcc is larger, the dropping voltage dropped more from the power supply voltage Vcc is output terminal mout. To be printed).
    [30] 4 is a circuit diagram of a data output buffer according to an embodiment of the present invention. In FIG. 4, the vref signal is a signal generated by the power supply voltage level detection unit 301 of the intermediate voltage generation circuit 203 and represents the result of detecting the level of Vcc. In the present embodiment, the vref1 signal has a high level when Vcc is greater than 1.6V and has a low level when Vcc is less than 1.6V. The vref2 signal has a high level when Vcc is greater than 2.1V and has a low level when Vcc is below 2.1V. The vref3 signal has a high level when Vcc is greater than 2.6V and has a low level when Vcc is less than 2.6V.
    [31] For example, if Vcc is 1.6 V or less, (vref1, vref2, vref3) becomes (L, L, L), and the outputs of three NANDs 401, 403, 405 (vrefout1, vrefout2, vrefout3) are (H, H). , H). However, if Vcc is 1.6V to 2.1V, (vref1, vref2, vref3) becomes (H, L, L), so that only the output (vrefout1) of the NAND 401 becomes L and the outputs of the remaining NAND (403, 405) (vrefout2). , vrefout3) becomes (H, H). At this time, vrefout1 turns on the PMOS 407 so that the node n41 becomes 1.1V under the assumption that Vcc is 1.8V and Vtn is 0.7V, and this voltage level is input to the gate G1 of the PMOS transistor 101.
    [32] In addition, between Vcc of 2.1V and 2.6V, vref1 and vref2 become H, vref3 becomes L, and only vrefout2 becomes L so that PMOS 409 is turned on so that node n41 becomes 1.1V when Vcc is 2.5V. The remaining vrefout1 and 3 are set to H to turn off the PMOSs 407 and 411. Similarly, when Vcc is 2.6V or more, vrefout3 becomes L and the PMOS 411 is turned on, so that the node n41 becomes 0.9V when Vcc is 3.0V. Although only the intermediate voltage applied to the gate of the PMOS transistor 101 has been described so far, the overall operation of the circuit will be described with reference to the signal waveform diagram of FIG.
    [33] 5 is a circuit diagram of the Vcc level detecting means according to the present invention. The circuit shown in FIG. 5A outputs a high level as the output signal vref when the power supply voltage Vcc is greater than the reference voltage 2.6V, and outputs a low level as the output signal vref when the power supply voltage Vcc is below the reference voltage 2.6V. . The output signal vref of the circuit shown in FIG. 5A corresponds to vref3 of FIG. 4. The reference voltage is adjusted by changing the wirings of the PMOS transistors 501, 503, 505 and the NMOS transistors 507, 509, 511 little by little to adjust the relative sizes between the PMOS transistors and the NMOS transistors. 5B is a circuit configuration that replaces the dotted line portion of FIG. 5A when the reference voltage is 1.6V, and the output signal of this circuit corresponds to vref1 of FIG. 3. 5C shows a case where the reference voltage is 2.1V, and the output signal of this circuit corresponds to vref2 of FIG.
    [34] Referring to the specific operation of the circuit illustrated in FIG. 5A, first, the PMOS transistor 513 is turned on by input of the first control signal Peq, and the node n51 is turned on by the PMOS transistor 515 and the resistor 517. Takes a certain level of voltage. The voltage applied to the node n51 by the logic threshold voltage logic Vt formed by the PMOS transistors 501, 503, and 505 and the NMOS transistors 507, 509, and 511 is a high or low level voltage at the node n53. To take this. The voltage level applied to the node n53 is fixed to the NANDs 517 and 519 to generate a signal called a power supply voltage level detection signal vref.
    [35] 6 is a circuit diagram of a means for generating a control signal, which is located in the control unit 209 shown in FIG. The second control signal poe is input, and the third control signal poeb1 is mainly generated using the RC delay units 601 and 603.
    [36] First, when the second control signal poe is input, the nodes of the waveforms as shown in FIG. 6 are displayed at the nodes n61 and n62, respectively, and the NAND logic operation is performed at the NAND gate 605 for the two signals. As shown in FIG. 6, a short width pulse for detecting the end of the second control signal poe is shown in (n63). The signal appearing at the node n63 is used as an input to generate a third control signal poeb1 which slightly increases the signal appearing at the node n63 due to the delay operation at the RC delay unit 603.
    [37] 7 is a signal timing diagram of a data output buffer according to the present invention. The overall operation of the data output buffer according to the present embodiment will be described with reference to the circuit diagram of the entire data output buffer shown in FIG. For example, it is assumed that Vcc is 3.0V, Vtn and Vtp are 0.7V, and the high-level cell data is output twice.
    [38] First, at (t0 to t1), the peq signal goes to H and the output of the NOR gate 413 goes to L to open the PMOS 415, so that the voltage 0.9V of the node n41 is transmitted to the node n45. At this time, since the poe signal is L, the PMOS 417 and the NMOS 419 are turned off, so the node gd and the node n45 are isolated, and the charge of the node n45 goes to Vcc by the NMOS 421. The current path remains blocked. During this period, the node gd becomes H by the poe signal.
    [39] In the next (t1 to t2), the Peq signal becomes L, the output of the NOR gate 413 becomes H, the PMOS 415 is turned off, and the node n45 maintains 0.9V. As in (t0 to t1), the node gd and the node n45 are separated to maintain their previous state.
    [40] In the next (t2 to t3), the poe signal becomes H and the output of the inverter 423 becomes H, thereby turning on the NMOSs 425, 427, and 429, and opening the transfer gates 417 and 419 to the node gd. And node n45 are connected. Therefore, the nodes gd and n45 become GND by turning on the NMOSs 425, 427, and 429 attached to the node gd. Since the capacitance of node gd is less than the node capacitance of node n45, even if node gd was Vcc in the previous time interval, the amount of charge charged at that time is small, so GND via NMOS 425, 427, 429. Can quickly withdraw charge. The node n45 has a large capacitance, but since a small voltage of 0.9V has been applied, it is charged with a small amount of charge, so that it does not take much time to discharge through the transfer gates 417 and 419. Therefore, the node n45 is quickly made GND so that the large sized PMOS 101 can be driven quickly, thereby improving the speed. In addition, the PMOS 101 cannot drive up to Vcc due to the NMOS 421, and can only drive up to (Vcc-Vtn), so that the output voltage can be increased by adding a smaller PMOS 431 to the output dout. Raise up to Vcc.
    [41] In the next (t3 to t4), since the poe signal is disabled by L, in this period, the nodes gd and n45 are separated by the transmission gates 417 and 419, and the PMOS 415 is represented by H of poeb1. Turn on to charge node n45 to 0.9V. The node gd turns on the PMOS 433 by turning the poe signal to L and turns it to H.
    [42] In the next (t4 to t5), the node n45 is separated from the node n41 as poeb1 becomes L, and the remaining node gd maintains the previous state. The period after the next t5 is the same as described above.
    [43] The description so far is directed to embodiments embodying the present invention, and is not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes to the configurations described in connection with the embodiments can be made within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.
    [44] According to the present invention as described above, when outputting high-level cell data, a voltage lower than Vcc / 2 is applied to the gate of the PMOS transistor having a large size before outputting the data. Conventionally, the gate voltage of the PMOS transistor varies from Vcc to GND. However, according to the present invention, the speed of turning on the PMOS transistor is improved since the voltage varies from Gcc to GND at a voltage lower than Vcc. When a high level data is output even at a high level Vcc or a low level Vcc, a voltage lower than Vcc / 2 is applied to the gate of the PMOS transistor before data output, thereby enabling high-speed operation even in a wide range of Vcc.
    权利要求:
    Claims (11)
    [1" claim-type="Currently amended] In the data output buffer,
    A gate driving voltage generated by the input data is selectively applied to the gate, a drain is selectively connected to a power supply terminal, and a source is connected to an output terminal of the data output buffer;
    An intermediate voltage generator for generating an intermediate voltage of the power voltage applied from the power terminal;
    A first switch for selectively applying the intermediate voltage to a gate of the first PMOS transistor;
    A second switch for selectively applying the gate driving voltage to a gate of the first PMOS transistor;
    A controller configured to control the first switch to apply the intermediate voltage to the gate of the first PMOS transistor, and then control the second switch to apply the gate driving voltage to the gate of the first PMOS transistor
    And a data output buffer.
    [2" claim-type="Currently amended] The method of claim 1,
    Before the gate driving voltage is applied to the first PMOS transistor, the drain and the power terminal of the first PMOS transistor are disconnected. When the gate driving voltage is applied to the first PMOS transistor, And a third switch for connecting the power terminal.
    [3" claim-type="Currently amended] The method of claim 1,
    The gate driving voltage is applied to a gate, a drain is connected to the power supply terminal, a source is connected to an output terminal of the data output buffer, and a second PMOS transistor having a smaller size than the first PMOS transistor is further added. And a data output buffer.
    [4" claim-type="Currently amended] The method of claim 1,
    The intermediate voltage generator
    Means for detecting a level of the power supply voltage;
    A power supply voltage dropping means connected to the power supply terminal and outputting a plurality of dropping voltages differently dropped from the power supply voltage;
    A switching means controlled by an output signal of the power supply voltage level detecting means and providing a dropping voltage lowered from the power supply voltage to the output terminal of the intermediate voltage generator from the power supply voltage dropping means as the power supply voltage is larger;
    And a data output buffer.
    [5" claim-type="Currently amended] The method of claim 1,
    And said second switch comprises a transmission gate.
    [6" claim-type="Currently amended] In the data output buffer,
    A gate driving voltage generated by the input data is selectively applied to the gate, a drain is selectively connected to a power supply terminal, and a source is connected to an output terminal of the data output buffer;
    An intermediate voltage generator for generating an intermediate voltage in which a voltage having a predetermined magnitude is dropped from the power supply voltage according to the level of the power supply voltage applied from the power supply terminal;
    A first switch for selectively applying the intermediate voltage to a gate of the first PMOS transistor;
    A second switch for selectively applying the gate driving voltage to a gate of the first PMOS transistor;
    A controller configured to control the first switch to apply the intermediate voltage to the gate of the first PMOS transistor, and then control the second switch to apply the gate driving voltage to the gate of the first PMOS transistor;
    Before the gate driving voltage is applied to the first PMOS transistor, the drain and the power terminal of the first PMOS transistor are disconnected. When the gate driving voltage is applied to the first PMOS transistor, A third switch connecting the power terminal;
    The gate driving voltage is applied to a gate, a drain is connected to the power supply terminal, a source is connected to an output terminal of the data output buffer, and a second PMOS transistor having a smaller size than that of the first PMOS transistor.
    And a data output buffer.
    [7" claim-type="Currently amended] The method of claim 6,
    The intermediate voltage generator
    Means for detecting a level of the power supply voltage;
    A power supply voltage dropping means connected to the power supply terminal and outputting a plurality of dropping voltages differently dropped from the power supply voltage;
    A switching means controlled by an output signal of the power supply voltage level detecting means and providing a dropping voltage lowered from the power supply voltage to the output terminal of the intermediate voltage generator from the power supply voltage dropping means as the power supply voltage is larger;
    And a data output buffer.
    [8" claim-type="Currently amended] In a semiconductor memory device,
    A memory unit for storing data,
    A data output buffer for outputting data stored in the memory unit;
    Equipped,
    The data output buffer
    A gate driving voltage generated by data input from the memory unit is applied to the gate, a drain is selectively connected to a power supply terminal, and a source is connected to an output terminal of the data output buffer;
    An intermediate voltage generator for generating an intermediate voltage in which a voltage having a predetermined magnitude is dropped from the power supply voltage according to the level of the power supply voltage;
    A first switch for selectively applying the intermediate voltage to a gate of the first PMOS transistor;
    A second switch for selectively applying the gate driving voltage to a gate of the first PMOS transistor;
    A controller configured to control the first switch to apply the intermediate voltage to the gate of the first PMOS transistor, and then control the second switch to apply the gate driving voltage to the gate of the first PMOS transistor;
    Before the gate driving voltage is applied to the first PMOS transistor, the drain and the power terminal of the first PMOS transistor are disconnected. When the gate driving voltage is applied to the first PMOS transistor, A third switch connecting the power terminal;
    The gate driving voltage is applied to a gate, a drain is connected to the power supply terminal, a source is connected to an output terminal of the data output buffer, and a second PMOS transistor having a smaller size than that of the first PMOS transistor.
    Semiconductor memory device comprising a.
    [9" claim-type="Currently amended] A method of driving a data output buffer comprising a PMOS transistor, wherein a gate driving voltage generated by input data is selectively applied to a gate, a drain is selectively connected to a power supply terminal, and a source is connected to an output terminal.
    Generating an intermediate voltage of a power supply voltage applied from the power supply terminal to the gate of the PMOS transistor while preventing the gate driving voltage from being applied to the gate of the PMOS transistor;
    Allowing the gate driving voltage to be applied to the gate of the PMOS transistor while the intermediate voltage is not applied to the gate of the PMOS transistor.
    And a data output buffer driving method.
    [10" claim-type="Currently amended] The method of claim 9,
    Before the gate driving voltage is applied to the gate of the PMOS transistor, the drain and the power terminal of the PMOS transistor are disconnected. When the gate driving voltage is applied to the PMOS transistor, the drain of the PMOS transistor and the power terminal are connected. And a step of driving the data output buffer.
    [11" claim-type="Currently amended] The method of claim 9,
    Generating the intermediate voltage
    Generating a level control signal by detecting a level of the power supply voltage;
    Outputting a plurality of dropping voltages differently dropped from the power supply voltage;
    According to the level control signal, the process of outputting a dropping voltage lowered more from the power supply voltage as the power supply voltage increases
    And a data output buffer driving method.
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    同族专利:
    公开号 | 公开日
    KR100412134B1|2003-12-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-06-27|Application filed by 주식회사 하이닉스반도체
    2001-06-27|Priority to KR10-2001-0036999A
    2003-01-06|Publication of KR20030000845A
    2003-12-31|Application granted
    2003-12-31|Publication of KR100412134B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-2001-0036999A|KR100412134B1|2001-06-27|2001-06-27|A data output buffer operating on wide source voltage and a semiconductor memory device using this buffer|
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