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    • 专利摘要:
    PURPOSE: To provide a switching power supply unit, capable of preventing production of magnetic strain noise generated from a transformer. CONSTITUTION: The number of times of ringing bottom is counted by LATCHs1 to 5, and the counted number of times of bottom in ringing is stored in FFs1 to 4. The number of times of bottom in ringing stored in the FFs1 to 4 and the number of times of bottom in the present ringing counted by the LATCHs1 to 5 are compared with each other by EXNORs1 to 4 and AND1, to see whether they match each other. The off-period of a switching element Q1 is maintained, until the number of times of bottom in ringing stored in the FFs1 to 4 matches the number of times of bottom in the present ringing.
    公开号:KR20020095005A
    申请号:KR1020010077389
    申请日:2001-12-07
    公开日:2002-12-20
    发明作者:츠게마코토
    申请人:산켄덴키 가부시키가이샤；
    IPC主号:
    专利说明:

    Switching Power Supply {SWITCHING POWER SUPPLY DEVICE}
    [13] The present invention relates to a switching power supply that can set the number of rings generated in the OFF period of the switching element to a certain number in order to prevent the generation of magneto striction noise in the transformer.
    [14] 4 is a diagram illustrating an example of a circuit configuration of a conventional switching power supply.
    [15] In Fig. 4, the rectifying smoothing circuit 11 inputs an alternating current (AC) supply voltage, for example, full-wave rectifies it through a diode bridge, smoothes it through a capacitor, and finally, converts the obtained direct current (DC) voltage into a transformer. Output to one end of primary winding L1 of (13).
    [16] The other end of the primary winding L1 of the transformer 13 is connected to the drain of the switching element Q1. The source of the switching element Q1 is connected to the ground which is also connected to the ground portion of the rectification smoothing circuit 11. The capacitor C1 is connected in parallel between the source and the drain of the switching element Q1.
    [17] The magnetic energy accumulated in the primary winding L1 of the transformer 13 is sequentially induced in the secondary winding by the switching operation of the switching element Q1 controlled by the ON-OFF operation of the controller 25 described later. . Half-wave rectification is then performed on the magnetic energy induced in the secondary winding by a diode D1 connected to one end of the secondary winding L2, smoothed by the capacitor C3, and then smoothed DC voltage. This is output to the load 17 and to the output DC voltage detection circuit 19.
    [18] The output DC voltage detection circuit 19 converts the output DC voltage supplied to the load 17 into a feedback signal and outputs it to the ON period control circuit 29 mounted in the controller 25.
    [19] The diode D3 of the output smoothing circuit 21 is half-wave rectified with respect to the flyback voltage generated in the auxiliary winding L3 of the transformer 13 and the capacitor C5 smoothes the voltage obtained from the diode D3. Let's do it. The control unit 25 inputs the smoothed voltage Vcc from the capacitor C5.
    [20] When the starting voltage of the predetermined voltage or more is supplied to the starting resistor R1, the control unit 25 starts oscillation.
    [21] When the switching element Q1 is OFF, ringing occurs in the primary winding L1 of the transformer 13. The resonance frequency f is as follows.
    [22]
    [23] At the same timing, ringing also occurs in the auxiliary winding L3.
    [24] In the ring generating circuit 23, ringing is divided by the resistors R3 and R5 after detection through the diode D5. The ringing signal from which the high frequency component is removed through the resistor R3 and the capacitor C7 is output to the comparator circuit 27 mounted on the controller 25.
    [25] The comparator circuit 27 compares the ringing signal input to the comparator COMP1 with the reference voltage Vref1, and outputs a high level signal when the ringing signal is greater than the reference voltage Vref1.
    [26] The ON period control circuit 29 generates an ON period control signal for stabilizing the output DC voltage supplied to the load 17 by adjusting the ON period by a feedback signal from the output DC voltage detection circuit 19 to generate a frequency control circuit. Output what was generated by (31).
    [27] The frequency control circuit 31 controls the ON period by the ON period control signal from the ON period control circuit 29, for example, oscillates a fixed frequency defined by the time constant of the capacitor and the resistor, thereby driving the drive circuit ( 33) to output the control signal.
    [28] In the inverter INV1 of the driving circuit 33, both the control signal V3 from the comparator circuit 27 and the control signal V18 from the frequency control signal 31 for one end of the OR gate OR1 are simultaneously low. When the level is reached, the high level drive signal V119 is output to the switching element Q1.
    [29] Next, the basic operation of the conventional switching power supply will be described with reference to the timing chart shown in FIG.
    [30] (1) When the AV voltage is supplied to the rectification smoothing circuit 11, the control signal V18 is generated at the timing t0 when the starting voltage of the predetermined voltage or more is supplied to the terminal Vcc through the starting resistor R1. It is output to the OR gate OR1. At this time, since the voltage V2 is not generated in the auxiliary winding L3 of the transformer 13, the comparator circuit 27 outputs the low level control signal V3.
    [31] As a result, when the gate of the switching element Q1 inputs the high level drive signal V19 from the inverter INV1, the switching element Q1 starts the ON state, and the direct current of the rectifying smoothing circuit 11 It flows from the terminal 11c through the primary winding L1 of the transformer 13 to the ground GND and the drain and source of the switching element Q1. During this time, magnetic energy is accumulated in the transformer 13.
    [32] (2) At the timing t1, the frequency control circuit 31 outputs the high level control signal V18 to the OR gate OR1.
    [33] As a result, the high level drive signal V19 from the inverter INV1 is switched to the low level, and the low level drive signal V19 is sent to the gate of the switching element Q1. As a result, the switching element Q1 is turned off and magnetic energy accumulated in the transformer 13 is induced in the second winding L2 and the auxiliary winding L3.
    [34] (3) At timings t1 to t2, electrical energy emitted through the second winding L2 of the transformer 13 is rectified by the diode D1 and smoothed by the capacitor C3. The rectified and smoothed output voltage is then supplied to the load.
    [35] At this time, the voltage V2 is generated in the auxiliary winding L3 of the transformer 13. Since the input voltage level of the comparator 27 is equal to or higher than the reference voltage Vref1, the comparator 27 outputs the high level output voltage V3.
    [36] (4) Just before timing t2, the level of the input voltage in the comparator 27 is gradually decreasing. As shown in FIG. 5, the voltage V2 of the auxiliary winding L3 reaches a bottom level B at timing t3 and then increases after timing t3 to be increased at timing t4. The high level is reached and reduced again after timing t4. This phenomenon is called "ringing." In addition, the same ringing occurs at the voltage V1 of the primary winding L1.
    [37] (5) At the timings t4 to t5, the ringing phenomenon described in (4) occurs once. Since the conventional switching power supply operates at a fixed frequency, the low level control signal V18 is sent to the OR gate OR1 at timing t5.
    [38] At this time, when the level of the voltage V2 is reduced by the ringing phenomenon caused by the auxiliary winding L3 of the transformer 13 and the level of the output voltage V3 of the comparator circuit 27 becomes a low level, Since the signals V18 and V3 of the level are input to both input terminals of the OR gate OR1, the gate of the switching element Q1 inputs the high level drive signal V19 from the inverter INV1. As a result, the switching element Q1 is turned on.
    [39] As described above, in the conventional switching power supply device, the control voltage V2 caused by the ringing phenomenon of the auxiliary winding L3 of the transformer 13 is turned off near the bottom level which becomes equal to or less than the reference voltage Vref1. .
    [40] As described above, since the conventional switching power supply operates at a fixed oscillation frequency, when the voltage V2 caused by the ringing phenomenon is near the bottom level at which the reference voltage Vref1 is less than or equal to the switching element Q1. Is OFF.
    [41] By the way, when the control signal V3 supplied from the comparator circuit 27 to the OR gate OR1 from the comparator circuit 27 and the control signal V18 from the frequency control circuit 31 are simultaneously at the low level. Inverter INV1 outputs high level drive signal V19 to switching element Q1. Therefore, when the timing at which one of the control signal V3 from the comparator circuit 27 and the control signal V18 from the frequency control circuit 31 becomes a low level is delayed, the timing at which the switching element Q1 is turned ON. Is delayed from the timing defined by the fixed oscillation frequency.
    [42] As a result, the following two cases occur: The number of times of ringing occurs N times and N + 1 times during the OFF period of the switching element Q1 under the condition of the same load and the same input voltage.
    [43] There is a problem in that the OFF period of the switching element Q1 varies by one ringing period, and a magnetic distortion sound is generated in the transformer by the variation of the OFF period.
    [44] Accordingly, an object of the present invention is to provide a switching power supply device capable of preventing the magnetic distortion sound in a transformer in view of the problems of the prior art.
    [45] Briefly, the present invention can be summarized as a switching power supply capable of preventing the generation of magnetic distortion sounds. The switching power supply includes a switching element connected in series to a primary winding of a transformer connected to a direct current (DC) power supply, and a rectification for rectifying and smoothing an alternating current (AC) voltage induced in a secondary winding of the transformer. An output voltage detection circuit for detecting an output voltage rectified and smoothed by the rectification smoothing circuit and outputting a voltage detection signal to a primary circuit of the transformer, based on a voltage detection signal from the output voltage detection circuit A control circuit for controlling the ON period of the switching element to stabilize the output voltage, and a bottom of the ringing at the same timing as the occurrence of the ringing between the capacitor and the transformer connected in parallel to the switching element during the OFF period of the switching element. A bottom detecting circuit for detecting. In the switching power supply of the present invention, a bottom number counting circuit for counting the number of occurrences of the bottom of the ringing detected by the bottom detecting circuit as the bottom count, and storing the bottom count counted by the bottom counting circuit A bottom count memory circuit for comparing the bottom count memory stored in the bottom count memory circuit with a bottom count comparison circuit for comparing whether the bottom count memory is equal to the current bottom count, and a bottom count comparison circuit according to a comparison result of the bottom count comparison circuit. And an OFF period control circuit for maintaining the OFF period of the switching element until the bottom number stored in the number memory circuit is reached.
    [46] According to the present invention, the switching power supply further includes a reset circuit for resetting the number of times stored in the bottom number memory circuit.
    [47] In the above-described switching power supply device, the reset circuit resets the number of bottoms stored in the bottom number memory circuit when the bottom number of rings counted by the bottom number counting circuit tends to increase or decrease.
    [48] From the following description and the appended claims, with reference to the accompanying drawings showing preferred embodiments of the invention, the above and other features and advantages of the present invention, and the manner of realizing them, become more apparent, and the invention itself It will be well understood.
    [1] 1 is a diagram showing the configuration of a switching power supply apparatus according to a first embodiment of the present invention;
    [2] Fig. 2 is a diagram showing the detailed configuration of the control unit 51 of the switching power supply device of the first embodiment of the present invention.
    [3] 3 is a timing chart showing the operation of the switching power supply apparatus according to the first embodiment of the present invention;
    [4] 4 is a diagram showing a circuit configuration of a conventional switching power supply;
    [5] 5 is a timing chart showing the operation of the conventional switching power supply.
    [6] <Explanation of symbols for main parts of drawing>
    [7] 11: rectifier smoothing circuit 13: transformer
    [8] 23: ringing circuit 27: comparator circuit
    [9] 51 control unit 53 OFF period control circuit
    [10] 55: bottom counter circuit 57: bottom count memory circuit
    [11] 59: bottom count comparison circuit 61: bottom count reset circuit
    [12] 63: driving circuit Q1: switching element
    [49] Other features of the present invention will become apparent from the following description of the preferred embodiments given by way of illustration of the invention and are not intended to be limiting.
    [50] First embodiment
    [51] 1 is a diagram showing the configuration of a switching power supply apparatus according to a first embodiment of the present invention. The switching power supply of the first embodiment according to the present invention basically has the same configuration as the conventional one shown in FIG. Therefore, the same components are denoted by the same reference numerals and characters, and description thereof is omitted here for brevity.
    [52] The switching power supply of the first embodiment is characterized by the OFF period control circuit 53, the bottom count counter circuit 55, the bottom count memory circuit 57, the bottom count comparison circuit 59, and the bottom count reset circuit 61. ) And a control unit 51 including a driving circuit 63. The OFF period control circuit 53 controls the OFF period of the switching element Q1 based on the PMW control. The bottom count counter circuit 55 counts the number of times the bottom of the ringing signal is generated, that is, the number of bottoms generated by the comparator circuit 27. The bottom count memory circuit 57 stores the number of times of occurrence of the bottom of the ringing signal counted by the bottom count counter circuit 55 (that is, the bottom count). The bottom count comparison circuit 59 compares the number of occurrences of the bottom of the ringing signal counted by the bottom count counter circuit 55 with the bottom count stored in the bottom count memory circuit 57. The bottom count reset circuit 61 resets the bottom count stored in the bottom count memory circuit 57. The drive circuit 63 drives the switching element Q1.
    [53] FIG. 2 is a diagram showing a detailed configuration of the control unit 51 of the switching power supply of the first embodiment of the present invention.
    [54] The ON period control circuit 29 that receives the feedback signal sent out from the output DC voltage detection circuit 19 stabilizes the output voltage of the secondary winding of the transformer 13 by adjusting the ON period of the switching element Q1.
    [55] The OFF period control circuit 53 generates a pulse signal after a fixed time counting from the start of the ON state of the switching element Q1 (rising edge of the control signal V19) has elapsed. Further, the OFF period control circuit 53 generates the control signals V24 and V25, the falling edge of the control signal V18, and the pulse signal (the bottom of the ring signal after the falling edge of the control signal V18). Required when the number of times changes from two to one).
    [56] The control signal supplied from the ON period control circuit 29 to the OFF period control circuit 53 is a signal for setting the switching element Q1 to the OFF state (ON state stop). The OFF-period control circuit 53 generates the control signal V24 during the period from the generation of the pulse signal of the control signal V25 to the falling edge of the control signal V18, and generates the bottom-count reset circuit 61. The output control signal V24.
    [57] The bottom counter counter 55 is composed of latch circuits LATCH1 to LATCH5 and inputs the falling edge of the ringing signal V3 generated by the comparator circuit 27 as a clock signal and clears the control signal V27 with a clear signal and Input as both data signals. The latch circuits LATCH1 to LATCH5 are cleared when receiving the low level control signal V27 transmitted from the OR gate OR3, and the latch circuits LATCH1 to LATCH5 of the bottom signal B of the ringing signal when the high level control signal V27 is received. Count the number of occurrences.
    [58] The bottom count memory circuit 57 includes the RS flip-flops indicated by the reference numerals FF1 to FF4 and receives the corresponding high level control signals V5 to V8 transmitted from the latch circuits LATCH1 to LATCH5, respectively, to receive the FF1 to FF4. Is set to a high level to store the number of occurrences of the bottom of the ringing signal. Further, the information, that is, the number of bottoms stored in the bottom number memory circuit 57 can be reset by receiving the reset signals V20 to V23 supplied from the bottom number reset circuit 61.
    [59] The bottom count comparison circuit 59 includes EXNOR gates EXNOR1 to EXNOR4 and an AND gate AND1. The bottom count comparison circuit 59 compares the previous bottom count with the current bottom count, that is, the number of occurrences of the bottom of the ringing signal generated in the last OFF period and stored in the flip-flops FF1 to FF4. Is compared with the control signals V5 to V8 indicating the number of occurrences of the bottom counted by the latch circuits LATCH2 to LATCH5 during this OFF period.
    [60] When both bottom counts match, the AND gate AND1 of the bottom count comparison circuit 59 receives the high level control signal V17 indicating that the current bottom count has reached the previous bottom count, respectively. To the reset terminal of FF4).
    [61] The flip-flop FF5 is set by receiving the control signal V25 indicative of the start of the OFF period maintenance sent from the OFF period control circuit 53, and the number of times this time, sent out from the AND gate AND1, is the last time. It is reset by receiving the control signal V17 indicating that the bottom number has been reached.
    [62] The bottom number reset circuit 61 is based on the control signals V4 to V7 sent from the latch circuits LATCH1 to LATCH4 and the control signals V24 sent from the OFF period control circuit 53 to flip the flip flops FF1 to FF1 to the bottom count reset circuit 61. Reset signals V20 to V23 are generated to reset the corresponding bit representing the number of bottoms stored in FF4. That is, the OFF period control circuit 53 generates the control signal V24 during the period from the pulse signal of the generated control signal V25 to the falling edge of the control signal V18. When the bottom count reset circuit 61 generates the control signal V24 when the at least one control signal V4 to V7 transmitted from the latch circuits LATCH1 to LATCH4 is at a low level when the control signal V24 is generated. Since at least one control signal V4 to V7 corresponding to the bottom of the ringing signal cannot be received, a reset pulse control signal V22 is generated. As a result, the switching element Q1 can be set to the ON state when the number of occurrences of the bottom of the ringing signal is three instead of four.
    [63] The driving circuit 63 includes an OR gate OR3 and an inverter INV1. The OR gate OR3 outputs a low level reset signal to the latch circuits LATCH1 to LATCH5 during the timing at which the next condition occurs simultaneously, and the inverter INV1 outputs the drive signal V19 to the switching element Q1.
    [64] When the comparator circuit 27 generates and outputs a low level control signal V3;
    [65] When the OFF period control circuit 53 outputs a low level control signal V18; And
    [66] When the flip-flop FF5 outputs the low level reset signal V27.
    [67] Next, the operation of the switching power supply will be described with reference to FIG. 2 showing the detailed configuration of the controller 51 and FIG. 3 showing the timing chart of the main part of the controller 51. FIG.
    [68] (1) Operation example of the switching power supply device during the timings t0 to t3.
    [69] At the timing t0 shown in Fig. 3, the inverter INV1 of the drive circuit 63 outputs a high level drive signal V19, whereby the switching element Q1 is turned on. As a result, the high level drive signal V19 transmitted from the inverter INV1 sets the switching element Q1 to the ON state, and the DC current is applied to the transformer 13 at the terminal 11c of the rectification smoothing circuit 11. Through the primary winding (L1) of the ground (GND) and the drain-source of the switching element (Q1). Magnetic energy is accumulated in the transformer 13 during the timings t0 to t1.
    [70] Here, upon receiving the feedback signal from the output DC voltage detection circuit 19, the ON period control circuit 29 generates the ON period control signal for stabilizing the output DC voltage supplied to the load 17. After adjusting the length of the ON period, the ON period control signal generated by the OFF period control circuit 53 is output. When receiving the ON period control signal sent from the ON period control circuit 29, the OFF period control circuit 53 generates a high level control signal V18 and outputs the generated one to the OR gate OR3. . As a result, the ON period of the switching element Q1 ends at the timing t1.
    [71] During the timings t1 to t2, the electrical energy released through the secondary winding L2 of the transformer 13 is rectified and smoothed by the diode D1 and the capacitor C3, whereby the output voltage is reduced. Supplied to the load.
    [72] At this time, the voltage V2 is generated in the auxiliary winding L3 of the transformer 13. Since the voltage V2 exceeds the reference voltage Vref1, that is, since the comparator circuit 27 inputs a control signal of this voltage V2, the comparator circuit 27 is a high level control signal V3. Outputs
    [73] During the timings t1 to t6 after the timings t1 to t2, the OFF period of the switching element Q1 is driven based on the control signal V18 generated by the OFF period control circuit 53. It is held by receiving the control signal V19 from 63.
    [74] The level of the control signal V2 sent out from the ring generation circuit 23, that is, the level of the input voltage V2 supplied to the comparator circuit 27 is gradually decreased immediately after the timing t2. In this case, the level of the voltage in the auxiliary winding L3 reaches the level of the bottom (indicated by reference numeral “B”, see FIG. 3), then increases to the peak level after the bottom level B, and then decreases as well. Repeating ringing occurs. It can be observed that the same ringing occurs at the voltage V1 generated in the primary winding.
    [75] The comparator circuit 27 then inputs a control signal V2 and a reference voltage V28. At the timing t6, this control signal V2 is generated by the ring generation circuit 23 at the same timing and is supplied to the control signal V1 supplied to the switching element Q1 in the OFF state. By this, the switching element Q1 can be kept in the OFF state during the timings t6 to t7, that is, the switching element Q1 can be kept in the OFF state during the timings t1 to t7.
    [76] In the OFF period during the timings t1 to t7, the OR gate OR3 of the drive circuit 63 inputs the control signal V3 generated by the comparator circuit 27 and the control signal V27 to the latch circuit LATCH1. And the latch circuits LATCH1 to LATCH5 input the control signal V3 from the comparator circuit 27. As a result, the latch circuits LATCH1 to LATCH5 generate and output the control signals V4 to V8, respectively.
    [77] That is, the latch circuits LATCH1 to LATCH5 count the number of falling edges of the control signal V3 during the timings t1 to t7. Details are as follows: As shown in Fig. 3, the high level control signals V4, V5, V6, and V7 are counted at timings t2, t3, t4, and t7, respectively. The flip-flops FF1 to FF4 also input the control signals V5 to V8 as the control signals V9 to V12 indicating the number of occurrences of the bottom of the ringing signal generated during the last OFF period.
    [78] Here, the EXNOR gate EXNOR1 compares the control signal V5 with the control signal V9, the EXNOR gate EXNOR2 compares the control signal V6 with the control signal V10, and the EXNOR gate EXNOR3 The control signal V7 is compared with the control signal V11, and the EXNOR gate EXNOR4 compares the control signal V8 with the control signal V12. These output the comparison results V13 to V16 to the AND gate AND1.
    [79] During the timings t1 to t7, the EXNOR gates EXNOR1 to EXNOR4 input control signals V5 and V9, V6 and V10, V7 and V11, and V8 and V12 of the same level, respectively. That is, since all input terminals of the AND gate AND1 input the high level control signal, the AND gate AND1 outputs the high level control signal V17. As a result, during the timings t1 to t7, the flip-flop FF5 inputs the low level control signal V26 because the flip-flop FF5 inputs the reset signal at the highest priority during operation.
    [80] At the timing t5 at which the OFF period control circuit 53 outputs the high level control signal V18, the OFF period control circuit 53 starts a control signal (starting the maintenance of the OFF period of the switching element Q1). Outputs V25) to the setting (S) terminal of the flip-flop (FF5).
    [81] Since the OR gate OR3 inputs the low-level control signals V26, V18, and V3 simultaneously at the timing t7, the switching element Q1 is turned on. At this time, since the clear terminal CLR of each latch circuit LATCH1 to LATCH5 inputs the control signal V27 transmitted from the OR gate OR3, the control signals V4 to V8 are cleared, that is, high level. To low level.
    [82] In the same manner as described above, the ON period of the switching element Q1 is terminated by the ON period control circuit 29 at the timing t8 and the control signal V18 sent from the OFF period control circuit 53 is at a high level. Thus, the OFF period of the switching element Q1 is maintained during the timings t8 to t12.
    [83] During the timings t8 to t12, the latch circuits LATCH1 to LATCH5 count the number of falling edges of the control signal V3 generated by the comparator circuit 27 and output the control signals V4 to V8.
    [84] At the timing t11, since the terminal S of the flip-flop 55 inputs the high level control signal V25 indicating the start of the OFF period sent from the OFF period control circuit 53, the flip-flop ( The Q output from FF5) transitions from low level to high level.
    [85] At this time, since the level of the control signal V7 is different from the control signal V11, the EXNOR gate EXNOR3 outputs the control signal V15 to the AND gate AND1, and the control signal from the AND gate AND1. The level of V17 is switched to the low level. Therefore, the switching element Q1 is kept in the OFF state after the timing t12. In contrast, the switching element Q1 of the conventional switching power supply shown in FIG. 4 is turned on at the timing t12.
    [86] At the timing t13, both control signals V7 and V11 become the same level at the same time by the falling edge of the control signal V3 generated by the comparator circuit 27, and this time the number of bottoms is AND gate AND1. The control signal V17 indicating that the previous number of bottoms outputted from the display reaches the high level, and the Q output (that is, the control signal V26) of the flip-flop FF5 is switched from the high level to the low level.
    [87] That is, the AND gate AND1 counts the number of bottoms of the ringing generated during the previous OFF period stored in the flip-flops FF1 to FF4 by the latch circuits LATCH1 to LATCH4. By matching with, the high level control signal V17 indicating that the current bottom number has reached the previous bottom number is output to the reset terminal of the flip-flop FF5.
    [88] The OFF period control circuit 53 generates the pulse signal of the control signal V24 during the period from the pulse signal of the generated control signal V25 to the falling edge of the control signal V18, and resets the bottom count signal 61. Is reset when the control signal V24 is generated, for example, when the control signal V24 is generated when the control signal V5 from the latch circuit LATCH2 is at a high level. The pulse control signal V22 is not generated. As a result, the switching element Q1 can be set to the ON state at the time of generation of the fourth bottom as in the last time when the fourth generation of the bottom sets the switching element Q1 to the ON state.
    [89] At the timing t13, the switching element Q1 is turned on by this. Thereafter, the same operation is performed during the timings t13 to t22.
    [90] As such, the latch circuits LATCH1 to LATCH5 count the number of bottoms of the ringing, the flip-flops FF1 to FF4 store the counted number of bottoms of the ringing, and the EXNOR gates EXNOR1 to EXNOR4 and the AND gate AND1 The number of previous bottoms stored in the flip-flops FF1 to FF4 is compared with the number of bottoms counted by the latch circuits LATCH1 to LATCH5, and the OFF period of the switching element Q1 is maintained until both bottoms coincide. do. As a result, the number of times of ringing can be set to the same number of times. This can prevent the generation of magnetic distortion sounds in the transformer.
    [91] As a result, even when the same load and the same input voltage are used, the number of occurrences of the ringing can be set to the same number of times, and when the number of occurrences of the ringing is changed, for example, N times and N + 1 times as in the prior art. Can be eliminated, and the occurrence of changing the time length of the generated OFF period of the switching element Q1 by one ringing period can be eliminated. Thereby, the fault which produces the magnetic distortion sound in a conventional transformer can be eliminated.
    [92] (2) Operation example of the switching power supply device during the timings t17 to t18
    [93] Next, the bottom number reset circuit 61 flips the high level control signal V22 based on the control signal V24 from the OFF period control circuit 53 and the Q output from the latch circuits LATCH1 to LATCH4. It does not output to the reset terminal R of the flop FF3. As a result, the flip-flop FF3 outputs a high level Q output.
    [94] That is, the OFF-period control circuit 53 generates the pulse signal of the control signal V24 during the reception of the generated control signal V25 to the falling edge of the control signal V18, and resets the bottom number of times. Since the second bottom occurs when the control signal V24 is generated when the control signal V5 from the latch circuit LATCH2 is at the high level when the control signal V24 is generated, the reset pulse of the control signal V21 is generated. Does not generate As a result, it is possible for the switching element Q1 to start the ON state at the time of generation of the ringing signal of the fourth bottom as in the previous time when the switching element Q1 is turned on by the generation of the ringing signal of the fourth bottom.
    [95] At the timing t19, the control signals V5 and V9 supplied to the EXNOR gate EXNOR1, the control signals V6 and V10 supplied to the EXNOR gate EXNOR2, and the control signals supplied to the EXNOR gate EXNOR3 ( V7 and V11 and the control signals V8 and V12 supplied to the EXNOR gate EXNOR4 are at the same level, and the AND gate AND1 controls the high level indicating that the number of bottoms has reached the previous number of bottoms. The signal V17 is output to the reset terminal R of the flip-flop FF5, and the flip-flop FF5 outputs a low-level Q output, whereby the switching element is turned on.
    [96] (3) Operation example of switching element Q1 during timings t23 to t27
    [97] Next, at timing t23, the bottom count reset circuit 61 is at a high level based on the control signal V24 from the OFF period control circuit 53 and the Q output from the latch circuits LATCH1 to LATCH4. Control signal V22 is outputted to the reset terminal R of the flip-flop FF3, whereby the flip-flop FF3 outputs a low level Q output.
    [98] That is, the OFF-period control circuit 53 generates the control signal V24 during the period from the generation of the control signal V25 to the falling edge of the control signal V18, and the bottom-count reset circuit 61 controls. When the control signal V5 from the latch circuit LATCH2 is at the low level when the signal V24 is generated, the second bottom does not occur when the control signal V24 is generated, thereby generating the reset pulse control signal V22. . As a result, the switching element Q1 starts the ON state by receiving the ringing signal of the fourth bottom at the previous time, whereas the switching element Q1 can be turned ON by receiving the ringing signal of the third bottom. .
    [99] At the timing t27, the control signals V5 and V9 supplied to the EXNOR gate EXNOR1, the control signals V6 and V10 supplied to the EXNOR gate EXNOR2, and the control signals supplied to the EXNOR gate EXNOR3 ( Since V7 and V11 and the control signals V8 and V12 supplied to the EXNOR gate EXNOR4 are at the same level, the AND gate AND1 has a high level indicating that the number of bottoms has reached the previous number of bottoms. The control signal V17 is outputted to the reset terminal R of the flip-flop FF5, and the flip-flop FF5 outputs a low level Q output, whereby the switching element is turned on.
    [100] (4) Operation example of switching power supply during other timing
    [101] The bottom frequency reset circuit 61 outputs the reset pulse signal V21 when the control signal V6 is at the low level when the control signal V24 is generated. This causes the switching element to start the ON state upon the reception of the third bottom last time, while setting the switching element Q1 to the ON state by receiving the ringing signal of the second bottom.
    [102] In addition, the bottom number reset circuit 61 generates the reset pulse control signal V23 when the control signal V6 becomes low when the control signal V24 is generated. This causes the switching element to start the ON state upon reception of the last fifth bottom, whereas setting the switching element Q1 to the ON state by receiving the ringing signal of the fourth bottom.
    [103] Further, the bottom number reset circuit 61 generates the control signal V24 (reference pulse signal) after receiving the falling edge of the control signal V18, and when the control signal V24 is generated, the control signal V4 is generated. When the low level is reached, the reset pulse signal V20 is output. This causes the switching element to start the ON state upon the reception of the second bottom last time, while setting the switching element Q1 to the ON state by receiving the ringing signal of the first bottom.
    [104] For example, when starting the ON state by receiving the fourth bottom according to the input / output condition of the switching power supply, the switching element Q1 receives the ringing signal of the second bottom instead of the third bottom. The ON state may be started.
    [105] As in the foregoing (2) to (4) methods, the OFF period control circuit 53 generates the control signal V24 during the reception of the control signal V25 to the falling edge of the control signal V18, and the bottom count The reset circuit 61 generates a second bottom ringing signal when the control signal V24 is generated when the control signal V5 from the latch circuit LATCH2 is at a low level when the control signal V24 is generated. The reset pulse signal V2 is generated.
    [106] As a result, although the switching element Q1 was turned ON at the last Nth bottom, it is possible to start the ON state at the occurrence of the (N-1) th bottom. That is, even if the occurrence of the number of bottoms of the ringing signal tends to decrease, the number of times of ringing occurring during the OFF period of the switching element Q1 can be set to a certain number, thereby generating the magnetic distortion sound in the transformer. Can be prevented.
    [107] In the above-described procedures (2) to (4), the switching element Q1 is turned on by the occurrence of the Nth bottom last time while the occurrence of the bottom frequency of the ringing signal tends to decrease, while the (N-1) It has been described to turn ON by the occurrence of a bottom. However, the concept of the present invention is not limited to this manner. That is, the present invention can be applied to a state in which the occurrence of the bottom number of the ringing signal tends to increase. For example, the switching element Q1 is turned on by the (N + 1) generation while being turned on by the Nth generation last time under the condition that the occurrence of the bottom frequency of the ringing signal tends to decrease. The number of occurrences of the ringing signal generated during the OFF period of Q1) can be set to a certain number, thereby preventing the occurrence of the magnetic distortion sound in the transformer.
    [108] (Variation)
    [109] In the above-described embodiment, the latch circuits LATCH1 to LATCH5 equivalently count the number of occurrences of the ringing bottom generated in the drain-source of the switching element Q1 during the OFF period of the switching element Q1. Has a configuration. However, the present invention is not limited to these configurations, and, for example, by mounting one or more additional latch circuits, the number of occurrences of the bottom count of five or more ring signals can be counted.
    [110] In addition, although the OFF period control circuit 53 performs PWM control in the above-described embodiment, the present invention is applicable to an OFF period control circuit having a fixed OFF period when the switching power supply is designed such that the OFF period can be extended. Can be.
    [111] All of these and other variations and modifications of the described embodiments are intended in the foregoing disclosure. Therefore, it is preferable that the present invention be broadly interpreted in accordance with the proper meaning or appropriate range of the appended claims.
    [112] As described above, according to the present invention, the number of bottoms of the ringing signal generated in the transformer during the OFF period of the switching element is stored, and it is compared whether or not the stored number of bottoms is equal to the number of bottoms of the present time. In order to set the number of occurrences to a certain number, it is controlled so that the OFF period of the switching element is maintained until the number of times this bottom coincides with the number of times of the previous bottom stored. Therefore, it is possible to prevent the occurrence of the magnetic distortion sound in the transformer.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] In a switching power supply,
    A switching element connected in series with a primary winding of a transformer connected to a direct current (DC) power supply;
    A rectification smoothing circuit for rectifying and smoothing the alternating current (AC) voltage induced in the secondary winding of the transformer;
    An output voltage detection circuit for detecting an output voltage rectified and smoothed by the rectification smoothing circuit and outputting a voltage detection signal to a primary circuit of the transformer;
    A control circuit for controlling the ON period of the switching element to stabilize the output voltage based on the voltage detection signal from the output voltage detection circuit; And
    A bottom detecting circuit for detecting the bottom of the ringing at the same timing as the occurrence of the ringing between the capacitor and the transformer connected in parallel to the switching element during the OFF period of the switching element,
    The control circuit,
    A bottom number counting circuit for counting the number of occurrences of the bottom of the ringing detected by the bottom detecting circuit as the number of bottoms;
    A bottom count memory circuit for storing the bottom count counted by the bottom count count circuit;
    A bottom count comparison circuit for comparing whether the bottom count stored in the bottom count memory circuit coincides with the current bottom count or not; And
    And an OFF period control circuit for maintaining the OFF period of the switching element until the current number of times reaches the bottom number stored in the bottom number memory circuit according to the comparison result in the bottom number comparison circuit. Switching power supply.
    [2" claim-type="Currently amended] The method of claim 1,
    And a reset circuit for resetting the number of bottoms stored in said bottom number memory circuit.
    [3" claim-type="Currently amended] The method of claim 2,
    The reset circuit resets the number of bottoms stored in the bottom number memory circuit when the bottom number of ringing counted by the bottom number counting circuit increases or decreases. Device.
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    同族专利:
    公开号 | 公开日
    DE60201294T2|2005-02-24|
    CN1215637C|2005-08-17|
    JP2002369518A|2002-12-20|
    EP1265345B1|2004-09-22|
    KR100540523B1|2006-01-16|
    JP3412624B2|2003-06-03|
    CN1391335A|2003-01-15|
    DE60201294D1|2004-10-28|
    EP1265345A1|2002-12-11|
    US6542387B2|2003-04-01|
    US20020186571A1|2002-12-12|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-06-08|Priority to JP2001174291A
    2001-06-08|Priority to JPJP-P-2001-00174291
    2001-12-07|Application filed by 산켄덴키 가부시키가이샤
    2002-12-20|Publication of KR20020095005A
    2006-01-16|Application granted
    2006-01-16|Publication of KR100540523B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP2001174291A|JP3412624B2|2001-06-08|2001-06-08|Switching power supply|
    JPJP-P-2001-00174291|2001-06-08|
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