Semiconductor chip package having tape circuit board

专利摘要:
The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package having a tape wiring board interposed with a conductive lead pattern. The inner lead of the semiconductor chip package according to the prior art has to be multi-pinned, miniaturized and highly integrated with increasing and miniaturization of semiconductor chip, but has limitations in its physical size, shape, and formation space. Accordingly, in the present invention, the tape wiring board is formed on the active surface of the semiconductor chip in all directions, thereby solving the problems of lead arrangement, physical size reduction, and circuit formation space limitation due to the miniaturization and high integration of the semiconductor chip. In addition, since the tape wiring board is formed by the same apparatus and method as the manufacturing process of the flexible circuit board and the printed circuit board of the prior art, it is possible to reduce the economic consumption of additional device and process development.
公开号:KR20020091326A
申请号:KR1020010030370
申请日:2001-05-31
公开日:2002-12-06
发明作者:김태형
申请人:삼성전자 주식회사；
IPC主号:

专利说明:

Semiconductor chip package having a tape wiring board {Semiconductor chip package having tape circuit board}
[16] The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package having a tape wiring board interposed with a conductive lead pattern.
[17] As the memory capacities of electronic devices and information devices become larger, high integration of semiconductor memory chips such as DRAM and SRAM is accelerating, and as the light weight and multifunctionality of electronic devices and information devices become lighter, the thinner and smaller pins of semiconductor chip packages are achieved ought. Therefore, while the size of the semiconductor chip is decreasing, the number of leads per semiconductor chip is increasing and the thickness and width thereof are decreasing according to the trend of higher integration.
[18] A semiconductor chip package according to the prior art will be described with reference to the drawings.
[19] 1 is a partial cutaway view of a semiconductor chip package according to the prior art, and FIG. 2 is a cross-sectional view of the semiconductor chip package taken along line A-A of FIG. 1.
[20] The semiconductor chip package 100 according to the related art includes a semiconductor chip 110 having an active surface provided with a bonding pad 180, an inner lead 130a attached to the active surface by an adhesive means 150, and A lead 120 including an external lead 130b connected to the wire 120, a wire 120 electrically connecting the bonding pad 180 and the internal lead 130a, and a semiconductor chip 110, a wire 120, and an internal lead ( It characterized in that it has a package body 160 formed by sealing 130a).
[21] In general, the size of the semiconductor chip 110 may be reduced by forming a center bonding pad type rather than an edge bonding pad type. The lead 130 electrically connected to the center bonding pad type semiconductor chip 100 is a lead on chip type (LOC type) attached to an active surface such that the inner lead 130a is close to the bonding pad 180. As a result, problems associated with an increase in wire loop height, such as wire tiling, device metal exposure, and cost increase, may be reduced.
[22] However, as described above, the semiconductor chip 110 has an increased degree of integration and a smaller size, and the inner lead 130a attached to the semiconductor chip 110 has to be further miniaturized and multiplied, but has a limitation in physical size and shape. In addition, in the semiconductor chip package 100, the leads 130 are arranged in two opposite directions of the semiconductor chip package 100, thereby limiting a space for arranging the leads 130. When the semiconductor chip 110 is formed in an edge bonding pad type to overcome the limitation of the lead 130, the number of semiconductor chips per wafer is reduced and the circuit design of the semiconductor chip that has been formed in the center bonding pad type is accompanied.
[23] Accordingly, an object of the present invention is to provide a semiconductor chip package having a tape wiring board to facilitate electrical connection between the semiconductor chip and the internal leads.
[1] 1 is a partial cutaway view of a semiconductor chip package according to the prior art,
[2] 2 is a cross-sectional view of the semiconductor chip package taken along the line A-A of FIG.
[3] 3 is a plan view of a semiconductor chip package according to the present invention,
[4] 4 is a cross-sectional view of the semiconductor chip package taken along the line B-B of FIG.
[5] 5 is a partially enlarged view of part C of FIG. 3;
[6] FIG. 6 is a process diagram of part C of FIG. 3.
[7] Description of the main parts of the drawing
[8] 100, 200: semiconductor chip package 110, 210: semiconductor chip
[9] 120, 220: wire 130, 230: lead
[10] 130a, 230a: internal lead 130b, 230b: external lead
[11] 150, 250: bonding means 160, 260: package body
[12] 180, 280: bonding pad 225: die pad
[13] 270 tape wiring board 273 conductive lead pattern
[14] 275 slot 276 connection hole
[15] 277: insulating tape
[24] In order to achieve the above object, a semiconductor chip package including a tape wiring board according to the present invention comprises: a semiconductor chip having an active surface provided with a bonding pad and a back surface opposite thereto and attached with a die pad; A slot attached to the active surface and formed to expose the bonding pad, an insulating tape, a conductive lead pattern interposed inside the insulating tape and exposed by the slot and connected to the bonding pad, and a conductive lead pattern are exposed. A tape wiring board having slots formed so as to expose connection holes and bonding pads formed on all sides; A lead including an inner lead connected to the conductive lead pattern exposed by the connection hole and a wire and positioned outside the semiconductor chip, and an outer lead connected thereto; And a package body encapsulating a semiconductor chip, a tape wiring board, a die pad, a wire, and an internal lead.
[25] Here, the conductive lead pattern exposed by the slot and the bonding pad are electrically connected by a beam lead bonding method, and the semiconductor chip is preferably a center bonding pad type. In addition, the lead preferably includes an inner lead formed on four sides of the semiconductor chip spaced apart by a predetermined distance, and an outer lead formed integrally with the inner lead and facing in two opposite directions of the semiconductor chip package.
[26] Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.
[27] 3 is a plan view of a semiconductor chip package according to the present invention, FIG. 4 is a sectional view of the semiconductor chip package taken along the line BB of FIG. 3, FIG. 5 is a partially enlarged view of part C of FIG. 3, and FIG. 6 is a part C of FIG. It is a process chart.
[28] The semiconductor chip package 200 including the tape wiring board 270 according to the present invention according to FIGS. 3 and 4 may include a semiconductor chip 210 including an active surface on which a bonding pad 280 is formed and a reverse surface thereof. ) And the tape wiring board 270. The tape wiring board 270 includes an insulating tape 277, a conductive lead pattern 273 interposed in the insulating tape 277, a connection hole 276 formed to expose the conductive lead pattern 273, and a semiconductor. A slot 275 is formed to expose the bonding pads 280 of the chip 210. The conductive lead pattern 273 is formed of a conductive material, and it is economical to use copper and can increase electrical efficiency. Since the conductive lead pattern 273 is exposed by the connection holes 276 formed on all sides of the tape wiring board 270 and connected to the internal lead 230a, a circuit formation space for multi-pinning and high integration is increased. Can be formed.
[29] The tape wiring board 270 is preferably formed by including a polyimide tape having a conductive layer formed on one surface thereof and an adhesive resin formed on the other surface thereof. The conductive layer of the tape is formed of a conductive lead pattern 273 through exposure, development, and etching processes, and an insulating layer made of polyimide is formed on the formed conductive lead pattern 273 to form a tape wiring board 270. Prepared. Therefore, the manufacturing method of the tape wiring board 270 is the same as the manufacturing method of the flexible circuit board and the printed circuit board of the prior art, thereby reducing the economic burden of developing additional devices and technologies. Can be.
[30] The semiconductor chip package 200 also includes a semiconductor chip 210 having an active surface provided with a bonding pad 280 and a reverse side thereof and a back surface to which the die pad 225 is attached by an adhesive means 250. The tape wiring board 270 is attached to the active surface. At this time, when heat is applied to the adhesive resin of the tape wiring board 270, the adhesive resin is melted and cured to adhere to the active surface of the semiconductor chip 210.
[31] The bonding pads 280 of the semiconductor chip 210 are electrically connected to correspond to the conductive lead patterns 273 exposed by the slots 275 of the tape wiring board 270. In particular, the conductive lead pattern 273 exposed by the slot 275 as shown in FIG. 6 is connected to the bonding pads 280 by thermal compression using a beam lead bonding tool. It is preferred to be connected.
[32] The conductive lead patterns 273 in the connected state by the beam lead bonding method are partially cut as shown in FIG. 5 and electrically connected to the bonding pads 280. Since the tape wiring board 270 shown in FIGS. 3 and 4 is advantageously applied to the center bonding pad type semiconductor chip rather than the edge bonding pad type semiconductor chip, the semiconductor chip 210 itself is reduced in size and the semiconductor chip per wafer. The yield of 210 can be improved.
[33] The lead 230 including the inner lead 230a and the outer lead 230b includes a conductive lead pattern 273 and a wire 220 exposed by connection holes 276 formed on all sides of the tape wiring board 270. It is connected to the internal lead 230a by the electrically connected to the semiconductor chip 210. In this case, the inner leads 230a are formed at four sides of the semiconductor chip 210 at a predetermined distance, and the outer leads 210b integral with the inner leads 230a face the semiconductor chip package 200. It is preferably formed to face in two directions.
[34] Therefore, the semiconductor chip package 200 according to the present invention is exposed by the bonding pads 280 and the slots 275 of the semiconductor chip 210, the semiconductor chip 210, and the conductive lead patterns 273 connected to the bonding pads 280. And an electrical signal path of the conductive lead pattern 273 -wire 220 -inner lead 230a -outer lead 230b exposed by the connection hole 276 and connected by the wire 220.
[35] The semiconductor chip 210, the tape wiring board 270, the die pad 280, the wire 220, and the inner lead 230a may be formed of a sealing resin such as an epoxy molding compound (EMC). By being encapsulated by the package body 260, it is protected from the external environment.
[36] On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented.
[37] Accordingly, according to the structure of the present invention, by forming a tape wiring board having a conductive lead pattern electrically connecting the semiconductor chip and the lead to the active surface of the semiconductor chip, the arrangement and physical size of the lead are reduced due to the miniaturization and high integration of the semiconductor chip. The problem according to the limit can be solved, and the circuit formation space can be increased because the conductive lead pattern can be formed on all sides of the tape wiring board and connected to the internal lead.
[38] In addition, since the tape wiring board is formed by the same apparatus and method as the manufacturing process of the tape wiring board substrate and the printed circuit board of the prior art, it is possible to reduce the economic consumption of additional device and process development.

权利要求:
Claims (4)
[1" claim-type="Currently amended] A semiconductor chip having an active surface provided with a bonding pad and a back surface opposite thereto and having a die pad attached thereto;
A slot attached to the active surface and formed to expose the bonding pad, an insulating tape, and a conductive lead pattern interposed in the insulating tape and exposed by the slot to the bonding pad; A tape wiring board having connection holes formed in all directions to expose the conductive lead patterns;
A lead including an internal lead connected to the conductive lead pattern exposed by the connection hole and a wire and positioned outside the semiconductor chip, and an external lead connected thereto;
And a package body for sealing the semiconductor chip, the tape wiring board, the die pad, the wire, and the internal lead.
[2" claim-type="Currently amended] The semiconductor chip package of claim 1, wherein the conductive lead pattern and the bonding pad exposed by the slot are electrically connected by a beam lead bonding method.
[3" claim-type="Currently amended] The semiconductor chip package of claim 1, wherein the semiconductor chip is a center bonding pad.
[4" claim-type="Currently amended] The semiconductor device of claim 1, wherein the lead includes an inner lead formed on four sides of the semiconductor chip spaced apart by a predetermined distance, and an outer lead formed integrally with the inner lead and facing two directions of the semiconductor chip package. A semiconductor chip package comprising a tape wiring board, characterized in that.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-05-31|Application filed by 삼성전자 주식회사

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2001-05-31|Priority to KR1020010030370A

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2002-12-06|Publication of KR20020091326A

优先权:

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申请号 | 申请日 | 专利标题

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KR1020010030370A|KR20020091326A|2001-05-31|2001-05-31|Semiconductor chip package having tape circuit board|