• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The device inspection apparatus of the present invention inspects a plurality of devices for each individual device. The inspection target classifying section 8 omits the inspection to be performed on the semiconductor element according to the information specifying the defective element determined to be defective in the manufacturing process of the element.
    公开号:KR20020088001A
    申请号:KR1020027014268
    申请日:2001-04-24
    公开日:2002-11-23
    发明作者:카라사와와타루
    申请人:동경 엘렉트론 주식회사；
    IPC主号:
    专利说明:

    Semiconductor Device Inspection System {SEMICONDUCTOR DEVICE INSPECTION SYSTEM}
    [2] In the manufacturing process of a semiconductor integrated circuit, the result of this process is observed after completion | finish of one process. At this time, the thickness of the film deposited on the wafer forming the semiconductor integrated circuit is measured by a separate inspection device rather than the manufacturing device that performed the process. In addition, particle inspection can also be performed. Thereby, the process is checked, that is, when a defect is found in the object inspected by this inspection, it is determined that the manufacturing apparatus has a specific defect, and the manufacturing apparatus is repaired. In addition, inspecting all wafers reduces productivity, so only one wafer is sampled and inspected.
    [3] Recently, the inspection apparatus described above is installed inside a manufacturing apparatus that performs a process. As a result, a manufacturing apparatus has been developed that can inspect all wafers without compromising productivity. Since the inspection apparatus is provided inside this kind of manufacturing apparatus, after a defective portion is detected in the manufactured wafer, the detection result is fed back directly to the manufacturing apparatus to take an action of automatically changing the process conditions.
    [4] However, the thickness of the film formed on the wafer may vary for each wafer, or may vary within each wafer. In process conditions such as temperature and pressure, unstable due to unevenness that occurs due to changes in time, difference in position, and the like. Due to such instability, there may be a case where a defective portion cannot be detected or the degree of the defect is small. In this case, the manufacturing process continues without changing the process conditions.
    [5] When performing the final probe inspection process after finishing this manufacturing process, the semiconductor integrated circuits formed on the wafer are subjected to an electrical functional test to determine whether their quality is good.
    [6] Therefore, even when the probe inspection in the last process step described above determines that the semiconductor integrated circuit is defective, this probe inspection is performed for all the chips formed in the semiconductor integrated circuit. Thus, probe inspection is also performed on defective semiconductor integrated circuits that are not adopted as products. As such, there is a problem that probe inspection is unnecessarily executed in a defective semiconductor integrated circuit.
    [1] TECHNICAL FIELD The present invention relates to an inspection apparatus, and more particularly, to an inspection apparatus and a system for inspecting semiconductor elements.
    [19] 1 is a block diagram showing a schematic structure of a semiconductor integrated circuit manufacturing system according to a first embodiment of the present invention;
    [20] Fig. 2 is a block diagram showing the structure of the probe inspection device shown in Fig. 1.
    [21] 3 is a flow chart of the operation of the probe inspection device shown in FIG.
    [22] FIG. 4 is an explanatory diagram for explaining data conversion performed by the probe inspection device shown in FIG. 2. FIG.
    [23] 5 is a block diagram showing a schematic structure of a semiconductor integrated circuit manufacturing system according to a second embodiment of the present invention.
    [7] It is a general object of the present invention to provide an improved useful device inspection apparatus without the above-mentioned problems.
    [8] A more specific object of the present invention is to provide a device inspection apparatus and method which efficiently inspects semiconductor devices to improve productivity and production costs.
    [9] In order to achieve these objects, there is provided an element inspection apparatus for inspecting a plurality of elements for each element according to one aspect of the present invention, and the inspection target classification unit detects a defective element determined to be defective in the manufacturing process applied to the element. The inspection to be performed in the device is omitted according to the information to be specified.
    [10] According to the above-described invention, by eliminating the inspection performed on the defective element by the inspection target classification unit, the inspection time performed after completing the element can be reduced.
    [11] The device inspecting apparatus according to the present invention further includes a marking part in which the inspection target classifier marks one of the elements in which the inspection is omitted. Thus, the defective element can be easily recognized by this mark.
    [12] In addition, in the device inspection apparatus according to the present invention, information specifying the defective device can be stored in the memory unit, and this information can be used at an appropriate time if necessary, so that a reliable device without the defective device can be obtained. .
    [13] According to another aspect of the present invention, there is provided an element fabrication system including an element fabrication apparatus for manufacturing a plurality of elements and obtaining information specifying the element having a defective portion, and an element inspection device for inspecting the elements manufactured by the element fabrication apparatus. Provided, the device inspection apparatus includes an inspection object classifying unit that omits inspection performed on the device according to information specifying a defective device executed during the manufacturing process performed by the device manufacturing apparatus.
    [14] According to the above-described invention, since the inspection performed on the defective element in the inspection target classification section can be omitted, the inspection time performed after completing the element can be reduced.
    [15] Further, according to another feature of the present invention, a plurality of element manufacturing apparatuses and an inspection apparatus for inspecting elements manufactured by a manufacturing process executed by the element manufacturing apparatus, wherein the inspection unit is manufactured by at least two element manufacturing apparatuses After providing the device to the process, an inspection is performed to determine whether or not the device is defective during the manufacturing process of these devices, and the inspection is obtained by obtaining information specifying one of the devices determined to be defective. The apparatus is characterized in that it comprises an inspection target classifying section which omits the inspection carried out on the element in accordance with information specifying the defective element determined to be defective in the manufacturing process of the element.
    [16] According to the present invention described above, the inspection target classifying unit can omit the inspection to be performed on the defective element, and by thus omitting the inspection can reduce the inspection time performed after completing the element.
    [17] In addition, according to another aspect of the present invention, there is provided an element inspection method for inspecting a plurality of elements for each individual element, preparing information for specifying a defective element determined to be defective in an element fabrication process, and preparing such information. And omitting the inspection to be performed on one of the elements determined to be defective according to the information prepared in the. The device inspection method further includes providing a mark to one of the elements for which the inspection is omitted. The device inspection method further includes storing information prepared in this preparation step in a memory.
    [18] Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.
    [24] An embodiment of the present invention will be described with reference to the drawings. Although the manufacture of semiconductor integrated circuits will be described below as an example, the present invention is not limited to the manufacture of semiconductor integrated circuits, but can be widely applied to the manufacture of devices including liquid crystal display panels and the like.
    [25] 1 illustrates a schematic structure of a semiconductor integrated circuit manufacturing system according to an embodiment of the present invention. As shown in Fig. 1, a semiconductor integrated circuit manufacturing system according to a first embodiment of the present invention is used in a semiconductor manufacturing process including a diffusion apparatus 1, a lithographic apparatus 3, an etching apparatus 5, and the like. A plurality of devices, a probe inspection device 7 for inspecting each semiconductor chip manufactured through this manufacturing process for each individual chip, and a communication line 9 for interconnecting these devices are included.
    [26] In the above-mentioned diffusion apparatus 1, the diffusion process by the ion implantation method is performed on the wafer which forms a semiconductor integrated circuit. In addition, in the lithographic apparatus 3, pattern formation is formed by applying a sensitization agent to the surface of a wafer, printing a predetermined pattern, developing it, and then exposing it through a photograph mask. In the etching apparatus 5, an etching process such as selectively removing an oxide film is performed. In the probe inspection apparatus 7, the probe of an individual chip formed on the wafer is brought into contact with the probe, and a connection test of the circuit formed on the chip is performed.
    [27] As shown in FIG. 1, the inspection sections 2, 4, 6 are included in the diffusion apparatus 1, the lithographic apparatus 3 and the etching apparatus 5, respectively. The inspection target classifying section 8 is embedded in the probe inspection device 7. The inspection sections 2, 4, 6 and the inspection target classification section 8 are connected by a communication line 9.
    [28] The operation outline of the semiconductor integrated circuit manufacturing system having the above-described structure will now be described. First, each inspection unit 2, 4, 6 shown in FIG. 1 checks for each individual wafer whether or not a wafer has passed through each manufacturing process. That is, for example, the inspection unit 6 embedded in the etching apparatus 5 measures the thickness of the wafer subjected to the predetermined etching in the etching apparatus 5, and determines whether the thickness of the wafer is within the allowable range of the design value. Check it. If the measured thickness is not within the allowable range, it is determined that the wafer is defective.
    [29] At this time, each inspection unit 2, 4, 6 specifies a position on the wafer determined to be a defective portion by the inspection conducted by this inspection unit, and information for specifying this position (for example, map data such as position coordinate data). Is provided to the inspection target classifying section 8 of the probe inspection device 7 via the communication line 9.
    [30] As a result, the inspection target classifying section 8 excludes the chip containing the portion of the inspection object 2, 4, 6 which has been determined to be defective from the target object to be provided for the probe inspection according to this provided information. Therefore, since the probe inspection on the chip determined to be defective in the product is omitted, it is not necessary to spend time spent due to the inspection which is not useful, and thus the probe inspection time can be shortened.
    [31] It should be noted that the use of the communication line 9 is unnecessary even when the information for specifying the defective chip is provided from the inspection units 2, 4, 6 to the inspection target classification unit 8 via the communication line 9. will be. For example, the information obtained by each inspection unit 2, 4, 6 can be recorded in a recording medium such as a floppy disk or CD-ROM. This recording medium can then be attached to the probe inspection device 7 to provide the inspection target classifying section 8 with the information recorded on the recording medium.
    [32] The semiconductor integrated circuit manufacturing system shown in FIG. 1 will now be described in detail. FIG. 2 is a block diagram showing the structure of the probe inspection device 7 shown in FIG. As shown in FIG. 2, the probe inspection device 7 includes an inspection target classifying section 8, a marking section 18 and a pro section inspection section 20. The inspection target classifying unit 8 includes a bus 10, a memory unit 11, a data converter 13, a central processing unit (CPU) 15, a map constructing unit 17, and a variable input unit 19. do. The memory unit 11, the data converter 13, the CPU 15, the map constructing unit 18, the variable input unit 19, and the professional unit inspecting unit 2 are connected to the bus 10. This bus is connected to a communication line (shown in FIG. 1) 9 via a communication interface 12.
    [33] The operation of the probe inspection device 7 will now be described with reference to FIG. 3. First, when applying power to the semiconductor integrated circuit manufacturing system, the CPU 15 sends a command to the variable input unit 19 for the user to request input of the variable. Then, as shown in step S1 of FIG. 3, the user inputs various variables into the variable input unit 19. For example, these variables include information about the orientation of the original flat (notch), which is a mark specifying the size of the wafer, the size of each chip formed on the wafer, and the location of the chip formed on the wafer.
    [34] Then, in step S2, the probe inspection unit 20 carries the wafer to be tested to a predetermined position to position the wafer based on the position of the original flat formed on this wafer. Note that the X-Y stage controlled by the interferometer is used for position operation. After prealigning the coarse position of the wafer, fine alignment is performed.
    [35] Then, in step S3, the CPU 15 determines whether the wafer carried in step S2 is the first of the wafers to be inspected. If it is determined that this wafer is the first wafer, the process proceeds to step S10. Otherwise, if it is determined that the wafer is not the first wafer, the process proceeds to step S4.
    [36] That is, in the first test, the probe of the probe inspection unit 20 is connected to the electrode of the chip to be tested by manually moving the chuck to which the wafer containing the chip is placed to perform positioning. Note that this initial setting is only needed once, because the position of the second wafer and the wafer following the second wafer can be automatically executed based on the positional information obtained through the initial setting and stored in the memory unit 11. to be.
    [37] Next, in step S4, the positions of the chips at the ends of the four directions of the wafer on which the probe inspection unit 20 is to be tested are measured. The map construction unit 17 generates a basic map indicating the position of the chip set as an object to be provided to the probe inspection according to the position information obtained through the measurement.
    [38] On the other hand, the CPU 15 stores the position information of the defective chip in the memory unit 11 according to the result of the inspection by each inspection unit 2, 4, 6 (shown in FIG. 1), and map configuration unit. (17) generates an inspection map indicating the position of the defective chip according to the inspection result of the previous process based on the position information.
    [39] We will now explain the creation of an inspection map. Each inspection unit 2, 4, 6 shown in FIG. 1 measures the wafer position of the defective portion, and acquires positional information about this portion. At this time, the xy (or XY) coordinate system shown in FIG. 4 is used. The xy (or XY) coordinate system has a coordinate corresponding to the center point PA of the wafer 21 or the intersection PB of the tangents 23 and 24 of the wafer 21 as the origin. As shown in FIG. 4, in the xy coordinate system having a coordinate corresponding to the center point PA of the wafer as the origin, the coordinates x 1 and y 1 are obtained as position information of the chip 22.
    [40] Then, the positional information obtained at each inspection section 2, 4, 6 is provided to the memory section 11 via the communication line 9 as map data. At this time, the information specifying the coordinate system used as a standard when generating the positional information is provided to the memory unit 11 together with the positional information.
    [41] Then, when it is determined that the coordinate systems of the information provided by the inspection units 2, 4, 6 are different from each other in the above-described standard, the CPU 15 issues a command to execute the coordinate transformation for the data conversion unit 13 This ensures that all location information is represented in one of the coordinate systems.
    [42] As a result, the data conversion unit 13 performs coordinate transformation by primary conversion or the like. The position information thus obtained is stored in the memory unit 11 and provided to the map constructing unit 17. Then, the CPU unit 15 generates the inspection map indicating the position of the portion determined to be defective through inspection of the previous process based on the position information. It should be noted that the inspection map generated by this is stored in the memory unit 11.
    [43] Next, in step S5, it is determined whether or not the inspection map should be considered when a decision is made to select a chip as an object to be provided to the probe inspection. The use of the inspection map is determined by the user in response to a request by the CPU 15. If the user instructs to consider the inspection map through keyboard input or the like, the path proceeds to step S6. Otherwise, the path proceeds to step S7.
    [44] In step S6, in accordance with the instruction of the CPU 15, the map construction unit 17 superimposes the inspection map on the basic map generated in step S4 to generate a new inspection target instruction map. This new inspection target indication map indicates only the chip positions other than those of the chips on the wafer made up of the objects to be provided for probe inspection that contain portions determined to be defective in previous processes. The inspection target instruction map is also stored in the memory unit 11.
    [45] Next, in step S7, the probe inspecting unit 20 performs probe inspection only one by one with respect to the chip explicitly indicating the position on the inspection target instruction map. Then, when the probe inspection is finished for all the chips indicated in the inspection target instruction map, the path proceeds to step S8. In step S8, the CPU 15 determines whether there is a next wafer to be provided for probe inspection. If it is determined that there is the next wafer to be examined, the path proceeds to step S2. Otherwise, if it is determined that there is no next wafer to inspect, the path ends.
    [46] Note that by marking the chip determined to be defective by probe inspection, the unmarked chip can be packaged in the next process. In addition, it is possible to provide a mark on a chip determined to be defective in a previous process, such as a process performed by the diffusion apparatus 1, the lithographic apparatus 3, or the etching apparatus 5, before performing the probe inspection. That is, when a user inputs a command to mark according to the inspection in the previous process, the CPU 15 reads the inspection map stored in the memory unit 11 and provides the inspection map to the marking unit 18. Then, the marking portion 18 provides the marks one by one to the chips containing the defect portions indicated in the provided inspection map.
    [47] Therefore, a reliable semiconductor integrated circuit can be manufactured positively since the chip without marking can be easily distinguished by a good quality product when picking up the chip.
    [48] In addition, since an inspection map indicating the position of the chip determined to be defective by inspection of the previous process is stored in the memory unit, it is useful for recording the inspection map on a recording medium such as a floppy disk or CD-ROM. This recording medium is attached to a pickup device that picks up a chip and provides an inspection map to the pickup device. Alternatively, the inspection map may be provided to the pickup device via a communication line. That is, when the chips indicated on the inspection map as having a defective portion are prevented from being picked up by the pickup device, unnecessary pick-up operation can be omitted, thereby improving the manufacturing efficiency of the semiconductor integrated circuit.
    [49] In addition, the diffusion apparatus 1, the lithographic apparatus 3, the etching apparatus 5 and the probe inspection apparatus 7 shown in FIG. 1 may constitute only one wafer processing system installed in one conveying system. According to such a system, a wafer is sequentially provided to the above devices provided to the system while being automatically transported to / from the above devices, to be inspected through the processing of the wafer. Therefore, since the time required for probe inspection can be reduced, the probe inspection efficiency can be improved and the productivity of the manufacturing system of the semiconductor integrated circuit can be increased.
    [50] 5, a semiconductor integrated circuit manufacturing system according to a second embodiment of the present invention will now be described. 5 is a block diagram of a schematic structure of a semiconductor integrated circuit manufacturing system according to a second embodiment of the present invention. As shown in FIG. 5, even if the semiconductor integrated circuit manufacturing system according to the second embodiment of the present invention has the same configuration as the semiconductor integrated circuit manufacturing system according to the first embodiment of the present invention shown in FIG. The difference between the systems is that the semiconductor integrated circuit fabrication system according to the second embodiment is equipped with only one wafer transport system for transporting one wafer at a time. Only one wafer conveying system is constituted by a supply 29, conveying paths 30 and 31, a stocker 33 and a storage device 35.
    [51] In addition, as shown in FIG. 5, the plurality of etching apparatuses 25 without the inspection portion are arranged in parallel along the conveying path 31. In addition, an independent inspection section 6 is provided along the same conveyance path 31 as in one row of etching apparatus.
    [52] Note that the aforementioned supply part 29 is connected to one end of the conveying path 30, and the stocker 33 is connected to one end of the conveying path 31. The storage device 35 is connected to the probe inspection device 7.
    [53] Since the operation of the semiconductor integrated circuit manufacturing system according to the second embodiment of the present invention is basically the same as the operation of the semiconductor integrated circuit manufacturing system according to the first embodiment shown in FIG. I will explain.
    [54] First, the wafers provided to the supply part 29 are conveyed one by one to the diffusion apparatus 1 along the conveyance path 30, and the diffusion apparatus 1 performs an expansion process on each wafer. Then, an inspection is carried out to determine whether there are any parts where defects have occurred during diffusion. If it is determined that there is a defective portion, positional information about the defective portion is obtained, and the positional information is provided to the inspection target classifier 8 via the communication line 9.
    [55] The wafer after the diffusion process is then transferred to the lithographic apparatus 3, which is patterned in the lithographic apparatus 3. The inspection unit 4 then inspects to determine whether there is a portion where a defect pattern has occurred. If it is determined that there is a defect pattern, the positional information of the defective portion is obtained, and the positional information is provided to the inspection target classifier 8 via the communication line 9.
    [56] Next, the patterned wafer is conveyed to the etching apparatus 25 along the conveyance path 31, and the etching apparatus 25 performs an etching process. Then, the etched wafer is conveyed to the inspection section 6 and inspected by the inspection section 6 to determine whether there is a defect etching section. If there is a defect etching portion, positional information relating to the defect etching portion is obtained, and the positional information is provided to the inspection target classifying portion 8 via the communication line 9. At this time, the plurality of wafers are simultaneously provided to the etching process by the plurality of etching apparatuses 25 arranged along the conveyance path 31. In addition, to adjust the processing speed of other fabrication processes, the etched wafer may be temporarily stored in stocker 33.
    [57] The wafer inspected by the inspection unit 6 is again transported along the conveyance path 30 to the next processing apparatus (not shown), and the predetermined process is sequentially performed. Thus, the processed wafer is conveyed to the probe inspection apparatus 7, and the probe inspection described in detail in the first embodiment is performed on the wafer. It is to be noted that the wafers that have passed the probe inspection can be transported and stored in the storage device 35 to be provided for the next process.
    [58] In addition, in the above-described structure, the supply portion 29, the stocker 33 and the storage device 35 do not necessarily need to be separated from each other. For example, the supply 29 may have the function of a stocker 33 or a storage device 35.
    [59] As described above, according to the semiconductor integrated circuit manufacturing system according to the present invention, since the inspection unit 6 is provided in the plurality of etching apparatuses 25, it is not necessary to provide the inspection unit in each etching apparatus 25. Thus, the cost of the etching apparatus 25 can be reduced, thereby reducing the cost of the entire semiconductor integrated circuit manufacturing system. In addition, even if the total non-operation time of the entire inspection unit is increased in the case of providing the inspection unit for each processing apparatus, its price / performance ratio can be improved by providing the inspection unit 6 in common to the plurality of processing apparatuses.
    [60] It should be noted that although the structure in which the etching apparatus 25 is only arranged in parallel is described in the second embodiment of the present invention, other apparatuses such as a cleaning apparatus or a chemical vapor deposition (CVD) apparatus may also be arranged in parallel. Is that there is. In addition, the same effect as that of the semiconductor integrated circuit manufacturing system shown in FIG. 5 can be achieved by providing a plurality of inspection portions shared in a plurality of processing devices arranged in parallel.
    [61] The present invention is not limited to the specific embodiments disclosed, but various modifications and changes may be made without departing from the scope of the present invention.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] An element inspection apparatus for inspecting a plurality of elements for each individual element,
    And an inspection target classifying section (8) for omitting the inspection to be performed on the elements in accordance with information specifying a defective element determined to be defective in the manufacturing process performed on the element.
    [2" claim-type="Currently amended] The device inspection apparatus according to claim 1, further comprising a marking portion (18) for providing a mark to one of the elements in which the inspection target classification portion (8) is omitted.
    [3" claim-type="Currently amended] The device inspecting apparatus according to claim 1, wherein the information specifying the defective element is stored in a memory section (11).
    [4" claim-type="Currently amended] Device manufacturing apparatuses (1, 3, 5) for manufacturing a plurality of devices to obtain information for specifying a device having a defective portion;
    An element inspection device 7 for inspecting elements manufactured in the element manufacturing apparatus,
    The device inspecting apparatus 7 includes an inspection target classifying section 8 which omits the inspection to be performed on the devices according to the information specifying the device having a defective portion formed during the manufacturing process of the device manufacturing apparatus. Device manufacturing system.
    [5" claim-type="Currently amended] 5. A device manufacturing system according to claim 4, comprising a marking section (18) for providing a mark to one of the devices in which the inspection target classifier (8) omits the inspection.
    [6" claim-type="Currently amended] The device inspection apparatus as claimed in claim 4, wherein the information specifying the defective device is stored in a memory unit (11).
    [7" claim-type="Currently amended] A plurality of device manufacturing apparatuses 25,
    An inspection device 7 for inspecting devices manufactured by executing a manufacturing process in the device manufacturing apparatus;
    After providing the devices to a manufacturing process by the at least two device manufacturing apparatuses, a test for determining whether or not a defect occurs in the devices during the manufacturing process of the device, and the devices determined to be defective It includes an inspection unit 6 for obtaining information specifying one of the,
    The inspection apparatus 7 includes an inspection object classifying section 8 which omits inspection to be performed on the elements according to information specifying a defective element determined to be defective in the manufacturing process of the element. .
    [8" claim-type="Currently amended] In the device inspection method for inspecting a plurality of devices for each individual device,
    Preparing information specifying a defective device determined to be defective in the manufacturing process of the devices;
    Omitting a test to be performed on one of the devices determined to be defective according to the information prepared in the preparation step.
    [9" claim-type="Currently amended] 9. The method of claim 8 including providing a mark to one of the elements that omit the inspection.
    [10" claim-type="Currently amended] The device inspection method of claim 8, further comprising storing the information prepared in the preparation step in a memory.
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    同族专利:
    公开号 | 公开日
    CN1211851C|2005-07-20|
    US20030155280A1|2003-08-21|
    EP1290726A4|2005-04-13|
    WO2001082364A1|2001-11-01|
    AU4885101A|2001-11-07|
    KR100779922B1|2007-11-28|
    TW586170B|2004-05-01|
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    CN1434981A|2003-08-06|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-04-25|Priority to JP2000124875
    2000-04-25|Priority to JPJP-P-2000-00124875
    2001-04-24|Application filed by 동경 엘렉트론 주식회사
    2002-11-23|Publication of KR20020088001A
    2007-11-28|Application granted
    2007-11-28|Publication of KR100779922B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP2000124875|2000-04-25|
    JPJP-P-2000-00124875|2000-04-25|
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