• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: An integrated device having a high-conductive gate, a local interconnect or a capacitor node for a stacked-type capacitor is provided to realize a high speed signal propagation in 0.25μm design rule and less. CONSTITUTION: A gate structure having a gate electrode(54) and a hard mask thereon is formed on a gate insulating layer(52) of a substrate(50). A sidewall spacer(62) is formed on sides of the gate structure, and the substrate(50) is exposed between adjacent spacers(62). A conductive layer(66) is formed on all surfaces and then an insulating layer(68) is formed thereon. An opening is formed in the insulating layer(68) to expose the gate electrode(54) and then a contact spacer(70) is formed therein. A metal plug(78) fills the opening and then two insulating layers(80,82) are formed thereon. A dual damascene structure(84), which has a lower contact plug and an upper local interconnect, is formed in the insulating layers(68,80,82) and connected to the conductive layer(66). Then, insulating layers(88,90) and conductive layers(92,94) are sequentially deposited to form a capacitor node.
    公开号:KR20020024555A
    申请号:KR1020010059246
    申请日:2001-09-25
    公开日:2002-03-30
    发明作者:박돈원
    申请人:추후제출；하이닉스 세미컨덕터 매뉴팩쳐링 아메리카 인코포레이티드；
    IPC主号:
    专利说明:

    Integrated devices with highly conductive gates, local interconnects, or capacitor nodes {AN INTEGRATED DEVICE WITH HIGHLY CONDUCTIVE GATE, LOCAL INTERCONNECTS, OR CAPACITOR NODES}
    [12] TECHNICAL FIELD The present invention relates to integrated devices, and more particularly, to integrated devices having highly conductive gates, local interconnects or node electrodes for stacked-type capacitors.
    [13] Conventional transistors implemented in silicon, eg MOSFETs, consist of a source and a drain formed in a silicon substrate, which are laterally separated to define the channel region within the substrate. A gate electrode made of a conductive material is disposed over the channel region and designed to emit an electric field to the channel region. The change in the electric field emitted by the gate electrode enables or optionally disables the flow of current between the source and the drain.
    [14] In a conventional process for forming a conventional MOSFET, a gate oxide layer is grown on a thinly doped silicon substrate, and a polysilicon layer is deposited on the gate oxide layer. The polysilicon and gate oxide layers are then anisotropically etched to the top surface of the substrate, leaving the polysilicon gate electrodes stacked on top of the gate oxide layer. After formation of the polysilicon gate electrode, the source and drain are formed by implanting the dopant into the substrate. The gate electrode serves as a hard mask for this implant, so that the source and drain are formed on a substrate self-aligned to the gate electrode.
    [15] The signal propagation rate of a semiconductor integrated device is typically determined by the semiconductor material (such as Si to GaAs), transistor characteristics (such as the ratio of width to length of the transistor junction), operating voltage, transistor circuit design, local interconnect, and the electrical contact of the contact. Determined by electrical conductance or the like. As semiconductor devices become smaller and smaller, the resulting shorter signal travel length improves the operating speed of the device. However, this advantage is offset by larger parasitic capacitance due to narrow spaces between the conductive lines, as well as greater resistance due to smaller electrodes, narrower interconnect lines and smaller contact geometry. do.
    [16] One method used to reduce the resistance of an electrode is the so-called silicide method, which forms silicide layers on the gate, source and drain electrodes of the transistor. This method forms a refractory metal film such as a titanium film or the like placed on these electrodes, and heat-treats the refractory metal film in order to react the electrode with the refractory metal film. The resulting compound is a silicide layer.
    [17] As semiconductor device structures shrink to less than 0.25 microns, the resistivity of titanium silicides, which are commonly used as contacts and poly gates for source and drain regions, undesirably increases. This increase in resistivity results from the standard two-step annealing process in which titanium silicide is formed. After the titanium layer is formed on the electrode, low temperature annealing is performed to convert titanium to the C49 phase of titanium silicide in those regions where the titanium and silicon interfaces are present. The C49 phase has a high resistivity and is not preferable as the final silicide material. The low temperature annealing inhibits the reaction of titanium with oxide regions (such as sidewall spacers and isolation regions), thus forming the C49 phase first. After the C49 phase is formed, a second high temperature annealing is performed, in which the C49 phase is converted to a C54 titanium silicide phase with lower resistivity. Unfortunately, as the transistor line width continues to decrease below 0.25 microns, the grain size of the silicide formed on C49 becomes too large (close to the device line width) to limit its conversion to C54. As a result, the resistivity of the silicide increases undesirably as the transistor size decreases below 0.25 micron. Thus, as device arrangements become smaller, there is a need for gate material to maintain or increase signal speed.
    [18] In order to solve the above problem, in one embodiment of the present invention, the semiconductor device includes a first insulating layer formed in the semiconductor region of the substrate. A gate electrode is provided on the first insulating layer, which has a lateral length of 0.25 μm or less. A first insulating spacer is provided adjacent to the gate electrode and defines an opening over the gate electrode. The metal plug fills the opening defined by the first insulating spacer and is in contact with the gate electrode.
    [19] In another embodiment, the semiconductor device includes a substrate having a first insulating layer thereon, the first insulating layer having an opening that exposes a portion of the substrate. A gate electrode is formed over the substrate. A metal plug is formed over the gate electrode and electrically connected to the top surface of the gate electrode. First and second electrical regions are formed on both sides of the gate electrode. Gate insulating spacers are formed adjacent to both sides of the gate electrode. A conductive layer is formed over the gate insulating spacer and the exposed portion of the substrate. The metal connector is connected to a conductive layer electrically connected to the substrate, and the metal contact connector has a dual damascene structure.
    [20] In another embodiment, the semiconductor device includes a gate electrode formed over the surface of the substrate. First and second electrical regions are formed on both sides of the gate electrode. A conductive layer overlying the substrate is provided over and electrically connected to the first and second electrical regions. The metal contact plug is electrically connected to the conductive layer.
    [1] 1 is a cross-sectional view of an active region of a semiconductor device after an initial gate electrode is formed on a gate insulator.
    [2] FIG. 2 shows the structure of FIG. 1 with sidewall spacers formed; FIG.
    [3] 3 shows the structure of FIG. 2 with a conductive layer formed thereon;
    [4] Figure 4 shows the structure of Figure 3 with an insulating layer formed thereon.
    [5] FIG. 5A shows the structure of FIG. 4 with the insulating layer etched to provide an opening that exposes the gate electrode; FIG.
    [6] FIG. 5B shows the structure of FIG. 5A with an insulating spacer formed in the opening; FIG.
    [7] Fig. 6 shows the structure of Fig. 5B with a metal plug filled in an opening formed by an insulating spacer.
    [8] Figure 7 shows the structure of Figure 6 with an insulating layer formed thereon.
    [9] FIG. 8 illustrates the structure of FIG. 7 with a double wavy structure including a local interconnect. FIG.
    [10] Figure 9 shows the structure of Figure 8 with an insulating layer formed thereon.
    [11] Figure 10 illustrates the structure of Figure 9 with a recessed capacitor cell structure formed around a local interconnect.
    [21] Referring to Fig. 1, the substrate 50 includes a gate insulator or a gate insulating film formed on the surface thereof, such as, for example, a silicon oxide film or a silicon nitride film (ie, SiO 2 or Si 3 N 4 ) or a combination thereof. do. A gate conductive layer or gate electrode 54, such as polysilicon, and a hard mask layer 56 are provided over the gate insulator 52. The hard mask layer usually consists of a combination of SiO 2 , or an antireflective coating material such as SiO 2 and silicon oxynitride (SiO x N y ), which improves the adjustment of the patterned critical dimension. The hard mask provided on the gate electrode is later removed to form a groove, as described later in FIG. Layers 54 and 56 are anisotropically etched to form gate structures 58 and 60. Gate structures 58 and 60 usually have a distance between the source and drain regions, which are laterally longer, i.e., 1.25 μm or less, preferably 0.13 μm or less. These layers may be etched in-situ, or the hard mask layer 56 and the gate conductive layer 54 may be etched separately.
    [22] 2, sidewall spacers 62 are formed on the left and right sides of gate structures 58 and 60. The gate sidewall spacer 62 is preferably an insulating material that can have high etching selectivity to another insulating material such as Si 3 N 4 , or SiO 2 . For example, gas mixtures comprising C 4 F 8 are known to provide higher etch selectivity of SiO 2 compared to Si 3 N 4 . Spacers are usually formed by chemical vapor deposition after anisotropic etching. An oxide opening 64 is made that exposes a portion of the substrate 50. Generally, the oxide film openings are formed by an anisotropic etching process used to form spacers.
    [23] Referring to Figure 3, a conductive layer 66, such as polysilicon, is formed over the substrate 50, gate structures 58 and 60 and spacers 62 using chemical vapor deposition. In one embodiment, the conductive layer of polysilicon is provided as an etch-stop layer for self-aligned contact etching. Compared with conventional silicon nitride etch-stop layers, the polysilicon conductive layer provides a much wider process window when etching SiO 2 . Moreover, the conductive layer provided in the contact openings can raise the source and drain from the silicon surface, thereby reducing undesirable short-channel effects. Referring back to FIG. 3, conductive layer 66 is etched in the field isolation region (not shown), so that the conductive layer only overlies the active region. And, as shown in Fig. 4, an insulator 68 such as SiO 2 is formed over the conductive layer. Insulators are planarized using chemical mechanical polishing or etchback methods.
    [24] 5A and 5B, the insulator 68 is anisotropically etched to form grooves or openings 69 and to expose the gate electrode 54. The conductive layer 66 serves as an etch-stop layer during this etching step. Once the conductive layer is exposed, the anisotropic etch process is turned into a tuned undercut etch process (eg, an isotropic etch process) that etches a portion of the conductive layer to form an undercut 70. As will be described later, the undercut 70 allows electrical separation between the conductive layer 66 and the metal plug to be formed over the gate electrode 54. After forming the undercut, an insulating contact spacer 72, such as Si 3 N 4 or silicon oxynitride (SiN x O y ) material, is formed in the groove 69 by performing chemical vapor deposition after anisotropic etching. (Figure 5b). Chemical vapor deposition fills the undercut and forms an insulator-filled handle 76.
    [25] A metal layer is deposited over the insulator 68 and the gate electrode 54 to fill the opening 69, thereby forming a metal plug 78 (FIG. 6). The metal layer may comprise one or more layers of different materials. For example, the metal plug 78 may include two thin layers Ti and TiN, and a tungsten metal plug as the adhesive and barrier metal layer.
    [26] As described above, an insulating spacer 72 surrounds the sidewall of the metal plug 78. This reduces the mechanical stresses and chemical interactions between the metal and adjacent insulators in subsequent process steps at high temperatures. The level of mechanical stress and chemical interaction between the metal and adjacent insulators corresponds to the temperature at which the substrate is exposed. In general, subsequent substrate processing steps include applying a high temperature to the substrate. Therefore, without an insulating spacer as a buffer, the mechanical stress between the metal plug and adjacent insulators can increase significantly during subsequent processing steps, causing cracks to form in the insulator. In addition, if an insulating spacer is not provided, the chemical interaction between the metal plug and adjacent insulators may increase in subsequent processing steps. An insulating space is also provided to electrically separate the metal plug 78 from the conductive layer 66. This electrical separation is also ensured by the additional margin provided by the handle 76 filled with the insulator of the insulating spacer. Another role of the spacer 72 is to compensate for the patterning of the gate hard mask 56 and the overlay margin between the gate conductive layer 66, which forms a groove 69 on top of the gate electrode 54. The etching process of the spacer 72 is optional for the gate electrode 54.
    [27] Referring to FIG. 7, an insulating layer 80, such as Si 3 N 4 or silicon oxynitride (SiN x O y ) material, is deposited over the metal plug. Then, an insulating layer 82 such as SiO 2 is deposited on the insulating layer 80. Insulating layer 80 surrounds the metal plug to minimize chemical interactions and mechanical stress between the metal and adjacent insulators. The insulating layer 80 also forms a dual damascene structure 84, ie, a contact plug (bottom) 87a and a local interconnect (top) 87b, as shown in FIG. It can be used as an etch stop layer during the etching of the insulating layer 82 to. Insulating spacers 86, such as Si 3 N 4 or silicon oxynitride (SiN x O y ) materials, are formed on the sidewalls of the double wavy structure and are in contact with the conductive layer 66. The double wavy structure 84 is formed by depositing a metal layer over the substrate and in the contact openings and removing residual metal using a chemical mechanical polishing process. The double wavy structure allows contact plugs and local interconnects to be formed in the same process step. In addition to the insulating spacer 72, the insulating spacer 86 is formed of a metal layer, in this case local interconnect 87, in order to minimize chemical stress and mechanical stress between the metal layer and adjacent insulators in subsequent processing steps of high temperature. Substantially surround it.
    [28] Referring to FIG. 9, a node electrode of a stacked capacitor may be formed on a local interconnect formed by the above-described double wave process. Forming a stacked capacitor includes depositing an insulating layer 88, such as Si 3 N 4 or silicon oxynitride (SiN x O y ) material. An insulating layer 90, such as SiO 2 , is deposited over the insulating layer 88. Insulating layers 88 and 90 are etched to form a hollow cylindrical structure (FIG. 10) around the local interconnect. Conductive layers 92 and 94 are sequentially deposited on this cylindrical structure to form conductive plates or node electrodes. The conductive layer 92 is mainly composed of a high conductive material such as Ti / TiN. This conductive layer provides increased conductivity and also serves as a barrier for diffusing atoms from the local interconnect 87 to the capacitor. The conductive layer 94 may be made of a material commonly used for forming capacitors, such as polysilicon or other types of silicon films.
    [29] The capacitor formed by the above method has a large capacitor cell area, and therefore, the capacitance of the capacitor is increased because the total capacitance is proportional to the effective area of the cell structure.
    [30] The present invention includes other embodiments. It is intended that the scope of the invention be defined by the claims appended hereto.
    权利要求:
    Claims (22)
    [1" claim-type="Currently amended] In a semiconductor device,
    A first insulating layer formed in the semiconductor region of the substrate;
    A gate electrode provided on said first insulating layer, said gate electrode having a lateral length of 0.25 [mu] m or less;
    A first insulation spacer provided adjacent said gate electrode to define an opening over said gate electrode; And
    A metal plug filling the opening defined by the first insulating spacer and contacting the gate electrode
    A semiconductor device comprising a.
    [2" claim-type="Currently amended] The method of claim 1,
    The first insulating layer has an opening exposing a portion of the substrate,
    A conductive layer provided over the first spacer and the exposed portion of the substrate and electrically connected to the substrate
    The semiconductor device further comprising.
    [3" claim-type="Currently amended] The method of claim 2,
    The conductive layer defines an elevated source or drain region.
    Semiconductor device.
    [4" claim-type="Currently amended] The method of claim 2,
    A second insulating layer provided over the conductive layer to define an opening that exposes an upper surface of the gate electrode, wherein the conductive layer has an undercut extended to the second insulating layer
    The semiconductor device further comprising.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    A second insulating spacer provided around the opening defined by the second insulating layer, the second insulating spacer comprising a handle defined by filling the undercut with an insulating material, the handle having the metal plug and the Provides better electrical isolation between conductive layers
    The semiconductor device further comprising.
    [6" claim-type="Currently amended] The method of claim 2,
    The conductive layer is made of polysilicon
    Semiconductor device.
    [7" claim-type="Currently amended] The method of claim 1,
    The metal plug is made of tungsten
    Semiconductor device.
    [8" claim-type="Currently amended] The method of claim 1,
    A dual damascene structure coupled to a portion of the substrate, wherein the dual moire structure includes a local interconnect and a contact plug;
    The semiconductor device further comprising.
    [9" claim-type="Currently amended] The method of claim 2,
    A double wavy structure in contact with the conductive layer and electrically connected to the substrate, wherein the double wavy structure includes a local interconnect and a contact plug
    The semiconductor device further comprising.
    [10" claim-type="Currently amended] In the method of forming a semiconductor device,
    Forming a gate insulating film on the substrate;
    Providing a gate electrode to the gate insulating film, wherein the gate electrode has a hard mask thereon;
    Forming a gate insulating spacer adjacent the gate electrode and the hard mask, wherein the gate insulating spacer exposes an upper surface of the hard mask;
    Forming a conductive layer over the gate insulating spacer, the hard mask, and an exposed portion of the substrate;
    Removing the hard mask and a portion of the conductive layer overlying the hard mask to provide an opening that exposes an upper surface of the gate electrode; And
    Forming a metal plug in the opening to be electrically connected to the gate electrode
    How to include.
    [11" claim-type="Currently amended] The method of claim 10,
    Forming a contact plug in the conductive layer, wherein the contact plug is electrically connected to the substrate
    How to include more.
    [12" claim-type="Currently amended] The method of claim 10,
    Forming an undercut in the conductive layer overlying the gate insulating spacer, wherein the undercut extends from the gate electrode to increase a distance between an edge of the gate electrode and an edge of the conductive layer.
    How to include more.
    [13" claim-type="Currently amended] The method of claim 10,
    The metal plug comprises tungsten
    Way.
    [14" claim-type="Currently amended] In a semiconductor device,
    A substrate having a first insulating layer thereon, wherein the first insulating layer has an opening that exposes a portion of the substrate;
    A gate electrode formed on the substrate;
    A metal plug formed on the gate electrode and electrically connected to an upper surface of the gate electrode;
    First and second electrical regions formed on both sides of the gate electrode;
    Gate insulating spacers formed adjacent to both sides of the gate electrode;
    A conductive layer formed over the gate insulating spacer and an exposed portion of the substrate; And
    A metal contact connector connected to the conductive layer to be electrically connected to the substrate, wherein the metal contact connector has a double wavy structure
    A semiconductor device comprising a.
    [15" claim-type="Currently amended] The method of claim 14,
    The conductive layer defines an elevated drain or source region.
    Semiconductor device.
    [16" claim-type="Currently amended] The method of claim 14,
    The conductive layer overlying the gate spacer includes an undercut that increases the distance between the edge of the conductive layer and the edge of the gate electrode.
    Semiconductor device.
    [17" claim-type="Currently amended] The method of claim 16,
    A metal plug spacer formed around a sidewall of the metal plug, the metal plug spacer made of a first insulating material; And
    A second insulating layer surrounding the metal plug spacer, the second insulating layer being made of a second insulating material, the metal plug spacer providing a buffer between the metal plug and the second insulating layer;
    The semiconductor device further comprising.
    [18" claim-type="Currently amended] In a semiconductor device,
    A gate electrode formed over the surface of the substrate;
    First and second electrical regions formed on both sides of the gate electrode;
    A conductive layer provided over and electrically connected to the first and second electrical regions, the conductive layer overlying the substrate; And
    A metal contact plug electrically connected to the conductive layer
    A semiconductor device comprising a.
    [19" claim-type="Currently amended] The method of claim 18,
    The conductive layer defines an elevated source or drain region.
    Semiconductor device.
    [20" claim-type="Currently amended] The method of claim 19,
    The metal contact plug is a double wavy structure having a top and a bottom
    Semiconductor device.
    [21" claim-type="Currently amended] The method of claim 20,
    A capacitor having a first conductive plate formed over and around an upper portion of the metal contact plug
    The semiconductor device further comprising.
    [22" claim-type="Currently amended] The method of claim 21,
    The first conductive plate is electrically connected to an upper surface of the upper portion of the metal contact plug.
    Semiconductor device.
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    同族专利:
    公开号 | 公开日
    KR100727449B1|2007-06-13|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-09-25|Priority to US23526200A
    2000-09-25|Priority to US60/235,262
    2001-09-25|Application filed by 추후제출, 하이닉스 세미컨덕터 매뉴팩쳐링 아메리카 인코포레이티드
    2002-03-30|Publication of KR20020024555A
    2007-06-13|Application granted
    2007-06-13|Publication of KR100727449B1
    优先权:
    申请号 | 申请日 | 专利标题
    US23526200A| true| 2000-09-25|2000-09-25|
    US60/235,262|2000-09-25|
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