• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for fabricating a transistor is provided to prevent the characteristic of the transistor from being degraded, by preventing conductive impurity ions implanted to a gate electrode from penetrating a gate insulation layer and being diffused to an active region of a substrate while minimizing the increase of the thickness of the gate insulation layer. CONSTITUTION: The first material layer doped with nitrogen and the second material layer doped with conductive impurities are sequentially formed on the substrate(40). A gate stack material is composed of the first and second material layers. The thickness of the second material layer is increased in the gate stack material. The resultant structure where the thickness of the second material layer is increased is patterned to form a gate pattern. The first junction region(54) is formed in the active region adjacent to the gate pattern. A gate spacer(56) is formed on the side surface of the gate pattern. The second junction region(60) deeper than the first junction region is formed in the first junction region while conductive impurity ions are implanted into the gate pattern. The thickness of the second material layer is further increased inside the gate stack material.
    公开号:KR20020022421A
    申请号:KR1020000055202
    申请日:2000-09-20
    公开日:2002-03-27
    发明作者:김세표
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Method for forming a transistor
    [10] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a transistor forming method.
    [11] Complementary metal oxide semiconductor consisting of an N-channel metal oxide semiconductor (N-MOS) transistor and a P-channel metal oxide semiconductor (P-MOS) transistor In a complementary metal oxide semiconductor device, a gate of each transistor is divided into a single gate or a dual gate according to a doping method.
    [12] The single gate is formed by patterning polysilicon doped with a single conductive impurity. Thus, gate doping occurs prior to source and drain region formation. On the other hand, in the case of the dual gate, gate doping is performed in the process of injecting conductive impurities into the source and drain regions.
    [13] Referring to FIG. 1, in the method of forming a transistor of a semiconductor device having a dual gate according to the related art, a gate insulating layer 12 and a polysilicon layer 14 without conductive impurities are sequentially formed on a semiconductor substrate 10. . Subsequently, as shown in FIG. 2, the polysilicon layer 14 and the gate insulating film 12 are patterned, and as a result, a gate pattern composed of the gate insulating film pattern 12a and the polysilicon layer pattern 14a is formed. Conductive impurities are implanted into the entire surface of the resultant ion 16 to form first junction regions 18 on both sides of the gate pattern.
    [14] Referring to FIGS. 3 and 4, after the gate spacer 20 is formed on the side of the gate pattern, conductive impurities for forming the second junction region 22 deeper than the first junction region 18 on both sides of the gate pattern are formed. Ion implantation 24 is performed. At this time, since the ion implantation 24 is blocked in the region under the gate spacer 20 among the first junction regions 18, the first and second junction regions 18, respectively, on both sides of the gate pattern. LDD source and drain regions 28 and 29 are formed. In addition, conductive impurities for forming the second junction region 22 are ion-implanted in the gate pattern to form a material layer 26 (hereinafter referred to as an ion implantation layer) having a different property from the lower layer portion. In this way, the gate pattern which consists of the gate insulating film pattern 12a, the polysilicon layer pattern 14a, and the ion implantation layer 26 is formed.
    [15] In order to form the second junction region 22, after the ions are implanted, the resultant is heat-treated at high temperature to activate the implanted conductive impurities. As a result, as shown in FIG. 5, the conductive impurity injected into the ion implantation layer 26 diffuses to the entire polysilicon layer pattern 14a below. As a result, the gate pattern 32 which consists of the gate electrode 30 in which the conductive impurity was ion-implanted in the gate insulating film pattern 12a and the polysilicon layer pattern 14a is formed.
    [16] In the above-described conventional transistor forming method, the gate insulating layer pattern 12a is deteriorated or the thickness of the gate insulating layer is increased depending on the degree of heat treatment in the process of forming the gate electrode 30.
    [17] For example, when the heat treatment is performed at a high temperature, conductive impurities injected into the ion implantation layer 26 pass through the gate insulating film pattern 12a and diffuse to the active region below it. In this process, since the conductive impurities may remain in the gate insulating film pattern 12a, the characteristics of the gate insulating film pattern 12a, that is, the insulating properties, are changed, thereby reducing the reliability of the gate insulating film pattern 12a. In addition, since the conductive impurity diffused to the active region is combined with the conductive impurity for adjusting the threshold voltage pre-injected therein, the concentration of the conductive impurity for adjusting the threshold voltage is changed. As a result, the threshold voltage becomes nonuniform. In addition, since it is difficult to predict the degree of diffusion of the conductive impurities by the heat treatment, it may be difficult to set the conditions in the ion implantation process for adjusting the threshold voltage.
    [18] In addition, the conductive impurities injected into the lightly doped drain (LDD) region, that is, the first junction region 18, are excessively diffused, which is outside the predicted range. This result makes it difficult to set the ion implantation energy for forming the first junction region 18 or the ion implantation amount of the conductive impurity and the thickness of the gate spacer 20.
    [19] On the other hand, when the heat treatment temperature is lowered, the conductive impurities injected into the ion implantation layer 26 do not diffuse to the entire area of the polysilicon layer pattern 14a, thereby increasing the effective thickness of the gate insulating film. In addition, the characteristics of the transistor due to a poor bonding between the gate, the source, and the drain are reduced.
    [20] Therefore, the technical problem to be achieved by the present invention is to solve the problems of the prior art described above. It is to provide a method of forming a transistor that can be prevented from reaching the substrate.
    [1] 1 to 5 are cross-sectional views showing a transistor forming method according to the prior art step by step.
    [2] 6 to 11 are cross-sectional views illustrating a method of forming a transistor according to the present invention step by step.
    [3] <Code Description of Main Parts of Drawing>
    [4] 40: substrate. 42: insulating film.
    [5] 44, 48: First and second material layers. 44a, 48a: first and second ion implantation material layers.
    [6] 46, 50, 52 and 58: ion implantation.
    [7] 54, 60: first and second junction regions. 56: gate spacer.
    [8] 62: LDD junction area.
    [9] 64: gate electrode.
    [21] In order to achieve the above technical problem, the present invention sequentially forms a material layer doped with a nitrogen doped material and a conductive impurity on the gate insulating film, and then patterned to form a gate pattern, the ion implantation on the entire surface And forming a source and a drain region, and then heat treating the resultant to diffuse the conductive impurity into the nitrogen-doped material layer, thereby doping the entire region of the gate electrode with the conductive impurity. do.
    [22] In this process, the nitrogen-doped material layer forms a material layer on the gate insulating film, and then nitrogen is added to the material layer by a method of annealing the resultant in a nitrogen atmosphere or by treating with a plasma containing nitrogen. Formed by doping. In this case, the material layer is a polysilicon layer, and ammonia (NH 3 ) gas is used as the nitrogen-containing source gas used for nitrogen doping. Nitrogen doping is preferably performed at a thickness of about 5 to 900 kPa when the material layer is formed to a thickness of about 10 to 1,000 kPa.
    [23] After the nitrogen doping, the resultant is heat-treated using a furnace or rapid thermal processing (RTP).
    [24] The conductive impurity doped material layer is formed by forming an undoped material layer on the nitrogen doped material layer and then ion implanting conductive impurity on the entire surface. In this case, the material layer is formed of a polysilicon layer, and the conductive impurity depends on whether the gate to be formed belongs to a P-MOS transistor or an N-MOS transistor. For example, in the case of belonging to the P-MOS transistor, it is preferable to use P-type, i.e., trivalent impurity, as the conductive impurity.
    [25] The material layer into which the conductive impurity is injected is formed to a thickness of about 10 to 2,000 kPa, and after the conductive impurity is injected, heat treatment is performed for about 1 to 30 seconds at about 900 ° C to 1,200 ° C by RTP method. This heat treatment condition is equally applied to the heat treatment performed after the source drain region is formed.
    [26] As described above, in the process of forming the gate electrode, the nitrogen doped material layer is formed directly on the gate insulating layer. In this way, even if the conductive impurity doped in the upper layer of the gate in the subsequent heat treatment process is diffused to the lower layer portion, it is possible to prevent the diffusion through the gate insulating film to the substrate, and also prevent the effect of increasing the thickness of the gate insulating film.
    [27] Hereinafter, a method of forming a transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following, the thicknesses of the layers or regions shown in the drawings are exaggerated for clarity. In the drawings, like reference numerals refer to like elements.
    [28] Referring to FIG. 6, an insulating film 42 and a first material layer 44 are sequentially formed on the substrate 40. The first material layer 44 is formed of a polysilicon layer. At this time, the first material layer 44 is preferably formed to a thickness of about 10 ~ 1,000Å. Subsequently, nitrogen (N) is implanted into the first material layer 44 to be doped (46). At this time, the first material layer 44 is preferably doped to a thickness of about 5 ~ 900∼. Therefore, the ion implantation is preferably performed such that the nitrogen ion concentration in the first material layer 44 is about 1.0 × 10 18 to 1.0 × 10 22 (ions / cm 3). Nitrogen is injected into the first material layer 44 to anneal the first material layer 44 under an ammonia (NH 3 ) gas atmosphere, or to place the first material layer 44 under an ammonia plasma atmosphere. Can also be used. After ion implantation of nitrogen into the first material layer 44, the resultant is heat-treated using a furnace or RTP method.
    [29] Referring to FIG. 7, a second material layer 48 is formed on the first material layer 44a (hereinafter, referred to as a 'first ion implantation material layer') into which nitrogen ions are implanted. In this way, a gate stack including the insulating layer 42, the first ion implantation material layer 44a, and the second material layer 48 is formed on the substrate 40. The second material layer 48 is preferably formed of a polysilicon layer. At this time, the second material layer 48 is preferably formed to a thickness of about 10 ~ 2,000Å. Subsequently, conductive impurities are implanted into the second material layer 48 (50). At this time, the conductive impurities are preferably ion implanted at about 1.0 × 10 19 to 1.0 × 10 22 (ions / cm 3).
    [30] Thereafter, the second material layer 48 is heat treated at 900 to 1,200 ° C. for 1 to 30 seconds using an RTP method.
    [31] As a result, as shown in FIG. 8, the conductive impurity is diffused to the first ion implantation material layer 44a so that a portion of the first ion implantation material layer 44a is implanted with a conductive layer ( 48a, hereinafter referred to as 'second ion implantation material layer'. In this way, the thickness of the first ion implantation material layer 44a is thinner than the first material layer 44, while the thickness of the second ion implantation material layer 48a is the second material layer 48. Thicker than Subsequently, when the second ion implantation material layer 48a and the first ion implantation material layer 44a are sequentially patterned, as shown in FIG. 9, the gate insulating film 42a and the first ion implantation material layer 44a are illustrated. ) And a second gate implant layer 48a is formed on the substrate 40.
    [32] Referring to FIG. 9, conductive impurities are ion implanted into the entire surface of the resultant product in which the gate pattern is formed (52). As a result, first junction regions 54 are formed on both sides of the gate pattern. In this case, the conductive impurities may vary depending on the type of transistor to be formed. For example, when the transistor to be formed is a P-MOS type, it is preferable to use P-type, that is, trivalent conductive impurity, as the conductive impurity. When the transistor is N-MOS type, an N-type, that is, a pentavalent conductive impurity is used. It is desirable to.
    [33] Referring to FIG. 10, a gate spacer 56 is formed on side surfaces of the gate pattern. A conductive impurity 58 is implanted into the entire surface of the resultant product in which the gate spacer 56 is formed to form a second deeper junction region 60 in the first junction region 54. It is preferable that the conductive impurity used to form the second junction region 60 also has the same properties as those used to form the first junction region 54. In forming the second junction region 60, the gate spacer 56 serves as a mask. Therefore, conductive impurities used to form the second junction region 60 are not implanted in the region formed under the gate spacer 56 in the first junction region 54. As a result, LDD type junction regions 62 formed of a part of the first junction region 54 and the second junction region 60 are formed on both sides of the gate pattern. One of the LDD type junction regions 62 is a source region and the other is a drain region.
    [34] Subsequently, the resultant in which the LDD type junction region 62 is formed is heat-treated at 900 ° C to 1,200 ° C for 1 to 30 seconds. In this process, the conductive impurity implanted into the second ion implantation material layer 48a during the formation of the second junction region 60 extends into the first ion implantation material layer 44a. However, the diffusion of the conductive impurity through the gate insulating layer 42a by the nitrogen injected into the first ion implantation material layer 44a is prevented. As a result, the first ion implantation material layer 44a becomes thinner while the second ion implantation material layer 48a becomes thicker. Preferably, the conductive impurity may be diffused to the entire area of the first ion implantation material layer 44a within a range not exceeding the gate insulating layer 42a. By doing so, all of the first ion implantation material layer 44a is included in the second ion implantation material layer 48a.
    [35] As a result, as shown in Fig. 11, a gate electrode 64 is formed on the gate insulating film 42a. The gate electrode 64 is the second ion implantation material layer 48a.
    [36] While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, a person of ordinary skill in the art may not partially make the first ion implantation material layer 44a the second ion implantation material layer 48a, but may leave a part thereof. have. In other words, the gate pattern may include the gate insulating layer 42a, the second ion implantation material layer 48a, and the first ion implantation material layer 44a having a much thinner thickness. In addition, the first material layer 44 or the second material layer 48 may be formed of a material layer other than the polysilicon layer. In addition, a heat treatment performed after ion implanting conductive impurities into the second material layer 48 may be performed by a heat treatment method other than the RTP method.
    [37] As described above, according to the present invention, a heat treatment and a source are sequentially formed on a gate insulating film, followed by sequentially forming a second material layer ion-implanted with a conductive impurity selected according to a region where a transistor is formed. A heat treatment performed after the ion implantation of the conductive material into the second material layer is further performed at the time of drain ion implantation. The conductive impurity implanted into the second material layer is diffused into the first material layer. In this case, the conductive impurities are prevented from penetrating through the gate insulating layer by the nitrogen injected into the first material layer to the active region of the substrate. In this way, while the thickness of the depletion layer is minimized in the gate electrode, that is, while the effect of increasing the thickness of the gate insulating layer is minimized, the conductive impurities implanted in the gate electrode diffuse through the gate insulating layer and diffuse into the active region of the substrate. This can prevent the transistor from deteriorating.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] Forming a gate stack including a nitrogen-doped first material layer sequentially formed on the substrate and a second material layer doped with conductive impurities;
    Firstly increasing the thickness of the second material layer in the gate stack;
    Patterning a resultant material having an increased thickness of the second material layer to form a gate pattern;
    Forming a first junction region in an active region of the substrate in contact with the gate pattern;
    Forming a gate spacer on side surfaces of the gate pattern;
    Forming a second junction region deeper in the first junction region while ion implanting conductive impurities in the gate pattern; And
    And further increasing the thickness of the second material layer in the gate stack.
    [2" claim-type="Currently amended] The method of claim 1, wherein the thickness of the second material layer is first increased by heat treating the gate stack at about 900 ° C. to about 1,200 ° C. for 1 to 30 seconds.
    [3" claim-type="Currently amended] The method of claim 1, wherein the second junction region is formed by heat-treating the resultant having the second junction region at about 900 ° C. to 1,200 ° C. for 1 to 30 seconds. .
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    同族专利:
    公开号 | 公开日
    KR100640572B1|2006-10-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-09-20|Application filed by 윤종용, 삼성전자 주식회사
    2000-09-20|Priority to KR1020000055202A
    2002-03-27|Publication of KR20020022421A
    2006-10-31|Application granted
    2006-10-31|Publication of KR100640572B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000055202A|KR100640572B1|2000-09-20|2000-09-20|Method for forming a transistor|
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