• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a plasma display panel driving apparatus capable of reducing the number of data lines between an output data portion included in an address driver and a data drive driver integrated circuit. The driving apparatus of the plasma display panel according to the present invention includes an input data portion for bit-extending predetermined bit data supplied from an input line into a predetermined bit string, a plurality of drive driving integrated circuits for driving an address electrode line, and an input data portion. At least one output data unit for converting the address data extended in a predetermined bit string into a format suitable for a display panel so as to be supplied to the address electrode lines, and for selecting any one of output signals of the output data units. And a demultiplexer and at least one de flip-flop for supplying a signal of the demultiplexer to any one of a plurality of drive driver integrated circuits. According to the present invention, a demultiplexer and a D flip-flop may be provided between the output data unit and the data drive driver integrated circuit, thereby reducing the number of data lines by half.
    公开号:KR20020004513A
    申请号:KR1020000038470
    申请日:2000-07-06
    公开日:2002-01-16
    发明作者:심수석
    申请人:구자홍；엘지전자주식회사；
    IPC主号:
    专利说明:

    Apparatus of Driving Plasma Display Panel
    [17] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a plasma display panel, and more particularly to a driving device of a plasma display panel to reduce the number of data lines between an output data unit included in an address driver and a data drive driving integrated circuit.
    [18] Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.
    [19] 1 is a perspective view showing a conventional AC surface discharge PDP.
    [20] Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 12Y and the common sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.
    [21] Referring to FIG. 2, a conventional AC surface discharge type PDP driving apparatus includes m / n discharge cells 1 having scan / sustain electrode lines Y1 to Ym, common sustain electrode lines Z1 to Zm, and A PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the scan / sustain electrode lines Y1 to Ym, and a common sustain; The common sustain driver 34 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3 and Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 36A and 36B for dividing and driving .X4, ..., Xn-2, Xn are provided. The scan / sustain driver 32 sequentially supplies scan pulses and sustain pulses to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n The discharge in each of the four discharge cells 1 is continued. The common sustain driver 34 supplies a sustain pulse to all of the common sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply address data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies address data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies even-numbered address electrode lines ( Address data is supplied to X2, X4, ..., Xn-2, Xn).
    [22] The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different discharge times in order to express gray levels of an image. Each subfield is further divided into a reset period for uniformly discharging the discharge, an address period for selecting the discharge cells, and a sustain period for expressing the gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period increases at a rate of 2n (n = 0,1,2,3,4,5,6,7) in each subfield. do.
    [23] The address driver 36 of the PDP includes a plurality of input data units 40, an output data unit 42, and a data drive integrated circuit (IC) 44 as shown in FIG.
    [24] Referring to FIG. 3, the conventional address driver 36 shifts address data of a predetermined bit (J bit) left or right input from an address data supply unit (not shown) to generate address data of a predetermined bit (J × k). Input data portions 40 for outputting and output data portions for converting address data of a predetermined bit (J × k) input from the input data portions 40 into a predetermined format so that the data can be supplied to the data drive ICs 44. 42 and data drive ICs 44 for supplying address data supplied from the output data sections 42 to the address electrode lines X.
    [25] In detail, the input data units 40 receive the address data of a predetermined bit (J bit) from the address data supply unit. Normally, the predetermined bit (J bit) supplied from the address data supply unit to the input data units 40 is 4 bits. After the address data of the predetermined bit (J bit) is supplied from the address data supply unit to the input data units 40, a clock signal is input to the first control line. The input data units 40 shift left or right predetermined bit (J bit) address data supplied from the address data supply unit in synchronization with the clock signal K input to the first control line. This process is repeated to generate address data of a predetermined bit (JxK bits) in the input data units 40. Usually, the address data of the predetermined bit (JxK) generated in the input data sections 40 is 64 bits. After the 64-bit address data is generated in the input data parts 40, the clock signal is input to the second control line. When the clock signal is input to the second control line, the address data generated by the input data units 40 is supplied to the output data units 42. The output data sections 42 convert the address data into a predetermined format that can be supplied to the data drive ICs 44 and store them. Thereafter, the output data parts 42 are shifted left or right and supply address data to the data drive ICs 44 by 4 bits through the data line DL. The data drive ICs 44 are supplied with clock signals to the third control line after 64-bit address data is supplied. When the clock signal is supplied to the third control line, the data drive ICs 44 supply address data to the address electrode lines X.
    [26] However, such a conventional address driver uses a plurality of data lines DL to supply data from the output data unit 40 to the data drive IC 44. The plurality of data lines DL must be kept at a predetermined interval so as not to be electrically interrupted. Therefore, the address driving circuit board cannot be reduced below a predetermined size. In particular, as the PDP becomes higher in resolution, the number of data lines DL increases.
    [27] Accordingly, an object of the present invention is to provide a driving apparatus of a plasma display panel which can reduce the number of data lines between an output data portion and a data drive driving integrated circuit included in an address driver.
    [1] 1 is a perspective view showing a discharge cell structure of a conventional AC surface discharge PDP.
    [2] FIG. 2 is a block diagram illustrating a PDP and a driving unit thereof in which discharge cells shown in FIG. 1 are arranged in a matrix form; FIG.
    [3] 3 is a view showing a conventional address driver shown in FIG.
    [4] 4 is a diagram showing an address driver of the present invention.
    [5] <Description of Symbols for Main Parts of Drawings>
    [6] 1: discharge cell 10: upper substrate
    [7] 12Z: common sustain electrode 12Y: scan / sustain electrode
    [8] 14,22 dielectric layer 16: protective film
    [9] 18: lower substrate 20X: address electrode
    [10] 24: partition 26: phosphor
    [11] 30: PDP 32: scan / sustain drive unit
    [12] 34: common sustain driver 36A, 36B: address driver
    [13] 40,46: input data section 42,48,49: output data section
    [14] 44,50,51: Data Drive Driver Integrated Circuit
    [15] 52: demultiplexer 54,55: D flip-flop
    [16] 56: inverter 58: selection signal generator
    [28] In order to achieve the above object, a driving apparatus of a plasma display panel according to the present invention includes an input data unit for bit-extending predetermined bit data supplied from an input line into a predetermined bit string, and a plurality of drive driving integrated devices for driving an address electrode line. A circuit, at least one output data portion for converting the address data extended in a predetermined bit string from the input data portion into a format suitable for a display panel so as to be supplied to the address electrode line, and among the output signals of the output data portions A demultiplexer for selecting any one and at least one de- flip-flop for supplying a signal of the demultiplexer to any one of a plurality of drive driver integrated circuits.
    [29] Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.
    [30] Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG. 4.
    [31] 4 is a diagram illustrating an address driver of the present invention.
    [32] Referring to FIG. 4, the address driver 36 of the present invention shifts the address data of a predetermined bit (J bit) to the left or right from the address data driver to generate the address data of the predetermined bit (J × K). Output data sections for converting the input data sections 46 and address data of a predetermined bit (J × K) input from the input data sections 46 into a predetermined format so that they can be supplied to the data drive ICs 50 and 51. (48,49), demultiplexers 52 for connecting the output lines of the two output data parts 48,49 with one data line DL, and one data line DL, D flip-flops 54 and 55 and D flip-off for supplying address data output from the two output data sections 48 and 49 to the two data drive ICs 50 and 51. The address data supplied from the flops 54, 55 Data drive ICs 50 and 51 for supplying the address electrode lines X are provided.
    [33] The demultiplexers 52 are either one of the address data input from the two output data parts 48 and 49 in response to the signal of the negative logic 0 or the positive logic 1 input from the selection signal generator 58. Is supplied to the data line DL. The D flip-flops 54 and 55 receive two pieces of address data supplied to the data line DL in response to a negative or positive logic signal input from the selection signal generator 58 and the inverter 56. One of the drive ICs 50 and 51 is supplied.
    [34] The operation process will be described in detail. First, the input data units 46 are supplied with address data of a predetermined bit (J bit) from the address data supply unit. Normally, the predetermined bit (J bit) supplied from the address data supply part to the input data parts 46 is 4 bits. After the address data of the predetermined bit (J bit) is supplied from the address data supply unit to the input data units 46, the clock signal k is input to the first control line. The input data units 46 shift left or right the address data of a predetermined bit J bit supplied from the address data supply unit in synchronization with the clock signal k input to the first control line. This process is repeated to generate address data of a predetermined bit (JxK bits) in the input data units 46. Usually, the address data of the predetermined bit (JxK) generated in the input data sections 46 is 64 bits. After 64-bit address data is generated in the input data units 46, a clock signal is input to the second control line. When the clock signal is input to the second control line, address data generated by the input data units 46 is supplied to the output data units 48 and 49. The output data parts 48 and 49 convert and store address data in a predetermined format so that the address data can be supplied to the data drive ICs 50 and 51. The negative logic signal is then supplied from the selection signal generator 58 to the demultiplexers 52, the inverter 56, and the second D flip-flops 55. The demultiplexers 52 supply address data stored in the first output data units 48 to the data lines DL by 4 bits when a negative logic signal is input. The negative logic signal supplied from the selection signal generator 58 to the inverter 56 is inverted into a positive logic signal and supplied to the first D flip-flops 54. That is, a positive logic signal is input to the first D flip-flops 54, and a negative logic signal is input to the second D flip-flops 55. Thus, the 4-bit address data supplied to the data lines DL is supplied to the first data drive ICs 50 through the first D flip-flops 54. After four bits of address data are supplied to the first data drive ICs 50, a positive logic signal from the selection signal generator 58 is demultiplexers 52, the second D flip-flops 55, and an inverter. Supplied to 56. When the positive multiplexer 52 receives a positive logic signal, the demultiplexers 52 supply address data stored in the second output data units 49 to the data lines DL by 4 bits. The positive logic signal supplied from the selection signal generator 58 to the inverter 56 is inverted into a negative logic signal and supplied to the first D flip-flops 54. That is, a negative logic signal is input to the first D flip-flops 54, and a positive logic signal is input to the second D flip-flops 55. Thus, 4-bit address data supplied to the data lines DL is supplied to the second data drive ICs 51 through the second D flip-flops 55. Through this process, 64-bit address data is supplied to the data drive ICs 50 and 51. After the 64-bit address data is supplied to the data drive ICs 50 and 51, the clock signal is supplied to the third control line. When the clock signal is supplied to the third control line, the data drive ICs 50 and 51 supply 64-bit address data to the address electrode lines X.
    [35] As described above, according to the driving apparatus of the plasma display panel according to the present invention, the number of data lines can be reduced by half by providing a demultiplexer and a D flip-flop between the output data unit and the data drive driving integrated circuit. Therefore, the size of the address driving circuit board can be minimized.
    [36] Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] A plasma display panel comprising an address driver circuit board for supplying data to an address electrode line in a display panel.
    An input data section for bit-extending the predetermined bit data supplied from the input line into a predetermined bit string;
    A plurality of drive driver integrated circuits for driving the address electrode lines;
    At least one output data section for receiving the address data extended in a predetermined bit string from the input data section and converting the address data into a format suitable for the display panel so as to be supplied to the address electrode line;
    A demultiplexer for selecting any one of output signals of the output data units;
    And at least one de-flip-flop for supplying a signal of the demultiplexer to any one of the plurality of drive driver integrated circuits.
    [2" claim-type="Currently amended] The method of claim 1,
    And a selection signal generator for controlling the operation of the multiplexer and separately driving the de-flip-flop into even-numbered and odd-numbered numbers.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-07-06|Application filed by 구자홍, 엘지전자주식회사
    2000-07-06|Priority to KR1020000038470A
    2000-07-06|Priority claimed from KR1020000038470A
    2002-01-16|Publication of KR20020004513A
    2002-07-02|Application granted
    2002-07-02|Publication of KR100342832B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000038470A|KR100342832B1|2000-07-06|Apparatus of Driving Plasma Display Panel|
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