• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A large area dummy pattern DL is formed in the lower layer of the target T2 region formed in the scribe region SR of the wafer. In addition, the lower layer is formed in a large area between the patterns of the patterns (active regions L1, L2, L3, gate electrode 17, etc.) serving as elements of the product region PR and the scribe region SR. The area dummy pattern and the small area dummy pattern Ds2 in the upper layer are disposed. At this time, the small area dummy pattern Ds2 of the upper layer is formed by half-pitch shifting with respect to the small area dummy pattern Ds of the lower layer.
    公开号:KR20010081954A
    申请号:KR1020000066669
    申请日:2000-11-10
    公开日:2001-08-29
    发明作者:우치야마히로유키；챠키하라히라쿠；이치세테루히사；카미나가미치모토
    申请人:가나이 쓰토무；가부시키가이샤 히타치세이사쿠쇼；스즈키 진이치로；가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈；
    IPC主号:
    专利说明:

    Semiconductor device and process for manufacturing the same
    [29] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly, to a technology effective for applying to a semiconductor device having a step of planarizing a surface by using a chemical mechanical polishing (CMP) method.
    [30] In semiconductor devices such as DRAM (Dynamic Random Access Memory), the demand for miniaturization and high integration is well known in recent years, and the multilayer structure such as multilayer wiring is inevitable from the demand for miniaturization of semiconductor devices. Unevenness is formed on the surface of the upper layer by reflecting the unevenness of the underlying member.If photolithography is carried out in the presence of unevenness on the surface, a sufficient depth of focus in the exposure process is not sufficiently taken, which causes a poor resolution. , The CMP method is used to planarize the surface and to improve the photolithography margin of the member formed on the surface.
    [31] The CMP method is also used to form the device isolation region. In the LOCOS (Local Oxidation of Silicon) method, which has been widely used in the past, it is difficult to attain a certain size or more because of the presence of a buzz beak. Thus, shallow grooves are formed in the main surface of the semiconductor substrate, and the shallow grooves are filled with the silicon oxide film to remove the silicon oxide film in the regions other than the grooves by the CMP method to form shallow groove element isolation. In the shallow groove element separation, the peripheral portion of the element isolation region is sharply formed, so that the peripheral portion can also be effectively used as the element portion, whereby miniaturization can be easily achieved.
    [32] By the way, in the polishing by the CMP method, the surface irregularities cannot be completely removed. If irregularities exist on the surface to be polished, the hysteresis of the irregularities on the surface of the surface to be polished remains to some extent. Moreover, when the part which is easy to be polished and the part which is hard to be polished are mixed on a to-be-polished surface, dishing (dentation by grinding | polishing) generate | occur | produces in the part which is easy to grind. From the polishing characteristics of the CMP method, the history and dishing of these unevennesses occur remarkably when the area of the unevenness or the portion which is easily polished is large. In other words, in the polishing by the CMP method, the fine unevenness can be flattened relatively well, but the undulation (global relief) over a large area is not sufficient for the repetition of a large pattern (usually a order of several micrometers or more). It remains, and it becomes difficult to completely planarize a surface.
    [33] Therefore, a countermeasure for disposing a dummy pattern in a large pattern or an area having a large pattern interval has been proposed. A pattern pattern is made small by a dummy pattern, and it is a method of suppressing a wide area | region (global) dish or ups and downs as mentioned above. For example, Japanese Unexamined Patent Application Publication No. 10-335333 (published US. Serial No. 09/050416 98.3.31) discloses a technique for arranging a dummy pattern in an area having a large pattern interval and improving the surface flatness of the insulating film filling the pattern. Is disclosed.
    [34] As described above, by disposing a dummy pattern in a region having a large distance between patterns to reduce the pattern spacing, it is possible to take measures for dishing (depression) or undulation in a large area. Since the dishing area is so large that the recessed position of the center portion is low, it is possible to arrange the dummy pattern to reduce the area where dishing occurs and to reduce the amount of depression relatively.
    [35] However, no matter how small the pattern interval, it is impossible to completely eliminate dishing. If the flat screen in question is a single layer, the amount of depression is greatly improved compared to the dishing of the large area portion, but in the case where a plurality of flattening layers are laminated, dishing (depression) overlaps due to the arrangement of the patterns, There is a problem in that dishing of a large portion occurs. In such a case, problems such as a decrease in the focus margin in the photolithography process in the upper layer and an increase in the amount of overetch in the etching process occur, resulting in a decrease in yield.
    [36] In addition, a target for alignment of an exposure apparatus (stepper or the like) used in photolithography is formed in a region where devices made of products such as scribe regions are not formed. In the vicinity of the target, a dummy pattern cannot be disposed in order to recognize the pattern. The area of the target usually has a size of a micrometer order or more. Therefore, dishing occurs as described above unless the dummy pattern is disposed in such a large (large area) pattern area. Conventionally, such a large area pattern is not particularly problematic since it is formed in the scribe region and not in the product region. However, in the situation where the effect of dishing in the scribe area extends to the product area, and the depth of focus margin in the exposure process becomes strict as the progress of miniaturization progresses, the flatness in the product area (particularly the peripheral part) is a problem. It is supposed to generate.
    [37] An object of the present invention is to suppress dishing on a plurality of stacked flat screens.
    [38] It is also an object of the present invention to improve surface flatness in a large area pattern area for optically detecting a target or the like.
    [39] Moreover, the objective of this invention is improving the flatness of large area patterns, such as a flat screen or a target laminated | stacked two or more, and improving the processing margin in a photolithography process and an etching process.
    [40] The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.
    [1] 1 is a plan view showing a silicon wafer used for producing a semiconductor device of one embodiment of the present invention;
    [2] 2 is an enlarged plan view showing a chip portion of a wafer of an embodiment;
    [3] 3 is a plan view showing an end region of a chip including a region of scribe brine;
    [4] 4 is an enlarged plan view showing a product region of a chip;
    [5] 5 (a) and 5 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [6] 6 (a) and 6 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [7] 7 (a) and 7 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [8] 8 (a) and 8 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [9] 9 (a) and 9 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [10] 10 (a) and 10 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [11] 11A and 11B are cross-sectional views each showing an example of a method of manufacturing a semiconductor device of the embodiment in the order of steps;
    [12] 12 (a) and 12 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [13] 13 (a) and 13 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [14] 14 (a) and 14 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [15] 15 (a) and 15 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [16] 16 (a) and 16 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [17] 17 is a plan view showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [18] 18 is an enlarged plan view of FIG. 17;
    [19] 19 (a) and 19 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [20] 20 (a) and 20 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [21] 21 (a) and 21 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [22] 22A and 22B are cross-sectional views each showing an example of a method of manufacturing a semiconductor device of the embodiment in the order of steps;
    [23] 23 (a) and 23 (b) are cross-sectional views each showing an example of the method of manufacturing the semiconductor device of the embodiment in the order of steps;
    [24] 24 is a plan view showing an example of a method of manufacturing a semiconductor device of the embodiment in process order;
    [25] 25 is an enlarged plan view illustrating another example of the semiconductor device of the embodiment;
    [26] 26 is an enlarged plan view illustrating another example of the semiconductor device of the embodiment;
    [27] 27 is an enlarged plan view illustrating still another example of the semiconductor device of the embodiment;
    [28] 28 is an enlarged plan view showing still another example of the semiconductor device of the embodiment.
    [41] Among the inventions disclosed herein, an outline of representative ones will be briefly described as follows.
    [42] The semiconductor device of the present invention includes a semiconductor substrate having a semiconductor element formed on a main surface thereof, a first pattern including a dummy pattern formed on any one surface of the main surface or the main surface, and an upper layer formed on the first pattern. It has a 2nd pattern including the pattern to become, and the pattern used as the object of optical pattern recognition is formed in the planar shape of a dummy pattern. According to such a semiconductor device, a dummy pattern is disposed under a pattern which is an object of optical pattern recognition, and the fall of global flatness in this pattern region can be suppressed.
    [43] The first pattern may include another dummy pattern having an area smaller than that of the dummy pattern. The dummy pattern and the other dummy pattern may be formed in the scribe area. In addition, other dummy patterns may be formed in the product region and the scribe region.
    [44] In addition, the dummy pattern is formed with an area larger than the pattern disposition prohibition area around the pattern to be the object of optical pattern recognition. Thereby, the fall of the recognition rate of the optical pattern recognition of the said pattern can be prevented.
    [45] In addition, the first pattern includes another dummy pattern having the same processing dimension as the design rule of the semiconductor element and having a smaller area than the dummy pattern, and no other dummy pattern is disposed in the pattern disposition prohibition area. As a result, a small area dummy pattern is disposed in the vicinity of the pattern that is the object of optical pattern recognition, the flatness of those areas is improved, and the small area dummy pattern is prohibited in the vicinity of the pattern, thereby preventing optical pattern recognition. The fall of the pattern recognition rate of the pattern made into the object can be prevented.
    [46] The dummy pattern is formed in the scribe region of the semiconductor wafer, and the other dummy pattern is formed in the product region and the scribe region of the semiconductor wafer. This improves the flatness not only in the product region but also in the scribe region, and improves the flatness near the boundary between the product region and the scribe region, thereby contributing to the improvement of the product yield.
    [47] A semiconductor device of the present invention is a semiconductor device having a semiconductor substrate on which a semiconductor element is formed on a main surface, a first pattern formed on any one surface on a main surface or a main surface, and a second pattern formed on an upper layer of the first pattern. The first dummy pattern is included, and the second pattern includes a second dummy pattern having a pattern pitch and a pattern width having the same design dimensions as the first dummy pattern, and the second dummy pattern is located in the planar position. It is formed on the space of. At this time, one short side of the second dummy pattern is formed to overlap the first dummy pattern in the planar position, or the pitch is at the planar position between the first dummy pattern and the second dummy pattern. It is shifted by half distance of. According to such a semiconductor device, dishing occurs between the patterns of the first small-area dummy pattern, but a second small-area dummy pattern is formed on the upper portion of the portion where the dishing occurs, and the dishing is formed between the second small-area dummy patterns. Overlapping can be prevented. For this reason, superposition of the dishing between upper and lower layers can be suppressed, and flatness can be improved.
    [48] In the semiconductor device, the first pattern further includes another dummy pattern having a larger area than the first dummy pattern, and the second pattern further includes a pattern that is an object of optical pattern recognition. The target pattern may be formed to be contained in the planar shape of another dummy pattern. The other dummy pattern is formed with an area larger than the pattern disposition prohibition area around the pattern, which is the object of optical pattern recognition, and the first dummy pattern is not disposed in the pattern disposition prohibition area. Another dummy pattern may be formed in the scribe region of the semiconductor wafer, and the first and second dummy patterns may be formed in the product region and the scribe region of the semiconductor wafer.
    [49] In any of the above semiconductor devices, the first pattern may be an active region pattern formed on the main surface, and the second pattern may be a pattern formed on the same layer as the gate electrode constituting the semiconductor element.
    [50] The method of manufacturing a semiconductor device of the present invention comprises the steps of (a) forming a first pattern including a dummy pattern on either the main surface of the semiconductor substrate or on the member layer on the main surface, and (b) the main surface on which the first pattern is formed. Depositing an insulating film on the patterned member in the upper or first pattern, polishing the insulating film to planarize the surface, and (c) a second pattern including a pattern to be subjected to optical pattern recognition on the upper surface of the flattened surface. It has a process of forming a pattern, and the pattern used as the object of optical pattern recognition is formed so that it may be contained in the planar shape of a dummy pattern.
    [51] In the above manufacturing method, a step of optically detecting a pattern to be an object of optical pattern recognition and aligning the semiconductor substrate can be provided.
    [52] In addition, the method of manufacturing a semiconductor device of the present invention includes the steps of (a) forming a first pattern including a dummy pattern on either the main surface of the semiconductor substrate or on the member layer on the main surface, and (b) the first pattern. Forming a second pattern including a pattern that is an object of optical pattern recognition on the upper layer of the substrate; and (c) optically detecting a pattern that is an object of optical pattern recognition and aligning the semiconductor substrate. The pattern to be subjected to the optical pattern recognition is formed to be contained in the planar shape of the dummy pattern.
    [53] In any manufacturing method, the dummy pattern can be formed with an area larger than the pattern disposition prohibition area around the pattern, which is the object of optical pattern recognition.
    [54] The first pattern further includes a first dummy pattern, and the second pattern further includes a second dummy pattern having a pattern pitch and a pattern width having the same design dimensions as the first dummy pattern. It may be formed on the space of the first dummy pattern in the planar position.
    [55] In addition, any short side of the second dummy pattern is formed so as to overlap the first dummy pattern at its planar position, or the pitch of the first dummy pattern and the second dummy pattern is at its planar position. It can be formed to shift by half the distance.
    [56] In addition, the dummy pattern can be formed in the scribe region of the semiconductor wafer, and the first and second dummy patterns can be formed in the product region and the scribe region of the semiconductor wafer.
    [57] The member to which the first pattern is transferred may be a semiconductor substrate, and the member formed by transferring the second pattern may be a gate electrode.
    [58] By the manufacturing method of these semiconductor devices, the above-mentioned semiconductor device can be manufactured.
    [59] (Detailed Description of the Preferred Embodiments)
    [60] EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing. In addition, in all the drawings for demonstrating embodiment, the same code | symbol is attached | subjected to the member which has the same function, and the repeated description is abbreviate | omitted.
    [61] 1 is a plan view showing a silicon wafer used for manufacturing a semiconductor device in the present embodiment. In the wafer 1w of single crystal silicon, there is a notch 1n, which is a target of the surface index of the wafer 1w. The chip 1c is formed in the wafer 1w. The chip 1c is formed in the effective processing area in the wafer 1w, and the chip area 1g deviated from the effective processing area is not used.
    [62] 2 is an enlarged plan view of the chip 1c of the wafer 1w. The chip 1c is later scribed with scribe brine SL and divided. In the process described below, each process is performed in the state of the wafer 1w, and it is in the final process that the chips are divided into the chips 1c.
    [63] In the present embodiment, a typical DRAM chip 1c is illustrated. Other devices, such as logic products such as CPUs, memory devices such as static random access memory (SRAM), batch erase type electrically rewritable memory (so-called Flash EEPROM: Electrical Erasable Read Only Memory), logic circuits and memory devices The system LSI mixed in the above may be used. The memory cell array MA, the direct peripheral circuit PCd, and the indirect peripheral circuit PCi are formed in the chip 1c. A memory cell of a DRAM is formed in the memory cell array MA. A direct peripheral circuit PCd is formed around the memory cell MA. An indirect peripheral circuit PCi is formed in the central region of the chip 1c.
    [64] 3 is a plan view showing an end region of the chip 1c including the region of the scribe brine SL. In FIG. 3, the state of the step in which the element isolation area | region was formed in the semiconductor substrate 1 (wafer 1w and the chip 1c) is shown. The product area PR is other than the scribe area SR.
    [65] In the scribe region SR, a target pattern T1, a large area dummy pattern DL, and a small area dummy pattern Ds are formed at the same time when the device isolation region is formed. In the scribe area SR, other elements for TEG (Test Equipment Group) are formed, but are omitted in the drawing. The target pattern T1 is a pattern formed simultaneously in the process of forming the element isolation region pattern, and is used for alignment in the exposure process when forming the gate electrode pattern described later. That is, it is used as a target for position detection at the time of mask matching of a gate electrode pattern. In the exposure apparatus, for example, the target is optically pattern-recognized to align the mask with respect to the wafer, and then the photoresist film is exposed.
    [66] The large area dummy pattern DL and the small area dummy pattern Ds are also patterns simultaneously formed in the process of forming the device isolation region pattern. On the large area dummy pattern DL, a target pattern T2 formed simultaneously with the gate electrode pattern is formed. The target pattern T2 is also used for alignment in the exposure step when forming an upper pattern, for example, a wiring pattern or a connection hole pattern. By arranging the large area dummy pattern DL, dishing of the area of the target pattern is prevented, the recognition rate of the target pattern is improved, and micromachining is advantageously performed. Conventionally, dummy patterns are not disposed around the target pattern, and thus surface flatness around the target pattern has been hindered. However, by placing a large area dummy pattern DL under the target pattern, the flatness is improved. This is to improve the recognition rate. In addition, the large area dummy pattern DL is formed larger than the target pattern so as to contain the target pattern. That is, since a large area dummy pattern DL exists under the target pattern region that is optically recognized, the recognition rate of the target pattern can be improved by preventing dishing. In the vicinity of the target pattern, there is an area where the arrangement of all patterns is prohibited so as not to impair the pattern recognition of the target. The large area dummy pattern DL is formed with an area equal to or larger than the pattern disposition prohibition area. For this reason, the large area dummy pattern DL is not recognized as a pattern by the exposure apparatus, and the recognition rate of the target patterns T1 and T2 is not lowered.
    [67] The small area dummy pattern Ds is formed in the scribe region SR and the product region PR. That is, it is formed in the whole surface of the wafer W. As shown in FIG. In this way, the small-area dummy pattern Ds is arranged in a region where the interval of the pattern which originally functions as an element is large. When the spacing between patterns serving as elements is wide, and small-area dummy patterns Ds are not disposed between such wide patterns, dishing occurs between the patterns. Since the dishing has a larger depression between the patterns, the flatness is significantly impaired. The small area dummy pattern Ds is disposed in such a wide inter-pattern space to improve flatness. Since the pattern size and the inter-pattern space of the small-area dummy pattern Ds are formed in the order of almost the same order as the pattern constituting the element, the pattern interval is narrow and small dishing occurs according to the narrow pattern interval. In such a situation, the amount of depression can be greatly improved than when the dummy pattern is not arranged, and the flatness can be improved. The pattern size of the small area dummy pattern Ds is the same order as the element design rule, but an appropriate value is selected from the ease of photolithography and the effect on dishing suppression. When the element design rule is, for example, about 0.2 mu m, the pattern size of the small area dummy pattern Ds can also be set to about 0.2 mu m. However, when the KrF excimer laser is used as the exposure light source, it is necessary to use a resolution enhancement method using a Levenson Mask or the like. Therefore, prior to ease of mask preparation, the pattern size of the small-area dummy pattern Ds can be set to about 1 µm and the space between patterns can be about 0.4 µm. It goes without saying that other values can be selected from the request of the photolithography process. However, if the pattern size and the space between patterns are very large, dishing in the space between patterns is remarkable, which is not preferable.
    [68] In addition, the width of the scribe region SR is about 100 μm.
    [69] In FIG. 3, in addition to the small area dummy pattern Ds, an active region constituting an element is formed in the product region PR. In the present embodiment, an active region L1 forming a channel region of a metal insulator semiconductor field effect transistor (MISFET), an active region L2 for well grade, and an active region L3 for guard band feeding To illustrate. It goes without saying that other active regions may be formed. The above-described small area dummy pattern Ds is formed between the patterns of the active regions L1, L2, and L3. The same large area dummy pattern DL may also be formed in the product region PR.
    [70] 4 is an enlarged plan view showing a region including the active regions L1 and L2 of the product region PR. As described above, a plurality of small area dummy patterns Ds are disposed between the patterns of the active regions L1 and L2. As described above, the pattern size d1 of the small area dummy pattern Ds is about 1 mu m, and the pattern spacing S1 is about 0.4 mu m.
    [71] The small-area dummy pattern Ds is formed by automatically generating a pattern of the size in a lattice (grid) of a pattern pitch (1.4 µm in the present embodiment). At this time, the small area dummy pattern Ds is not generated in the portion where the active regions L1 and L2 constituting the element already exist at each lattice point. In other words, in the mask design apparatus, figure calculation is performed to expand a pattern of the active areas L1 and L2. This enlarged pattern region becomes the placement inhibiting region R1 of the small area dummy pattern Ds. Next, a small area dummy pattern Ds is generated at the remaining lattice points except the lattice in the placement prohibition area R1 among the lattice points in the figure calculation, and the generated small area dummy pattern Ds and Addition with the active areas L1, L2, and L3 is made as data for mask creation. In addition, the large area dummy pattern DL is provided with a prohibition area R1 of the small area dummy pattern Ds around the large area dummy pattern DL. For this reason, the large area dummy pattern DL is also included in the pattern to expand. In this way, the mask pattern in which the dummy pattern is disposed can be automatically generated. In addition, it is also possible to provide a layer (pattern arrangement layer) corresponding to the manual or non-position prohibition area R1 and to specify a location where other small area dummy patterns Ds are not automatically arranged and to exclude this.
    [72] Next, the manufacturing method of the semiconductor device of the present embodiment will be described, including the steps of forming the active region and the dummy region (element isolation region) DR.
    [73] 5 to 23 (except for FIG. 17 and FIG. 18) are cross-sectional views showing one example of a method for manufacturing a semiconductor device of the present embodiment in the order of steps. In addition, in the following sectional drawing, (a) shows the A-A line cross section in FIGS. 3 and 4, (b) shows the B-B line cross section. Further, in (a), the dummy region DR in which the dummy pattern is formed, the circuit region CR, and the power feeding region SR in which the pattern for power feeding is formed are respectively shown. Formation of the small area dummy pattern is prohibited in the circuit area CR and the power supply area SR. In (b), the target area TR, the small area dummy pattern prohibition area IR, and the dummy area DR in which the target pattern is formed are shown, respectively.
    [74] As shown in FIG. 5, the semiconductor substrate 1 (wafer 1w) is prepared, and the thin silicon oxide (SiO) film 2 and the silicon nitride (SiN) film 3 are formed. The semiconductor substrate 1 is, for example, a single crystal silicon wafer having a resistivity on the order of several dB in which p-type impurities are introduced. The silicon oxide film 2 is a sacrificial film for relieving stress between the silicon nitride film 3 and the semiconductor substrate 1, and is formed by, for example, a thermal oxidation method. The silicon nitride film 3 is used for a mask for forming grooves described later. The film thickness of the silicon nitride film 3 is several hundred nm, and is formed by, for example, a chemical vapor deposition (CVD) method.
    [75] Next, as shown in FIG. 6, the photoresist film 4 is formed on the silicon nitride film 3. The photoresist film 4 is formed so as to cover each of the regions where the active regions L1, L2, L3, the large area dummy pattern DL, and the small area dummy pattern Ds described in FIGS. 3 and 4 are formed. As described above, since the size of the small area dummy pattern Ds is not required to be fine enough to use a Levenson mask, the formation area of the small area dummy pattern Ds is applied to a super resolution technique such as the Levenson method. The deterioration of machinability due to the following decrease in focal point tolerance does not occur. This can simplify the mask design.
    [76] Next, as shown in FIG. 7, dry etching is performed in the presence of the photoresist film 4, and the silicon nitride film 3 and the silicon oxide film 2 are etched and removed.
    [77] After removing the photoresist film 4, as shown in FIG. 8, dry etching (anisotropic etching) is performed in the presence of the silicon nitride film 3, and the semiconductor substrate 1 is etched to form the grooves 5. The depth of the groove 5 is several hundred nm. The pattern of the grooves 5 formed in this step is an inverse pattern of the pattern such as the active region L1 shown in FIGS. 3 and 4.
    [78] In this step, the patterned silicon nitride film 3 is used as a hard mask. By using the thin silicon nitride film 3 as a hard mask in this manner, the etching characteristics can be improved and the micromachining can be facilitated. Instead of using the silicon nitride film 3 as a hard mask, the groove 5 may be formed by etching the semiconductor substrate 1 in the presence of the photoresist film 4. In this case, the process can be simplified.
    [79] Next, as shown in FIG. 9, the silicon oxide film 6 is formed on the entire surface of the semiconductor substrate 1 including the inside of the groove 5. The silicon oxide film 6 can be formed by, for example, a CVD method using TEOS (tetraethoxysilane) gas and ozone (O 3 ) as source gases. The film thickness of the silicon oxide film 6 is a film thickness sufficient to fill the grooves 5.
    [80] Next, as shown in FIG. 10, the silicon oxide film 6 is polished using the CMP method. Polishing is performed until the surface of the silicon nitride film 3 is exposed. As a result, the silicon oxide film 6 remains only in the region of the groove 5 to form the element isolation region 7.
    [81] At this time, since the small area dummy pattern Ds is formed in the dummy area DR, dishing occurs only slightly between the patterns of the small area dummy pattern Ds, and the flatness is considerably flatter compared to the case where the dummy pattern does not exist. Can improve. In addition, since the large area dummy pattern DL is also formed in the target region TR, global dishing is prevented, and flatness in the region can be improved. In the case of the present embodiment, the target region TR is formed in the scribe region SR, and the deterioration of the flatness of the target region TR sometimes causes the flatness of the product region PR adjacent to the target region TR. Lowers. However, in the present embodiment, since the large area dummy pattern DL is formed in the target region TR, such adverse effects on the product region PR do not occur.
    [82] Next, as shown in FIG. 11, the silicon nitride film 3 and the silicon oxide film 2 are removed to form the surfaces of the active regions L1, L2 and L3, the large area dummy pattern DL, and the small area dummy pattern Ds. Expose The state of FIG. 3 and FIG. 4 has shown the stage which this process complete | finished. For example, wet etching using thermal phosphoric acid is used to remove the silicon nitride film 3. Thereafter, the surfaces of the silicon oxide film 2 and the element isolation region 7 are appropriately etched using hydrogen fluoride (HF) to realize an almost flat surface as shown in FIG.
    [83] Next, as shown in FIG. 12, a photoresist film (not shown) is formed, and ion implanted with p-type or n-type impurities to form a deep well 8, an n-type well 9, and a p-type well ( 10) form. The deep well 8 has a function of electrically separating the p-type well 10 from the semiconductor substrate 1.
    [84] Next, as shown in FIG. 13, the silicon oxide film 11 serving as a gate insulating film, the polycrystalline silicon film 12 serving as a gate electrode, the tungsten silicide (WSi) film 13, and the silicon serving as a gap insulation film are shown. The nitride film 14 is deposited. The silicon oxide film 11 is formed by, for example, thermal oxidation or thermal CVD, and has a film thickness of several nm. The polycrystalline silicon film 12 is formed by, for example, a CVD method, and n-type or p-type impurities are introduced. The film thickness is several hundred nm. The tungsten silicide film 13 is formed by the CVD method or the sputtering method, and similarly the film thickness is several hundred nm. The tungsten silicide film 13 reduces the sheet resistance of the gate electrode (gate wiring) and contributes to the improvement of the response speed of the device. The silicon nitride film 14 is formed by, for example, a CVD method, and has a thickness of several hundred nm.
    [85] In addition, although the tungsten silicide film 13 is illustrated here, other metal silicide films, such as a titanium silicide (TiSi) film and a cobalt silicide (CoSi) film, can be used. Moreover, although the laminated film of the tungsten silicide film 13 and the polycrystalline silicon film 12 is illustrated, the laminated film of metal films, such as a polycrystalline silicon film, a barrier film, and tungsten (W), may be sufficient. In this case, the resistivity of the gate electrode (gate wiring) can also be reduced. Metal nitride films such as tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN) may be used for the barrier film. In addition to tungsten, tantalum (Ta), titanium (Ti) and the like can be used for the metal film.
    [86] Next, as shown in FIG. 14, the photoresist film 15 is formed on the silicon nitride film 14, dry etching (anisotropic etching) is performed, and the silicon nitride film 14 is patterned as shown in FIG. . As a result, a gap insulating film 16 is formed. The pattern of this gap insulating film 16 is demonstrated later. In the exposure step for forming the photoresist film 15, the target T1 is used for position detection of mask alignment.
    [87] Next, the photoresist film 15 is removed by ashing or the like, and as shown in FIG. 16, the tungsten silicide film 13, the polycrystalline silicon film 12, and the silicon oxide film 11 are present in the presence of the gap insulating film 16. Etching (anisotropic etching) is performed to form the gate electrode 17.
    [88] At this time, the second small area dummy pattern Ds2 and the target T2 are formed simultaneously with the gate electrode 17.
    [89] 17 is a plan view showing a state in this step and corresponds to FIG. 3. 18 is an enlarged plan view corresponding to FIG. 4.
    [90] As shown in FIG. 17, the target T2 is formed in the scribe area SR in addition to the small area dummy pattern Ds2. The target T2 is used at the time of exposing the subsequent process, for example, the wiring formation or the connection hole forming process. The target T2 is formed on the large area dummy pattern DL and is formed to be embedded therein. In addition, although the pattern placement prohibition area R2 is provided around the target T2 to prevent the recognition rate from being lowered when the target T2 is used later, the large area dummy pattern DL has the pattern placement prohibition area ( It is formed larger than R2). As a result, the pattern is not formed in the pattern disposition prohibition region R2 except for the target T2, so that the target T2 can be accurately recognized. In addition, since the target T2 is formed on the large area dummy pattern DL, the target T2 is not formed on the recessed base, but is formed on the flattened base. For this reason, in the exposure process using the target T2, recognition of the target T2 is performed correctly later, and the mask registration precision can be improved. In addition, since the large area dummy pattern DL is formed under the target T2, the flatness of the region is improved, and the flatness of the product region PR near the target T2 is improved. The photolithography margin can be improved to facilitate the etching process.
    [91] In addition, a small area dummy pattern Ds2 is also formed in the scribe region SR. Thereby, the flatness of the said area can be improved. However, it is not arranged in the placement prohibition area R1 of the small area dummy pattern. The small area dummy pattern Ds2 will be described later.
    [92] The gate electrode 17 is formed in the product region PR. In addition, a plurality of small area dummy patterns Ds2 are disposed between the patterns of the gate electrodes 17. In the same manner as in FIG. 3, it is not disposed in the placement prohibition area R1 of the small area dummy pattern. The method of generating the arrangement inhibiting area R1 is the same as described above.
    [93] As shown in FIG. 18, the small area dummy pattern Ds2 is formed on the inter-pattern space of the lower area small dummy pattern Ds. That is, the pattern between the small area dummy pattern Ds2 and the lower area dummy pattern Ds in the lower layer is formed in a state in which the pitch is shifted by half. That is, the small-area dummy pattern Ds is formed to be shifted with respect to the small-area dummy pattern Ds by Px in the x direction and Py in the y direction. Both Px and Py are, for example, 0.7 µm. By forming the small-area dummy pattern Ds2 by shifting by half pitch as described above, the flatness can be improved without the influence of dishing generated in the lower layer. That is, since dishing in the lower layer occurs in the space portion of the small-area dummy pattern Ds, and the small-area dummy pattern DS2 is formed thereon, the dishing does not overlap. Dicing by the small-area dummy pattern Ds2 occurs in the space portion, but a small-area dummy pattern Ds is formed in this lower layer, and no dishing occurs from the beginning. That is, when the small area dummy patterns Ds and Ds2 are arranged as in the present embodiment, dishing is not performed in the upper layer of the region where dishing occurs in the lower layer, and dishing is performed in the lower layer. It is formed on an area which does not generate. Thereby, the dishing amount which combined two layers can be reduced, and the whole flatness can be reduced.
    [94] Further, the small area dummy pattern Ds2 in the upper layer is not formed in the pattern disposition prohibition region R1 as in the case of the small area dummy pattern Ds. The method of generating the small area dummy pattern Ds2 is also the same as that of the small area dummy pattern Ds except that the lattice position is half pitch shifted.
    [95] Although the example in which the small-area dummy patterns Ds and Ds2 are half-pitch shifted has been described here, the shift amount is arbitrary as long as the short side of Ds2 overlaps Ds1. That is, Ds2 should just be formed in the upper part of the space part of Ds1.
    [96] Next, as shown in FIG. 19, an impurity semiconductor region 19 is formed by ion implantation of impurities. Low concentration of impurities are introduced into the impurity semiconductor region 19. The conductivity type of the impurity to be implanted is selected according to the channel type of the MISFET to be formed. P-type impurities are implanted into the n-type well region to form a p-channel MISFET. An n-type impurity is introduced into the p well region to form an n-channel MISFET.
    [97] Next, as shown in FIG. 20, the silicon nitride film is formed in the whole surface of the semiconductor substrate 1, for example, and anisotropic etching is performed to this, and the sidewall spacer 20 is formed. Thereafter, ion implantation is performed to form the impurity semiconductor region 21. The impurity semiconductor region 21 selects impurity ions so that the conductivity type is appropriate according to the region as described above. High concentrations of impurities are inserted into the impurity semiconductor region 21, and together with the impurity semiconductor region 19, a source-drain having an LDD (Lightly Doped Drain) structure is formed.
    [98] Next, as shown in FIG. 21, the silicon oxide film 22 which embeds a gate electrode pattern is formed, and as shown in FIG. 22, the silicon oxide film 22 is polished by CMP method, and the surface is planarized. In this planarization, since the small area dummy pattern Ds2 is formed in the same layer as the gate electrode pattern, the flatness is improved. In particular, since half-pitch shift | deviation and the upper-area small area dummy pattern Ds2 are formed with respect to the small area dummy pattern Ds of a lower layer, dishing in the space between patterns is not overlapped between two layers. For this reason, the fall of flatness by overlapping of dishing can be suppressed. Further, since the large area dummy pattern DL is formed in the region of the target T2, flatness can be improved even in the scribe region SR without generating global dishing. As a result, the yield and the like can be improved without adversely affecting the product region PR. In addition, since the small area dummy pattern Ds2 is disposed in the scribe area SR, the flatness can be improved in the same manner as the product area PR.
    [99] Here, an example in which the target T2 is formed in the scribe region SR is shown. However, the target T2 may be formed in the product region PR. In addition, although the target pattern was illustrated here as a pattern which requires pattern recognition, of course, if the pattern becomes an object of optical pattern recognition, of course, this invention can be applied. For example, the inspection pattern used for quality control of mask fitting, the inspection pattern for monitoring film thickness, the position detection pattern for laser relief, etc. may be sufficient.
    [100] Next, as shown in FIG. 23, the connection hole 23 is formed in the silicon oxide film 22, and the connection plug 24 is formed in the connection hole 23. Next, as shown in FIG. In addition, a wiring 25 is formed on the silicon oxide film 22.
    [101] The connection hole 23 can be formed by anisotropic etching using a photoresist film (not shown) as a mask. In forming the photoresist film, i.e., exposing in this step, the above-mentioned target T2 can be used for position detection of mask alignment. As the connection plug, for example, a laminated film of a titanium nitride film and a tungsten film can be used in addition to polycrystalline silicon. The connection plug is formed by forming a conductive material which fills it after the opening of the connection hole, and removes the conductive film in regions other than the connection hole by using the CMP method.
    [102] Similarly, the wiring 25 can be formed by anisotropic etching using a photoresist film (not shown) as a mask. In forming the photoresist film, i.e., exposing in this step, the above-mentioned target T2 can be used for position detection of mask alignment. As the wiring 25, for example, a metal material such as a tungsten, titanium nitride, and a laminated film of tungsten can be used. The wiring 25 can be formed by patterning the metal material after film formation.
    [103] In addition, although wiring of upper layers, such as a 2nd layer and a 3rd layer, can be formed and it can be set as a multilayer wiring structure, since it can be formed similarly to the case of the said wiring 25, the description is abbreviate | omitted.
    [104] 24 is a plan view showing a state in which the scribe area SR is scribed after the wafer process is completed. The wafer 1w is divided by the scribe brine SL, and the chip 1c is formed. The width of the scribe brine SL is a dimension in which a margin is added to the blade width (for example, 35 µm). For this reason, the area | region of about several tens of micrometers remains as the distance from the edge part of the product area | region PR to the edge part of the chip | tip 1c in the chip | tip 1c. Part of the targets T1 and T2 and the large-area dummy pattern DL remain in this remaining area. In addition, the target T3 is shown in FIG. This is a target pattern formed at the same time as patterning the wiring 25 of the first layer. The target T3 is used to form wirings or through holes in the upper layer.
    [105] As mentioned above, although the invention made by this inventor was demonstrated concretely based on embodiment of this invention, this invention is not limited to the said embodiment, Needless to say that it can be variously changed in the range which does not deviate from the summary. .
    [106] For example, although the example which provided the shift | offset | difference with the small-area dummy patterns Ds and Ds2 in both the x direction and the y direction was shown in embodiment, any one shift may be sufficient.
    [107] Moreover, although the rectangular shape was illustrated as small-area dummy patterns Ds and Ds2, other shapes, such as rectangular, may be sufficient. For example, as shown in FIG. 25 and FIG. 26, a lattice dummy pattern may be used. That is, as shown in FIG. 25, the lattice pattern 26 is formed simultaneously with the active region L1, and as shown in FIG. 26, the lattice pattern 27 is half-pitch shifted with respect to the pattern 26. It may be formed simultaneously with the gate electrode 17. In addition, instead of the small-area dummy patterns Ds and Ds2, a line-shaped dummy pattern may be used as shown in FIGS. 27 and 28. That is, as shown in FIG. 27, the line-shaped pattern 28 is formed simultaneously with the active region L1 and the like, and as shown in FIG. 28, the line-shaped pattern 29 is half pitched with respect to the pattern 28. It may be shifted and formed simultaneously with the gate electrode 17. These dummy patterns 26, 27, 28, and 29 are not formed in the pattern disposition prohibition region R1 as in the embodiment. In addition, the sizes of these patterns 26, 27, 28, and 29 are also the same as in the embodiment.
    [108] Among the inventions disclosed by the present invention, the effects obtained by the representative ones are briefly described as follows.
    [109] (1) Dishes on a plurality of stacked flat screens can be suppressed.
    [110] (2) The surface flatness in a large area pattern area for optically detecting a target or the like can be improved.
    [111] (3) The flatness of a large area pattern such as a multi-layered flat screen or a target can be improved, and the processing margin in the photolithography step and the etching step can be improved.
    权利要求:
    Claims (28)
    [1" claim-type="Currently amended] A semiconductor device having a semiconductor substrate having a semiconductor element formed on its main surface, a first pattern formed on the main surface or any one layer on the main surface, and a second pattern formed on an upper layer of the first pattern,
    The first pattern includes a dummy pattern, and the second pattern includes a pattern that is an object of optical pattern recognition.
    The pattern which becomes the object of the said optical pattern recognition is formed so that it may be contained in the planar shape of the said dummy pattern.
    [2" claim-type="Currently amended] The method of claim 1,
    And the other dummy pattern having an area smaller than that of the dummy pattern.
    [3" claim-type="Currently amended] The method of claim 2,
    And the dummy pattern and the other dummy pattern are formed in a scribe region.
    [4" claim-type="Currently amended] The method of claim 2,
    And the other dummy pattern is formed in a product region and a scribe region.
    [5" claim-type="Currently amended] The method of claim 1,
    And the dummy pattern is formed at an area greater than or equal to a pattern disposition prohibition area around a pattern to be the target of the optical pattern recognition.
    [6" claim-type="Currently amended] The method of claim 5,
    The first pattern includes another dummy pattern having a processing dimension of the same order as the design rule of the semiconductor element and having a smaller area than the dummy pattern. A semiconductor device, characterized in that no other dummy pattern is arranged.
    [7" claim-type="Currently amended] The method of claim 6,
    And the dummy pattern is formed in a scribe region of a semiconductor wafer, and the other dummy pattern is formed in a product region and a scribe region of the semiconductor wafer.
    [8" claim-type="Currently amended] A semiconductor device having a semiconductor substrate having a semiconductor element formed on a main surface thereof, a first pattern formed on the main surface or any one layer on the main surface, and a second pattern formed on an upper layer of the first pattern.
    The first pattern includes a first dummy pattern, and the second pattern includes a second dummy pattern having a pattern pitch and a pattern width having the same design dimensions as the first dummy pattern.
    The second dummy pattern is formed on a space of the first dummy pattern at a planar position thereof.
    [9" claim-type="Currently amended] The method of claim 8,
    The short side of any one of the second dummy patterns is formed to overlap the first dummy pattern at the planar position.
    [10" claim-type="Currently amended] The method of claim 8,
    And the first dummy pattern and the second dummy pattern are shifted by a distance of half the pitch in the planar position.
    [11" claim-type="Currently amended] The method of claim 8,
    The first pattern further includes another dummy pattern having a larger area than the first dummy pattern, and the second pattern further includes a pattern that is an object of optical pattern recognition.
    The pattern which becomes the object of the said optical pattern recognition is formed so that it may be contained in the planar shape of the said other dummy pattern.
    [12" claim-type="Currently amended] The method of claim 11,
    The other dummy pattern is formed in an area larger than the pattern disposition prohibition area around the pattern to be the object of the optical pattern recognition,
    And the first dummy pattern is not disposed in the pattern disposition prohibition region.
    [13" claim-type="Currently amended] The method of claim 11,
    And the other dummy pattern is formed in a scribe region of a semiconductor wafer, and the first and second dummy patterns are formed in a product region and a scribe region of the semiconductor wafer.
    [14" claim-type="Currently amended] The method of claim 1,
    The first pattern is an active region pattern formed on the main surface, and the second pattern is a pattern formed on the same layer as the gate electrode constituting the semiconductor element.
    [15" claim-type="Currently amended] (a) forming a first pattern including a dummy pattern on the main surface of the semiconductor substrate or on one of the member layers on the main surface;
    (b) depositing an insulating film on the main surface on which the first pattern is formed or on a member patterned with the first pattern, and polishing the insulating film to planarize the surface;
    (c) forming a second pattern including a pattern that is an object of optical pattern recognition on an upper layer of the planarized surface;
    And a pattern that is an object of optical pattern recognition is formed to be included in a planar shape of the dummy pattern.
    [16" claim-type="Currently amended] The method of claim 15,
    And a step of optically detecting a pattern to be the object of optical pattern recognition and aligning the semiconductor substrate.
    [17" claim-type="Currently amended] (a) forming a first pattern including a dummy pattern on a main surface of a semiconductor substrate or on any member layer on the main surface;
    (b) forming a second pattern including a pattern that is an object of optical pattern recognition on an upper layer of the first pattern;
    (c) optically detecting the pattern to be the object of the optical pattern recognition and aligning the semiconductor substrate;
    The semiconductor device manufacturing method of claim 1, wherein the pattern to be the target of the optical pattern recognition is formed to be included in the planar shape of the dummy pattern.
    [18" claim-type="Currently amended] The method of claim 15,
    And the dummy pattern is formed with an area equal to or greater than a pattern disposition prohibition area around a pattern to be the target of the optical pattern recognition.
    [19" claim-type="Currently amended] The method of claim 15,
    The first pattern further includes a first dummy pattern, and the second pattern further includes a second dummy pattern having a pattern pitch and a pattern width of the same design dimension as the first dummy pattern.
    The second dummy pattern is formed on a space of the first dummy pattern at a planar position thereof.
    [20" claim-type="Currently amended] The method of claim 19,
    Any one short side of the second dummy pattern is formed so as to overlap the first dummy pattern at its planar position,
    A second configuration in which the first dummy pattern and the second dummy pattern are shifted by a distance of half of the pitch in the planar position;
    It has a structure of any one of the manufacturing methods of the semiconductor device.
    [21" claim-type="Currently amended] The method of claim 15,
    And forming the dummy pattern in the scribe area of the semiconductor wafer and forming the first and second dummy patterns in the product area and the scribe area of the semiconductor wafer.
    [22" claim-type="Currently amended] The method of claim 15,
    The member to which the first pattern is transferred is a semiconductor substrate, and the member formed by transferring the second pattern is a gate electrode.
    [23" claim-type="Currently amended] The method of claim 8,
    The first pattern is an active region pattern formed on the main surface, and the second pattern is a pattern formed on the same layer as the gate electrode constituting the semiconductor element.
    [24" claim-type="Currently amended] The method of claim 17,
    And the dummy pattern is formed to have an area greater than or equal to a pattern disposition prohibition area around a pattern that is an object of optical pattern recognition.
    [25" claim-type="Currently amended] The method of claim 17,
    The first pattern further includes a first dummy pattern, and the second pattern further includes a second dummy pattern having a pattern pitch and a pattern width having the same design dimensions as the first dummy pattern.
    The second dummy pattern is formed on a space of the first dummy pattern at a planar position thereof.
    [26" claim-type="Currently amended] The method of claim 17,
    And forming the dummy pattern in the scribe area of the semiconductor wafer and forming the first and second dummy patterns in the product region and the scribe area of the semiconductor wafer.
    [27" claim-type="Currently amended] The method of claim 17,
    The member to which the first pattern is transferred is a semiconductor substrate, and the member formed by transferring the second pattern is a gate electrode.
    [28" claim-type="Currently amended] The method of claim 25,
    Any one short side of the second dummy pattern is formed so as to overlap the first dummy pattern at its planar position,
    A second configuration in which the first dummy pattern and the second dummy pattern are shifted by a distance of half of the pitch in the planar position;
    It has a structure of any one of the manufacturing methods of the semiconductor device.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-12-03|Priority to JP34542999A
    1999-12-03|Priority to JP1999-345429
    2000-11-10|Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼, 스즈키 진이치로, 가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈
    2001-08-29|Publication of KR20010081954A
    2006-07-12|Application granted
    2006-07-12|Publication of KR100599218B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP34542999A|JP4307664B2|1999-12-03|1999-12-03|Semiconductor device|
    JP1999-345429|1999-12-03|
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