• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A demodulator such as a digital terrestrial broadcaster that transmits coded digital video and audio information in a packet form counts a synchronous code pattern detection circuit that detects a partial synchronization code pattern from the most significant bit signal of the received packet data, and counts the number of symbol data in the received packet data. A synchronization detection setting circuit for determining a correct division synchronization code pattern by obtaining a division synchronization code pattern from the synchronization code pattern detection circuit when the symbol number counter circuit and the symbol number counter circuit have completed a certain number of counting, and a synchronization code pattern detection circuit And a synchronous detection protection counter circuit for detecting and setting the division synchronization signal in the received data from a specific number of countups of the output and the symbol number counter circuit. With this configuration, packet synchronization detection, AGC, and clock reproduction are stably and precisely processed even in an environment that is poor in broadcast reception such as a weak electric field or strong signal or C / N degradation due to the multipath characteristic of terrestrial waves. A digital broadcast demodulator is provided.
    公开号:KR20010032615A
    申请号:KR1020007005891
    申请日:1999-09-29
    公开日:2001-04-25
    发明作者:니노미야구니오；사카시타세이지；가토히사야
    申请人:모리시타 요이찌；마쯔시다덴기산교 가부시키가이샤；
    IPC主号:
    专利说明:

    Demodulator for demodulating digital broadcast signals
    [2] Recently, with the improvement of digital compression technology and digital modulation and demodulation technology, television broadcasting has been provided using satellite and CATV. Video data is encoded in MPEG2 and the digital modulation system is realized by QPSK method in satellite broadcasting or QAM method in CATV. In the United States, terrestrial digital broadcasting (DTV) is scheduled from fall 1998, and a digitally modulated 8VSB system with video compression to MPEG2 is planned.
    [3] With reference to the drawings, a conventional example of a digital terrestrial broadcast reception and demodulation device will be described below.
    [4] 10 is a block diagram of a demodulator for terrestrial digital broadcasting. The RF modulated wave signal received by the antenna 1 receiving the RF signal is input to the tuner 2 which selects a channel and an arbitrary channel is selected. In the tuner 2, the selected signal is gain controlled, frequency converted and output as the intermediate frequency IF. The IF output from the tuner 2 is limited in band to the frequency characteristic determined by the SAW filter 3 and input to the amplifier 4 which amplifies the signal.
    [5] In the amplifier 4, the signal level is controlled and supplied to the mixers 5 and 6 by the control signal from the AGC detector 11 described later. In the mixers 5 and 6, the IF signal is multiplied by the local frequency signal from the voltage controlled oscillator 8 (VCO) and quadrature detected. After quadrature detection, the baseband signals of the I and Q signals are supplied separately to the LPFs 9 and 10.
    [6] Here, the mixer 6 is applied to the LPF 9 by transferring the bit signal generated by the difference between the IF carrier frequency and the frequency signal from the VCO 8 and is supplied to the VCO 9 as a frequency error signal. Regeneration carriers from the VCO 8 are applied to the mixer 5, and carriers whose phases are delayed by 90 degrees are supplied to the mixer 6 through a 90 degree phase shifter 7 which delays the phase by 90 degrees. By configuring the PLL with a system of mixers 6, LPF 9, VCO 8 and 90 degree phase shifter 7, a local signal equal to the IF carrier signal of the received modulated wave can be oscillated by the VCO 8; Can be.
    [7] The baseband signal supplied to the LPF 10 is limited to desired frequency characteristics, and is supplied to an A / D converter 12 for converting an analog signal into a digital signal and an AGC detector 11 for determining the average of the signal amplitude. In the AGC detector 11, an envelope of the input baseband signal is detected, and an AGV control signal is generated. The AGC operation is performed because the AGC control signal is fed back to the amplifier 4 and the tuner 2 and controlled.
    [8] On the other hand, the baseband signal supplied to the A / D converter 12 is converted into a digital signal and supplied to the demodulation processor and the waveform equalizer 12 at the rear stage. Digital data delivered from the A / D converter 12 is applied to the BPF 13, and the half frequency component of the symbol frequency Fs of the data rate is extracted.
    [9] The frequency component of Fs / 2 is fed to square circuit 14 and squared and applied to BPF 15. In the BPF 15, a frequency component equal to the symbol rate is extracted and applied to the phase detector 16 which detects the phase error. At the phase detector 16, a phase error from the symbol frequency Fs is detected and supplied to the loop filter 17.
    [10] In the loop filter 17, the phase error signal is integrated and supplied as a control signal of the VCO 18. By constructing a feedback loop to the BPF (Fs / 2) 13, the square circuit 14, the BPF (Fs) 15, the phase comparator 16, the loop filter 17, and the VCO 18, the clock is Is played.
    [11] Furthermore, the output digital data from the A / D converter 12 is supplied to a symbol determination circuit 19 that determines the value of the symbol data, and the value of the received symbol data is determined so as to synchronize to detect the synchronization signal in the received data. It is supplied to the signal detection circuit 21. In the synchronization signal detection circuit 21, a synchronization signal of packet data is detected in comparison with the symbol data value of the synchronization reference signal from the known data circuit 21 of the synchronization signal which transfers the data value of the known synchronization signal. .
    [12] Therefore, the important steps for demodulating the digital terrestrial broadcast 8VSB and the like are the synchronization signal detection processing step of the transmission packet data, the AGC processing step of controlling the signal amplitude, and the clock reproduction step of extracting and reproducing the clock component from the transmission data.
    [13] However, when the environment for receiving a broadcast such as a specific ghost or multipath of digital terrestrial broadcast is poor and co-channel interference occurs by NTSC or other analog broadcast, such synchronization detection processing by precisely determining the data value of the symbol, In AGC processing by determining the average of the detected baseband signals, or clock regeneration processing for extracting frequency components in transmission data, it is extremely difficult to detect synchronization, operate AGC, or precisely reproduce clocks. Therefore, in order to increase the accuracy, the filter had to be composed of a process of increasing the sampling frequency or a fairly large circuit.
    [1] The present invention relates to a digital broadcast demodulator for demodulating a digitally modulated signal modulated with, for example, multi-value VSB modulation in a digital broadcast in which video audio information is encoded and digitally transmitted.
    [20] 1 is an entire block diagram of a digital broadcast demodulator of the present invention, FIG. 2 is an essential block diagram of a digital broadcast demodulator in a first embodiment of the present invention, and FIG. 3 is an essential block of a digital broadcast demodulator in a second embodiment of the present invention. 4 is an essential block diagram of a digital broadcast demodulator in a third embodiment of the present invention, FIG. 5 is a data frame diagram of a digital terrestrial broadcast VSB modulation system, FIG. 6 is a field synchronization signal diagram of a digital terrestrial broadcast VSB modulation system, Fig. 7 is a waveform diagram of a division synchronization signal for explaining a second embodiment of the present invention, Fig. 8 is a waveform diagram of a division synchronization signal for explaining a third embodiment of the present invention, and Fig. 9 is a clock phase error detection of the present invention. 10 is a block diagram showing the configuration of a digital broadcast demodulator in the prior art.
    [14] In order to solve the above problem, the digital broadcast demodulator of the present invention includes, in one aspect, a circuit for setting a synchronization signal in the received data by the most significant bit (MSB) indicating a positive or negative sign of the received transport packet data. It features.
    [15] With this arrangement of the present invention, even in a strong radio wave state of strong ghost or multipath interference characteristics of digital terrestrial broadcasting, it is possible to stably detect and set a synchronization signal in a packet with an extremely low cost circuit configuration.
    [16] The second aspect of the digital broadcast demodulator of the present invention determines the difference between the synchronization signals of the received packet data, which should be essentially the same level, and detects the clock phase error of the transmission data, thereby reproducing the clock by phase control based on this phase error. It is.
    [17] With this configuration of the present invention, an extremely low-circuit circuit configuration is provided by detecting a phase error of the clock of the received data and controlling the feedback by feeding back to the VCO, even in a poor radio wave state of the strong ghost or the multipath interference characteristics of digital terrestrial broadcasting. Can be played stably and precisely.
    [18] The third aspect of the digital broadcast demodulator of the present invention is characterized by detecting a synchronization signal in the received packet data, determining a difference between the data value of the detected synchronization signal and a reference value, and controlling the ATC based on this difference. .
    [19] With this configuration of the present invention, precise AGC is realized even in a poor radio wave state.
    [21] DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the drawings. First, in FIG. 1, the schematic configuration of the digital broadcast demodulator of the digital terrestrial broadcast VSB modulation system will be described in detail with reference to the claims of the present invention.
    [22] Since the same reference numerals are assigned to components having the same function as that of FIG. 10 showing a conventional reception demodulator for digital terrestrial broadcasting, detailed description thereof will be omitted.
    [23] The output digital data Data of the A / D converter 12 is divided into four parts. One of these is applied to the sync code pattern detection circuit 101 of the division sync detection setting circuit block 116, and the sync pattern is detected by detecting a sign bit (most significant bit (MSB) indicating a positive or negative sign). Is detected. The output of the sync code pattern detection circuit 101 is divided into three parts, which are separately supplied to the detection protection counter circuit 103, the division sync detection setting circuit 104, and the clock phase error detection circuit 105. .
    [24] The output of the section synchronous detection setting circuit 104 for determining the correct synchronization pattern of each section is supplied to the symbol number counter 102 as a reset signal, and the result of counting the number of symbols in one packet is determined by the detection protection counter 103 and The section synchronous detection setting circuit 104 returns. The detection protection counter 103 sends a segment start signal Segst indicating the position of the segment sync signal in the packet to the terminal 109 based on the fed back information, and the segment sync setting signal (not shown) indicating the detection setting of the segment sync signal. Shld) to terminal 110.
    [25] The division synchronization setting signal Shld is applied to the switch circuit 111 to become a switch signal for switching the control signal Gerr and the control signal from the AGC detector circuit 11 from the AGC error detection circuit 106 described later.
    [26] The second output digital data Data from the A / D converter 12 is a signal from the sync code pattern detection circuit 101 to the clock phase error detection circuit 105 and the division start signal from the detection protection counter 103 ( Segst) is supplied together, and the clock phase error of the data is output to the terminal 108 as a clock regeneration control signal Pherr. This clock regeneration control signal (Pherr) is applied to the D / A converter 112 and converted into an analog signal, which is supplied to the LPF 113. The control signal integrated in the LPF 113 is applied to the VCO 18 to control its oscillation frequency. The feedback loop is composed of the flows of the VCO 18, the A / D converter 12, the clock phase error detection circuit 105, the D / A converter 112, and the LPD 113.
    [27] Further, the third divided output of the digital data Data of the A / D converter 12 is applied to the AGC error detection circuit 116 and output to the terminal 107 as an AGC control signal Gerr different from the known value. . The AGC control signal Gerr is applied to the D / A converter 114 to be converted into an analog signal and supplied to the LPF 115. The AGC control signal integrated in the LPF 115 is supplied to the switch circuit 111.
    [28] The switch circuit 111 switches between the control signal from the analog AGC detector 11 and the AGC control signal from the LPF 115 detected by digital processing by the partitioning signal Shld. The ATC control signal output from the switch circuit 111 is applied to the amplifier 4 and the tuner 2 so that the amplitude of the input signal is controlled.
    [29] The fourth output of the A / D converter 12 is applied to the waveform equalizer 22 to become a reception output.
    [30] In the digital broadcast demodulator configured as described above, specific embodiments corresponding to the claims will be described below.
    [31] (Example 1)
    [32] Figure 2 shows a block diagram of an embodiment corresponding to claims 1, 2 and 3 of the present invention. This embodiment relates to a digital broadcast demodulator used in an apparatus for receiving digital broadcasts in which coded digital video and digital audio information is transmitted in the form of packets. In particular, in a digital VSB transmission system, the present invention is a circuit for receiving transport packet data. It is configured to process the code bit MSB and a synchronization signal in the received data is set. In this configuration, even if the radio wave conditions for receiving the broadcast, such as ghost, multipath, or co-channel interference of NTSC, are poor, the synchronization signal in the packet can be detected and can be set precisely and reliably.
    [33] The configuration and operation are described below with reference to FIG. In the embodiment of the present invention, the baseband signal after quadrature detection is applied to the A / D converter 12 and the clock reproduction is already locked. Among the output digital data Data from the A / D converter 12, the code bits MSB are supplied to the sync code pattern detection circuit 101 and the symbol number counter 116 in the block sync detection setting circuit block 116. . Here, the data structure of the packet of VSB digital terrestrial broadcasting is shown in FIG. 5 and FIG. The transmission frame shown in Fig. 5 is composed of 832 symbols in one packet, and the partition synchronization signal is inserted only four symbol parts from the start point.
    [34] For every 313 packets (blocks), field sync signals # 1 and # 2 are inserted. 6 shows a field synchronization signal. At the beginning of the packet, four compartment synchronization signals and a certain number of PN codes are constructed. The partition synchronization signal is a mapping signal whose values are +5, -5, -5, +5 as shown in FIG. This signal is known data and is inserted at the beginning of every packet as shown in FIG.
    [35] In the sync code pattern detection circuit 101, the code bit MSB of all received data is processed, and +,-,-, + are detected as a code pattern of the division sync signal. When processing this signal with two's complement, the codes of the block sync signal are-, +, +,-.
    [36] Even with the strong ghost, multipath, or NTSC co-channel interference characteristics of digital terrestrial broadcasting, when processing only the code bits, the received data is significantly affected by impedance, causing degradation. However, since the code bit information is extremely strong against the interference effect even in a situation where wave reception is poor, it is possible to stably detect the synchronization pattern of the synchronous signal.
    [37] When the sync code pattern detection circuit 101 simultaneously detects a sync pattern for four symbols in all received data, a signal Sdet is output to the detection protection counter 103 and the division sync detection setting circuit 104. When the power is supplied, an all-in-one reset is applied and automatically starts counting up in synchronization with the signal processing clock equal to the symbol rate Fs. When counting 832 symbols in one packet, the count-up signal Co is output to the detection protection circuit 103 and the division synchronization detection setting circuit 104.
    [38] In the division synchronization detection setting circuit 104, the synchronization pattern detection signal Sdet, the symbol number count-up signal Co, and the signal Shld from the detection protection counter 103 are supplied, and division synchronization is performed in all received data. If there is a pattern identical to the code pattern, it is determined which pattern is the correct divisional synchronization signal.
    [39] In the operation of the division synchronization detection setting circuit 104, the division synchronization code from the synchronization code pattern detection circuit 101 or the signal Co outputted when the symbol number counter 102 reaches the symbol number count value 832 of the packet. When the pattern detection signal Sdet is input, the output signal Lo is output.
    [40] In general, although the received data contains a lot of code pattern data identical to the block synchronization code pattern, the same code pattern detection signal Sdet as the block synchronization signal is supplied to the block synchronization detection setting circuit 104 and dropped low by one clock portion. When the floating Lo signal is input, the symbol number counter 102 is reset once and counts up to 832, which is the number of symbols in one packet. During counting up, when the same pattern as the sync code pattern is detected, the division synchronization detection setting circuit 104 outputs a signal Lo to reset the symbol number counter 102. Therefore, the counting operation is repeated until the signal Sdet is input simultaneously with the output of the count-up signal Co of the number of symbols of one packet. That is, in the case of the correct division synchronization signal, when 832 counts are finished, there is a division synchronization signal of the next packet at the same time, and the signal Sdet and the signal Co are simultaneously inputted to the division synchronization detection setting circuit 104, and the Lo signal. Is output and the symbol number counter 102 is reset.
    [41] The output signal Co of the symbol number counter 102 and the output signal Sdet of the synchronization pattern detection circuit 101 are also supplied to the detection protection counter 103. As a result, the detection protection counter 103 sets the holding signal Shld high once at any time, and the division synchronization detection setting circuit 104 is held by this signal Shld, and the signal Sdet and the signal Sdet are separated from the circuit 101. The reset signal Lo is not outputted until the signal Co from the circuit 102 is input at the same time. However, at this first time, if the signal Co is input to the circuit 103 next, if the signal Sdet is not input at the same time, the symbol number counter 102 and the detection protection counter 103 are reset, and the signal ( Shld) goes low. In the detection protection counter 103, the number of times the signal Sedt and the signal Co are input simultaneously is counted, and when Sedt and Co are input simultaneously at the specified number of times, for example, four consecutive times, the correct partition in the received data is received. It is detected and set as a synchronization signal. The reason for this is that when the signal Co is outputted, a signal having the same pattern but not a correct divisional synchronization signal can be avoided. Therefore, when the division synchronization signal in the received data is repeatedly detected and set by a predetermined number of times, the division setting signal Shld is fixed at the high level.
    [42] By this Shld signal, in the state where the reset signal Lo is not output until the division synchronization detection setting circuit 104 is held and the Sdet signal from the circuit 101 and the signal Co from the circuit 102 are simultaneously input. maintain. Therefore, if only the Sdet signal is input in the meantime, the reset signal Lo is not output. Even in this holding state, only when the signal Sdet and the signal Co are input at the same time, the reset signal Lo is output, and the symbol number counter 102 is updated.
    [43] Once the division synchronization signal is set and the signal Sdet and the signal Co are not simultaneously input, the division setting is not immediately canceled and setting of the division synchronization signal detection when a mistake is made 8 times or more for a predetermined number of times. Is canceled and the signal Shld is set to the low level.
    [44] Therefore, when the number of symbols counter 102 is detected each time the same waveform as the division synchronization signal is detected, while the waveform similar to the synchronization signal is not input until it is reset by the correct division synchronization signal and the specified number is counted up, the symbol The count up of the number counter 102 and the input of the correct sync signal of the next section occur simultaneously and the signal Shld is output from the detection protection counter, and similar waveforms are removed while the circuit 102 counts up, and this operation is performed. When the predetermined number of times is repeated, it is detected and set as the correct divisional synchronization signal.
    [45] The structure of this embodiment is a synchronization code pattern detection circuit 101 for detecting a known synchronization signal code pattern by processing only the code bits MSB of received data, a symbol number counter 102 for counting the number of symbols in one packet, and synchronization. When the symbol number counter 102 detects the specified count value while simultaneously detecting the signal code pattern, the division synchronous detection setting circuit that determines the correct division synchronous code pattern and outputs a signal for resetting the symbol number counter 102 ( 104 and a detection protection counter that outputs a signal Shld by detecting and setting the divisional synchronization signal in the received data from the output of the synchronization code pattern detection circuit 101 and the predetermined number of count-ups of the symbol number counter circuit 102. Circuitry, which is poor in receiving broadcasts such as the multipath characteristics of strong ghost or digital broadcasts, co-channel interference of NTSC broadcasts, low C / N, and others. In OPA reception conditions, can be set to stabilize the synchronization signal can be stably detected decryption process.
    [46] (Example 2)
    [47] 3 shows a block diagram of Embodiment 2 corresponding to claims 4, 5, 6, and 7 of the present invention. This embodiment relates to a digital broadcast demodulator used in an apparatus for receiving digital broadcasts in which coded digital video and audio information is transmitted in packet form, in particular in a digital VSB transmission system, wherein the clock phase error of the received data Obtained by calculating the difference between the Nth and N + 1th (N > 1) packet synchronization signals, the clock is stably reproduced even in a poor radio wave reception environment.
    [48] The configuration and operation are described below with reference to FIG. The block 116 indicated by the dotted line corresponds to the block synchronous detection setting circuit block shown in Fig. 2 of the first embodiment, and the block synchronous setting signal Shld indicating establishment of detection of the block synchronous signal in the received data Data. And a segment start signal Segst indicating the position of the segment synchronization signal in the packet. The operation of block 116 is the same as described in Embodiment 1, and will be omitted.
    [49] The digital data output Data received from the A / D converter 12 is applied to the clock phase error detection circuit 105. The division synchronization detection setting circuit block 116 supplies a signal Sdet indicating the position of data identical to the code pattern of the synchronization signal in the packet data and a signal Segst indicating the position of the division signal in the packet data.
    [50] 9 is a block diagram of the clock phase error detection circuit 105. The digital data Data of the A / D converter 12 is applied to the addition input of the subtraction circuit 202 through the latch 203. This input is also applied to the subtraction input of the subtraction circuit 202 via the latch 204. In the subtraction circuit 202, the Nth input is subtracted from the N + 1th input, and the subtraction value is applied to the latch circuit 207. The order of subtraction operations is not limited and it is important whether the value is zero. In the latch circuit 207, data is latched by the signal Sdet of the code pattern detection of the division synchronization signal and output to the latch circuit 208. The signal Sdet is adjusted in time so as to latch the subtraction value at the timing after the subtraction operation of the second and third division synchronization signals of the received data by the latch circuit 205. In the latch circuit 208, by latching by a signal Segst indicating the position of the division synchronization signal to be sent out after detecting and setting the division synchronization signal, it is output as a clock phase error signal Pherr. The signal Segst is time adjusted to the timing latched by the latch circuit 208 by the subtracted values of the second and third compartment synchronization signals in the latch circuit 206.
    [51] This circuit is configured to detect the division synchronization signal of four symbols as shown in Fig. 7, and the circuit can be configured differently if different code patterns are used.
    [52] Fig. 7 shows sample points of the division synchronization signal unit obtained in this way. The sample points are a, b, c, d when the oscillation frequency of the VCO 18 is completely in phase with the clock of the received data. The data values are smooth values because the band is limited so as not to cause inter-code interference by the filter processing of the SAW filter 3 at the front end. Here, if the N-th data is the second data value b, c-b is processed by subtracting from the N + 1th value c.
    [53] As shown in Fig. 7, the subtraction process determines the inclination of the connection lines of sample points b and c, or b 'and c', which are originally the same level. Here, when the clock of the received data and the phase of the frequency signal oscillated by the VCO 18 are completely synchronized, the value of c-b is zero. If the frequency or phase is out of phase, as indicated by the dotted line in Fig. 7, this becomes equal to c'-b ', and the clock phase error signal Pherr is determined by the subtraction process. Feedback control is executed so that this clock phase error signal (Pherr) is close to zero. As shown in Fig. 1, the clock phase error is fed back to the D / A converter 112, converted into an analog signal, and supplied to the LPF 113. The clock phase error converted into an analog signal is integrated in the LPF 113 and supplied to the VCO 18 as a clock phase control signal. In the VCO 18, the oscillation frequency signal is controlled based on the clock phase control signal and synchronized with the clock signal of the received data by the PLL. In this example, the level may be compared between two consecutive signals that are originally the same level, and if not, the level may be compared between two signals that are originally assumed to be the same level.
    [54] Further, according to the invention as set forth in claim 7, when the power is switched on or the channel is switched, all the data of the original same level matched between the sync signal and the code pattern in the packet data until the segment synchronization signal of the packet is detected and set. The difference value is continuously fed back to the VCO 18 as a clock phase error so that the clock reproduction can be completed quickly.
    [55] In this embodiment, the Nth of the packet data which is originally at the same level from the packet data which is the same data as the signal Segst indicating the position of the synchronization signal of the data sent out in the packet form and the signal Sdet indicating the synchronization signal in the code pattern. And the N + 1th synchronization signal is processed by subtraction, the clock phase error signal is determined and the clock regeneration process is executed to control the error to be zero.
    [56] In this configuration, even in a poor radio wave condition for receiving digital broadcasts, clock reproduction is stably realized with a very simple and inexpensive circuit configuration.
    [57] (Example 3)
    [58] 4 is a block diagram of an embodiment corresponding to claims 8, 9 and 10 of the present invention. This embodiment represents a digital broadcast demodulator, i.e., a digital broadcast demodulator for receiving digital broadcasts in which coded digital video and audio information has been transmitted in the form of packets, wherein in particular in a digital VSB transmission system, a synchronization signal is contained within received packet data. From the detected and detected signal indicating the position of the synchronization detection setting signal and the synchronization signal in the packet, the difference between the value of the synchronization signal and the reference value is calculated and thereby AGC is realized.
    [59] Referring to Fig. 4, the configuration and operation will be described below. The dotted line block 116 corresponds to the block synchronous detection setting circuit block shown in Embodiment 1, which is a block synchronous setting signal Shld indicating establishment of detection of the block synchronous signal in the received data, and a block within the packet. A segment start signal Segst indicating the position of the synchronization signal is output. Operation of block 116 is the same as described in Embodiment 1, and will be omitted. The digital data output Data from the A / D converter 12 is applied to the AGC error detection circuit 106.
    [60] FIG. 8 shows a four-part block synchronizing signal added to a start point of packet data. The block synchronization signal is mapped to values of ± 5 as shown in FIG. Since these are known values, at the receiving side, data values corresponding to ± can be treated as reference values. When the division synchronization setting signal Shld is input to the AGC error detection circuit 106, from the signal Segst indicating the position of the division synchronization signal in the packet, the positions of four symbols of data from the start of the division synchronization are specified. The difference between this value and the internal reference value is then determined. As shown in Fig. 8, when the received data is input as indicated by the dotted line, the difference from the reference value is as shown by d on the + side and d 'on the-side. The feed rack control is executed so that the differences d and d 'from the reference value are close to zero.
    [61] This shows a case where the received data larger than the reference value of the division synchronization signal is input, but when data smaller than the reference value is input, the code is not inverted by the subtraction process to increase the difference value by subtracting after the absolute value processing. The error signal Gerr is output as an AGC control signal. The AGC control signal Gerr is applied to the D / A converter 114 from the terminal 107 as shown in FIG. 1, converted into an analog signal, and supplied to the LPF 115. The AGC control signal integrated by the LPF 115 is fed back to the amplifier 4 and the tuner 2 via the switch circuit 111, and by feedback control, the amplitude of the received data is controlled to realize AGC.
    [62] According to the tenth aspect of the present invention, the division synchronization setting signal Shld output from the terminal 110 shown in FIG. 1 until the division synchronization signal in the packet data is detected and set when the power is turned on or the channel switching is performed. Is supplied to the switch circuit 111 to switch the AGC control signal between the control signal for detecting the amplitude error from the envelope of the analog signal and the control signal for detecting the amplitude error from the synchronization level by digital processing. When the received data is input, the amplitude error is detected from the envelope of the baseband signal by analog detection in the analog processing section at the front end until the block synchronization signal of the packet is set and based on this error, AGC control is first performed. After detecting and setting the intra-packet synchronous signal, the error signal is fed back from the digital processing for detecting the amplitude error from the synchronization signal, and the AGC is efficiently performed.
    [63] In the third embodiment, the signal Segst indicating the position of the synchronization signal of the data sent in the form of a packet and the signal Shld indicating the detection and setting of the synchronization signal are compared with the reference value of the division synchronization signal of the received data and the division signal. By the subtraction process, the amplitude error signal Gerr is determined, D / A converted, integrated by LPF, fed back through the switch circuit 111 to an analog amplifier and tuner, and thus amplitude is controlled so that the AGC Is realized. In this method, AGC can be stably realized with a very low cost circuit configuration even in a poor radio wave condition for receiving digital broadcast such as ghost and multipath.
    [64] In the above embodiments, the demodulator of terrestrial digital broadcasting is shown but may be applied to other applications.
    [65] The details of the number of symbols, the number of blocks, the configuration of the pulse parts, and the signal format can be changed or modified within the scope of the claims.
    [66] Of course, the operation of the individual circuits in embodiments may be realized by the processing of the microprocessor.
    [67] As described above, the digital broadcast demodulator of the present invention relates to digital terrestrial broadcasting of packet data and the like, and includes a synchronization pattern detection circuit, a synchronization detection protection counter circuit, and a synchronization detection unit that process code bits of received data and detect a synchronization signal pattern. Including the setting circuit, the correct synchronizing signal pattern is set and detected, and therefore, even in poor radio wave conditions such as strong ghost and multipath interference characteristics of digital terrestrial broadcasting, the synchronizing signal in the packet is stably set in a very low cost circuit configuration. And can be detected.
    [68] Also, by including the subtraction means for subtracting the received data, the level difference between the synchronization signals that are originally the same level is determined from the same code pattern detection signal as the synchronization signal and the signal indicating the position of the synchronization signal in the packet, thereby reducing the clock phase error of the reception data. It is fed back to the VCO for detection and control, thus ensuring stable clocks with very low cost circuitry, even under harsh radio wave conditions such as strong ghosts, multipath coherent nature of digital terrestrial broadcasts, and low C / N, and others. Can be played back precisely.
    [69] Furthermore, by subtracting the synchronization signal of the received data and the known reference value from the signal indicating the position of the synchronization signal in the received packet data and the signal for detecting and setting the synchronization signal in the packet data, an amplitude error is determined and the analog amplifier circuit and the tuner are determined. By controlling feedback, precise AGC is realized even in harsh radio wave environments.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] In the digital broadcast demodulator, which is a device that receives digital broadcast by transmitting digital video and audio information coded by a digital VSB modulation system in a packet form,
    And a circuit for setting a synchronization signal in the received data by most significant bit (MSB) indicating a positive or negative sign of the received transport packet data.
    [2" claim-type="Currently amended] 2. The circuit of claim 1, wherein the circuit for setting the synchronization signal in the received data is
    A sync code pattern detection circuit for detecting a block sync code pattern from the most significant bit signal of the received packet data;
    A symbol number counter circuit for counting the number of symbol data in the received packet data;
    A synchronization detection setting circuit for determining a correct division synchronization code pattern by obtaining the division synchronization code pattern from the synchronization code pattern detection circuit when the symbol number counter circuit has finished counting a specific number, and
    And a synchronization detection protection counter circuit for detecting and setting the division synchronization signal in the received data from an output of the synchronization code pattern detection circuit and a specified number of count-ups of the symbol number counter circuit.
    [3" claim-type="Currently amended] The digital broadcast demodulator according to claim 2, wherein the most significant bit signal of the received packet data is processed to output a signal indicating a start position of a synchronization signal in the data and a signal for detecting and setting the synchronization signal.
    [4" claim-type="Currently amended] Coded by the digital VSB modulation system by determining the difference value of the synchronization signal of the received packet data which should be originally at the same level, detecting the clock phase error of the transmission data, and regenerating the clock by phase control based on this phase error. And a device for receiving digital broadcast by transmitting the digital video and audio information in the form of a packet.
    [5" claim-type="Currently amended] 5. The method according to claim 4, wherein the difference between the N-th and N + 1-th (N> 1) sync signals, which must be essentially the same level, is determined from the code pattern detection signal of the sync signal and the signal representing the position of the sync signal. And a clock phase error detection circuit for outputting a clock phase error.
    [6" claim-type="Currently amended] The method of claim 4, wherein
    Circuitry for processing the difference of all received data,
    A circuit for detecting the difference value only for data that matches the code pattern of a synchronization signal, and
    And a circuit for detecting the difference value only for the data of the simultaneous signal.
    [7" claim-type="Currently amended] The clock is reproduced by detecting a clock phase error from a difference value of data that must be at the same original level as the synchronization signal code pattern of the reception data until the synchronization signal of the received packet data is detected and set. And a device for receiving digital broadcast by transmitting digital video and audio information encoded in the form of packets.
    [8" claim-type="Currently amended] Digital video and audio information coded by a digital VSB modulation system by detecting a synchronization signal in the received packet data, determining a difference between the detected data value of the synchronization signal and a reference, and realizing AGC based on this difference. And a device for receiving digital broadcast by transmitting a packet in the form of a packet.
    [9" claim-type="Currently amended] The synchronization signal according to claim 8, wherein a specific position of the synchronization signal is detected from a signal representing the detection and setting of the synchronization signal and a signal representing the position of the synchronization signal in the received data, and an error between the synchronization signal and the reference value at this specific position is detected. And an AGC error detection circuit output as a control signal.
    [10" claim-type="Currently amended] Until the synchronization signal of the received packet data is detected and set, AGC is realized by detecting an amplitude difference from the envelope of the analog detected baseband signal, and the digital video and audio information coded by the digital VSB modulation system is converted into a packet form. Digital demodulator characterized in that the device for receiving a digital broadcast by transmitting.
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    CN1178413C|2004-12-01|
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    CN1496035A|2004-05-12|
    JP2000115263A|2000-04-21|
    WO2000019645A1|2000-04-06|
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    US6967694B1|2005-11-22|
    TW435030B|2001-05-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-09-30|Priority to JP27718398A
    1998-09-30|Priority to JP98-277183
    1999-09-29|Application filed by 모리시타 요이찌, 마쯔시다덴기산교 가부시키가이샤
    2001-04-25|Publication of KR20010032615A
    2003-01-10|Application granted
    2003-01-10|Publication of KR100367636B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP27718398A|JP2000115263A|1998-09-30|1998-09-30|Digital broadcast demodulator|
    JP98-277183|1998-09-30|
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