• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method in which an external connection terminal is provided in a small diameter opening formed in a substrate. It is a subject to make it possible to mount a connection terminal on a board | substrate. To this end, the present invention is formed on the tape-shaped substrate 22, the semiconductor chip 23 mounted on the surface of the substrate 22, and the surface of the substrate 22 and electrically connected to the semiconductor chip 23. In the semiconductor device provided with the electrode film 25 connected and the plating bump 41 provided in the back surface of the board | substrate 22, and connected to the electrode film 25 through the opening 27 formed in the board | substrate 22. In the case where the plating bump 41 is formed on the electrode film 25 by plating, the maximum cross-sectional area of the plating bump 41 is S1, and the area of the opening 27 is S2. And S1 ≤ S2.
    公开号:KR20000076950A
    申请号:KR1020000015071
    申请日:2000-03-24
    公开日:2000-12-26
    发明作者:다까시마아끼라；안도후미히꼬；사또미쓰루；스즈끼다까시；구마가야요시까즈；고사까이가즈나리
    申请人:아끼구사 나오유끼；후지쯔 가부시끼가이샤；
    IPC主号:
    专利说明:

    Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME}
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device provided with an external connection terminal such as a solder ball in a small diameter opening formed in a substrate, and a method for manufacturing the same.
    In recent years, with the miniaturization and high density of semiconductor devices, many fine pitch ball grid arrays (BGA) which can cope with this have been used.
    In the fine pitch BGA, a semiconductor chip and a resin package overmolding the semiconductor chip are formed on the surface side of the substrate, and solder balls serving as external connection terminals are provided on the back side.
    Therefore, in order to further downsize and increase the density of the semiconductor device, it is necessary to narrow the ball pitch of the solder ball. In addition, high reliability is required for the semiconductor device, and thus it is necessary to maintain predetermined reliability while achieving narrow pitch of the solder balls.
    1 and 2 show semiconductor devices 1A and 1B having a general fine-pitch ball grid array (FBGA) structure. The semiconductor device 1A shown in FIG. 1 is a so-called overmolded BGA. This semiconductor device 1A is generally comprised by the board | substrate 2, the semiconductor chip 3, the resin package 8, the solder ball 10, etc. As shown in FIG.
    The board | substrate 2 consists of a resin film, and the semiconductor chip 3 is mounted in the upper part through the adhesive agent 4. Moreover, the opening part 7 is formed in the predetermined position of the board | substrate 2, and copper or gold (Au) is formed in the opening edge of the side in which the semiconductor chip 3 of this opening part 7 is mounted, for example. ), An electrode film 5 functioning as an electrode formed is formed. Therefore, the opening edge of one of the openings 7 is closed by the electrode film 5.
    Moreover, the via part 9 which consists of solder is formed in the inside of the opening part 7, The solder ball 10 is integrally joined to this via part 9. As shown in FIG. Therefore, the solder ball 10 is electrically connected with the electrode film 5 via the via part 9. This solder ball 10 functions as an external connection terminal and is formed to protrude from the substrate 2.
    In the overmolded semiconductor device 1A shown in FIG. 1, the semiconductor chip 3 and the electrode film 5 are connected by a wire 6. The resin package 8 is formed using, for example, a transfer molding method, and has a function of protecting the semiconductor chip 3, the electrode film 5, and the wire 6 described above.
    On the other hand, the semiconductor device 1B shown in FIG. 2 is a so-called flip chip type FBGA, and the electrode film 5 uses the stud bumps 11 (some may use solder bumps) formed on the semiconductor chips 3. It has a configuration in which flip-chip bonding is carried out. 2, the same code | symbol is attached | subjected about the component same as FIG.
    The semiconductor device 1A, 1B having the above-described FBGA structure uses the solder ball 10 as an external connection terminal. Therefore, the manufacturing process of this semiconductor device 1A, 1B has a ball mounting process which mounts the solder ball 10 to the board | substrate 2. As shown in FIG. 3 to 5 show a method (ball mounting method) for mounting the solder ball 10 that has been conventionally performed on the substrate 2. 3 to 5 exemplify the method for manufacturing the semiconductor device 1A shown in FIG. 1.
    In the ball mounting method shown in FIG. 3, a flux 12 (or solder paste) is applied to the solder ball 10 in advance, and the solder ball 10 is used as an opening 7 of the substrate 2. ). 4 shows a state in which the solder ball 10 is inserted into the opening 7.
    Conventionally, since the pitch (inter-ball pitch) between adjacent solder balls is relatively large about 0.8 mm, the diameter dimension L1 of the opening part 7 was also large (for example, 0.30 mm-0.40 mm). In addition, the diameter R of the solder ball 10 to be used is generally 0.40 mm to 0.50 mm. For this reason, when the solder ball 10 is inserted in the opening part 7, as shown in FIG. 4, the whole solder ball 10 is inserted in the opening part 7, or there are many parts where the solder ball 10 is large. It is inserted into the opening 7.
    After the solder ball 10 is inserted into the opening 7 as described above, the reflow process (heating process) is performed to melt the solder ball 10. However, as described above, the entirety of the solder ball 10 or Since many of the portions are inserted into the openings 7, the molten solder balls 10 reliably fill the openings 7 and join the electrode films 5. In addition, excess solder forms the solder ball 10 on the board | substrate 2 by surface tension. As a result, the semiconductor device 1A shown in FIG. 1 is formed.
    On the other hand, with the ball mounting method shown in FIG. 5, the solder paste 13 is first provided in the opening part 7 using the printing method (screen printing method) to the board | substrate 2. FIG. As mentioned above, since the diameter L1 of the opening part 7 was large conventionally, the solder paste 13 could be easily filled to the inside of the opening part 7 by performing screen printing. The solder paste 13 has a structure in which solder powder is mixed into a flux made of an organic material.
    Subsequently, the solder ball 10 is attached to the opening 7 filled with the solder paste 13, and a reflow process is performed. As a result, the organic components contained in the solder paste 13 are scattered, and the solder powder is melted to fill the openings 7. In addition, the solder balls 10 are also melted and joined to the solder in the openings 7, whereby the semiconductor device 1A shown in FIG. 1 is formed.
    By the way, in recent years, the density of the semiconductor chip 3 advances and there exists a tendency for the number of terminals to increase. In addition, with the miniaturization of electronic devices in which semiconductor devices are installed, there is a demand for further miniaturization of semiconductor devices.
    As a result, in recent years, the pitch between balls required for a semiconductor device has been reduced to about 0.5 mm. Thus, in order to make pitch between balls about 0.5 mm, the diameter dimension L1 of an opening part needs to be made small about 0.20 mm-0.25 mm, and the diameter dimension of a solder ball needs to be about 0.3 mm.
    As the ball mounting method of the semiconductor device designed to be densified in this manner, when the ball mounting method described with reference to FIGS. 3 and 4 is applied, the opening of the solder ball 10 in the opening 7 with respect to the solder ball diameter is determined. Since the diameter is small, the solder ball 10 cannot be fully inserted into the opening 7, and the space between the solder ball 10 and the electrode film 5 is largely separated. Therefore, even if the reflow process is performed, there arises a problem that the solder balls 10 and the electrode film 5 cannot be electrically connected.
    6 has shown the example which applied the ball mounting method demonstrated using FIG. 5 to the board | substrate 2 which made the diameter dimension L2 of the opening part 14 0.20 mm. As shown in Fig. 6A, when the diameter dimension L2 of the opening portion 14 is smaller than 0.20 mm to 0.25 mm, even if the solder paste 13 is to be provided in the opening portion 14 using the screen printing method. Therefore, the solder paste 13 cannot be sufficiently filled in the opening 14. That is, as shown, the solder paste 13 is in a state filled only in a predetermined range near the opening edge of the opening 14.
    When the solder ball 10 is mounted in the opening 14 in this state of charge and subjected to reflow treatment, as shown in FIG. 6 (B), the solder of the solder paste 13 is deposited on the molten solder ball 10. It is absorbed, and there is no solder in the opening part 14. Therefore, even if the ball mounting method shown in FIG. 5 is applied to the board | substrate 2 which has the opening part 14 with small diameter dimension L2, there existed a problem that the solder ball 10 could not be mounted suitably. In this way, a gap is formed between the solder ball 10 (external connection terminal) and the electrode film 5, and an electrical connection is not made.
    As shown in FIG. 7, the diameter L3 of the opening 7 decreases, so that the electrode pad 16 formed in the mounting substrate 15 on which the semiconductor device 1A is mounted (diameter in FIG. L4 is large with respect to the opening 7 (L3 < L4). In addition, solder plating 17 is applied to the electrode pad 16 in order to improve the bonding property with the solder ball 10.
    As described above, when the electrode pad 16 becomes large with respect to the opening 7, when the solder ball 10 and the solder plating 17 are melted by heat applied at the time of mounting, the molten solder ball 10 becomes the electrode pad. Absorbed by (16). For this reason, as shown in FIG. 8, in the opening part 7, the clearance gap which does not exist solder generate | occur | produced, and also there existed a problem that it became an open defect by this.
    Moreover, in the semiconductor device 1A of the conventional structure, when this is mounted on the mounting substrate 15, there also existed a problem that the crack 19 bunches in the via part 9, as shown in FIG. This crack is considered to occur due to the thermal expansion difference between the semiconductor chip 3 and the mounting substrate 15.
    Moreover, in the semiconductor device using a flexible printed circuit board (FPC) or a TAB tape board | substrate, it is common to fix a semiconductor chip to an FPC or TAB tape board | substrate with an adhesive agent. In a flip chip type semiconductor device in which the circuit formation surface of the semiconductor chip faces the substrate, an insulating adhesive is used. That is, an insulating adhesive is applied to the tape substrate on which the copper (Cu) pattern is formed, and after mounting the semiconductor chip, the adhesive is cured by heating to fix the semiconductor chip to the substrate. In this case, by accurately managing the application amount of the adhesive, the semiconductor chip can be fixed easily and reliably.
    The semiconductor chip is fixed with an adhesive and then sealed with a sealing resin. Since the tape substrate, the wiring pattern, the adhesive, the semiconductor chip, and the encapsulation resin are formed of different materials, the coefficients of linear expansion of these members differ from each other. In the above-described configuration of the semiconductor device, these members are in close contact with each other, and stresses due to the difference in linear expansion coefficients are generated between the members. Among these members, the wiring pattern is structurally weakest, and if stress is repeatedly acted upon by repetition of temperature change, a failure occurs that the wiring pattern portion is disconnected or the external terminal is broken.
    For example, an adhesive having a linear expansion rate of 10 to 16 [pm / ° C] (ppm / ° C means 10 × 10 -6 / ° C) and a sealing resin having a linear expansion rate of 6 to 10 [pm / ° C] Consider the case of using. Such a material generally has a low glass transition temperature (Tg), the glass transition temperature of the adhesive is 135 ° C to 145 ° C, and the glass transition temperature of the encapsulating resin is 130 ° C. The material with low glass transition temperature is generally a disadvantageous material with respect to pattern breaking. However, since the respective coefficients of linear expansion and the glass transition temperature are approximated, the thermal stress between these members can be moderated to some extent. Here, in the general material, when the glass transition temperature (Tg) is exceeded, the linear expansion rate is known to increase about 3 times or more. For this reason, when the high temperature side of the temperature cycle in the evaluation test of a semiconductor device is more than glass transition temperature, the thermal stress of each member will become very large, and the generation | occurrence | production time of the failure of disconnection etc. will be shortened extremely. However, because the coefficient of linear expansion and the glass transition temperature of each member are approximated, the stress generated at the interface of these members is small.
    On the other hand, for example, when using the adhesive whose linear expansion rate is 30-40 [pm / degreeC], and the sealing resin whose linear expansion rate is 12-16 [pm / degreeC], the glass transition temperature of a sealing resin is 210 It becomes quite high at ℃. If the glass transition temperature of the encapsulating resin is high, the warpage of the semiconductor device can be reduced, and there is an effect of improving the mounting reliability. However, since the coefficients of linear expansion of the adhesive and the encapsulation resin are significantly different, and the glass transition temperature is also quite low, the stress generated at the interface between the adhesive and the encapsulation resin becomes large. The likelihood of failure increases.
    The present invention has been made in view of the above-mentioned point, and the semiconductor which can reliably mount an external connection terminal to a board | substrate even if the pitch between terminals of an external connection terminal becomes small and the diameter dimension of the opening part formed in the board | substrate with this becomes small. It is an object to provide an apparatus and a method of manufacturing the same.
    It is also an object of the present invention to provide a semiconductor device having high reliability by suppressing the occurrence of breakage failure of the wiring pattern and breakage failure of the external terminal due to the difference between the coefficient of linear expansion of the adhesive and the coefficient of linear expansion of the component.
    1 is a diagram illustrating an example of a semiconductor device having a general FBGA structure.
    2 is a diagram illustrating an example of a semiconductor device having a general FBGA structure.
    3 is a view for explaining an example of a conventional method for manufacturing a semiconductor device.
    4 is a view for explaining an example of a conventional method for manufacturing a semiconductor device.
    5 is a diagram for explaining an example of a conventional method for manufacturing a semiconductor device.
    6 is a diagram for explaining a conventional problem.
    7 is a diagram for explaining a conventional problem.
    8 is a diagram for explaining a conventional problem.
    Fig. 9 is a view for explaining the cracks generated in the solder balls in the conventional mounting.
    FIG. 10 is a diagram for explaining a semiconductor device as a first embodiment of the present invention; FIG.
    11 is a view for explaining a method for forming a plating bump.
    12 is a view showing plating bumps grown more than necessary.
    FIG. 13 is a diagram for explaining a semiconductor device as a second embodiment of the present invention; FIG.
    14 is a view for explaining a method of forming a base electrode and a solder ball.
    15 is a diagram for explaining the semiconductor device as a third embodiment of the present invention;
    16 is a diagram for explaining a phenomenon that occurs when an inner wall thin film is not formed.
    Fig. 17 is an enlarged view of the vicinity of the inner wall thin film in the semiconductor device of the third embodiment of the present invention.
    18 is a view for explaining a method of filling solder paste in an opening.
    19 is a view for explaining a method of filling a solder paste in an opening.
    20 is a diagram for explaining the semiconductor device as a fourth embodiment of the present invention;
    Fig. 21 is a view for explaining the manufacturing method of the semiconductor device of the fourth embodiment of the present invention.
    Fig. 22 is an enlarged view of the vicinity of the adhesive of the semiconductor device of the fourth embodiment of the present invention.
    The figure for demonstrating the fillet in the case of using a low viscosity adhesive agent as an adhesive agent.
    24 is an enlarged view of the vicinity of an adhesive agent in a general semiconductor device.
    25 is a view showing the effect of the present invention.
    FIG. 26 is a view for explaining a method for equalizing the thickness of an adhesive; FIG.
    27 is a diagram for explaining a method for equalizing the thickness of an adhesive.
    28 is a diagram for explaining the semiconductor device as the fifth embodiment of the present invention;
    Fig. 29 is a view for explaining the linear expansion coefficient and the elastic modulus of the component parts of the semiconductor device according to the fifth embodiment of the present invention.
    30 is a view for explaining the coefficient of linear expansion and the glass transition temperature of the adhesive and sealing resin of the semiconductor device according to the fifth embodiment of the present invention.
    The figure for demonstrating the change of the linear expansion coefficient and elastic modulus at the time of adding an additive material to an adhesive agent.
    32 is a graph showing the relationship between the amount of additive added, the coefficient of linear expansion, and the modulus of elasticity;
    33 is a view for explaining a test result of a semiconductor device according to a fifth embodiment of the present invention.
    34 is a diagram for explaining a method for equalizing the thickness of an adhesive layer.
    35 is a view for explaining a method for equalizing the thickness of an adhesive layer.
    36 is a plan view of a substrate on which a deformation prevention pattern is formed.
    ※ Explanation of code about main part of drawing ※
    20B, 29D: semiconductor device
    22: substrate
    23: semiconductor chip
    25: electrode film (conductive film)
    27: opening
    28: Resin Package
    30: solder ball
    31: paste printing unit
    32: heating section
    33: Ball Mount
    34: printing mask
    36: squeegee
    41: plating bump
    42: base electrode portion
    43: inner wall thin film
    44: stenosis
    45: dispenser
    46: jig
    47A: filet
    55: spacer
    57: deformation prevention pattern
    60: adhesive
    62, 62A: additive
    64: dummy pattern
    MEANS TO SOLVE THE PROBLEM In order to solve the said subject, this invention is characterized by taking each means mentioned later.
    The invention described in claim 1,
    Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    The external connection electrode is formed on the electrode film by plating;
    The diameter of the portion protruding from the tape-shaped substrate of the external connection electrode is set to S1, and the diameter of the opening is set to S2, so that S1 S2.
    Moreover, invention of Claim 2 is
    The method of claim 1,
    At least one of nickel, copper, and gold is used as the material of the external connection electrode.
    In addition, the invention described in claim 3,
    Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    The external connection electrode,
    A first electrode portion formed directly on the electrode film and having a height smaller than a depth of the opening and larger than a central position of the opening; And
    One end portion is joined to the first electrode portion, and the other end portion is configured by a second electrode portion formed to protrude outward from the opening portion.
    In addition, the invention described in claim 4,
    In the semiconductor device according to claim 3,
    As a material of the first electrode portion, at least one of nickel, copper, and gold is used,
    Moreover, solder is used as a material of the said 2nd electrode part.
    In addition, the invention described in claim 5,
    Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    A thin film made of a material having good adhesion to the external connection electrode is formed on the inner wall of the opening.
    In addition, the invention described in claim 6,
    The semiconductor device according to claim 5, wherein the thin film is formed by plating,
    Moreover, at least any one of nickel, copper, and gold is used as the material.
    In addition, the invention of claim 7 is
    Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    When the diameter dimension of the opening portion is A and the thickness dimension of the tape substrate is B, the ratio (B / A) of the diameter dimension A of the opening portion and the thickness dimension B of the tape substrate is It is characterized by being comprised so that it may be 0.3 or less ((B / A) <= 0.3).
    In addition, the invention described in claim 8,
    A solder paste printing step of printing a solder paste on a resin substrate having an opening formed in a tape-shaped substrate on which a semiconductor chip is mounted, and having an opening formed by covering a conductive film at one edge of the opening, and loading the solder paste into the opening; And
    In the manufacturing method of the semiconductor device which has a ball mounting process which joins the said solder ball to the said electrode film by providing and heating the solder ball which becomes an external connection terminal after completion | finish of the said solder paste printing process,
    In the solder paste printing step, a printing process is performed such that the solder paste is deeply inserted to a position where the solder paste is in contact with the electrode film.
    In addition, the invention described in claim 9,
    Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An adhesive for fixing the semiconductor chip to the tape type substrate;
    An electrode film formed on the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device comprising an external connection electrode connected to the electrode film through an opening formed in the tape type substrate.
    The thickness of the adhesive from the tape substrate is set to 100 µm to 150 µm.
    In addition, the invention described in claim 10,
    In the manufacturing method of the semiconductor device which manufactures the semiconductor device of any one of Claims 1-9,
    A chip mounting step of mounting the semiconductor chip on the tape-shaped substrate is performed by attaching an adhesive to the tape-type substrate, then mounting the semiconductor chip on the adhesive, and then performing heat treatment to cure the adhesive. Equipped,
    Further, when the heat treatment is performed on the adhesive in the chip mounting step, the heat treatment is performed in a direction in which the semiconductor chip is located below the tape-shaped substrate.
    In addition, the invention described in claim 11,
    Wiring Board:
    A semiconductor device mounted on the surface of the wiring board:
    An adhesive for fixing the semiconductor element to the wiring board:
    An electrode film formed on the wiring board and electrically connected to the semiconductor element;
    A semiconductor device comprising a sealing resin encapsulating the semiconductor element and the electrode film,
    The linear expansion rate of the adhesive is made larger than the linear expansion rate of the semiconductor element and smaller than the linear expansion rate of the wiring board, and the linear expansion rate of the adhesive is approximated to the linear expansion rate of the encapsulating resin.
    In addition, the invention according to claim 12 is the semiconductor device according to claim 11,
    A strain preventing pattern for preventing unnecessary deformation of the wiring board may be formed at positions other than the position where the electrode film is formed.
    In addition, the invention according to claim 13 is the semiconductor device according to claim 11 or 12.
    The additive material is characterized in that it comprises particles having a particle size equal to the distance between the wiring board and the semiconductor element.
    Each said means acts as follows.
    According to the invention of claim 1,
    By forming the external connection electrode on the electrode film by plating, it is unnecessary to install the solder paste, to transfer the solder ball, and to perform the positioning process, as compared with the configuration using the solder ball. Can be facilitated and the cost can be reduced.
    Further, by configuring the diameter dimension S1 of the portion protruding from the tape-shaped substrate of the external connection electrode to be smaller than the diameter dimension S2 of the opening (S1 S2), the pitch between adjacent external connection electrodes can be reduced. have. Therefore, even if the semiconductor chip is densified and the number of external connection electrodes is increased, it is possible to cope with this. Further, as described above, S1 S2 can be realized by appropriately controlling the plating speed, the plating time, and the like of the external connection electrode.
    As described in claim 2, at least one of nickel, copper and gold can be used as a material of the external connection electrode.
    Moreover, according to invention of Claim 3,
    A first electrode portion formed directly on the electrode film and having a height smaller than the depth of the opening portion and larger than a central position of the opening portion, and formed such that one end portion is joined to the first electrode portion and the other end portion protrudes outward from the opening portion; By forming the external connection electrode by the two-electrode portion, when the second electrode portion is formed, it is in a state formed in the first electrode portion in the opening portion. Therefore, the second electrode portion and the electrode film can be electrically connected by bonding the second electrode to the first electrode portion.
    As described above, since the first electrode portion has a height that does not protrude from the opening portion, the distance between the first electrode portion and the second electrode portion becomes short when the second electrode portion is formed. Accordingly, the second electrode portion can be reliably connected to the first electrode portion, and no gap is formed between the first electrode portion and the second electrode portion. Therefore, the second electrode portion can be reliably connected to the first electrode portion (that is, the electrode film), so that the reliability of the semiconductor device can be improved.
    As described in claim 4, at least one of nickel, copper, and gold can be used as the material of the first electrode portion, and solder can be used as the material of the second electrode portion.
    Moreover, according to invention of Claim 5,
    By forming a thin film made of a material having good bonding property with the external connection electrode on the inner wall of the opening formed in the tape-shaped substrate, a gap is formed between the inner wall of the opening and the outer connection terminal in the opening. Can be prevented from occurring). Therefore, damages such as cracks and the like to the external connection terminals due to the constriction portion can be prevented and the reliability of the semiconductor device can be improved.
    That is, when the external connection electrode is formed in the opening in which a thin film made of a material having good adhesion to the external connection electrode is formed on the inner wall, the external connection terminal is bonded to the thin film (ie, the inner wall) in the opening. Therefore, no gap is generated between the external connection terminal and the opening, and the external connection terminal is firmly bonded to the inner wall of the opening, thereby preventing damage to the external connection terminal in the opening. can do.
    In addition, as described in claim 6, the thin film can be formed by plating, and at least one of nickel, copper, and gold can be used as the material.
    Moreover, according to invention of Claim 7,
    When the diameter dimension of the opening formed in the tape-shaped substrate is A and the thickness dimension of the tape-shaped substrate is B, the ratio (B / A) of the diameter dimension (A) of the opening and the thickness dimension (B) of the tape-shaped substrate Is set so that (B / A) ≤ 0.3 to prevent the occurrence of an open defect (a state in which a gap is formed between the external connection terminal and the electrode film and not electrically connected) between the external connection terminal and the electrode film. It is possible to cope with the higher density of the semiconductor chip, to maintain the strength of the tape type substrate itself, and to improve the strength of the external connection terminal.
    That is, as the diameter dimension A of the opening is increased, the strength of the external connection electrode in the opening is improved, and as the thickness dimension B of the tape type substrate is reduced, the external connection electrode in the opening is increased. Strength is improved. By the way, when the diameter dimension A and the thickness dimension B are independent of each other, the diameter dimension A of the opening is increased, and the thickness dimension B of the tape-shaped substrate is reduced. It becomes impossible (this is related to diameter dimension A), and the intensity | strength of the tape-shaped board | substrate itself falls (this is attributable to thickness dimension B).
    By the way, the diameter dimension (A) of the opening and the thickness dimension (B) of the tape-shaped substrate are correlated, and the diameter dimension (A) of the opening and the tape-type substrate are adjusted so that (B / A) ≤ 0.3 as described above. By setting the thickness dimension B, it is possible to suppress the occurrence of open defects due to the breakage of the external connection terminal, to cope with high density of the semiconductor chip, to maintain the strength of the tape-type substrate itself, and to The strength can be improved.
    Moreover, according to invention of Claim 8,
    In the solder paste printing process in which the solder paste is printed and filled in the openings formed in the tape-shaped substrate, the printing process is performed such that the solder paste is deeply inserted to the position where the solder paste is in contact with the electrode film. When joining the solder and the solder ball in the paste, no gap is formed between the two, so that the occurrence of an open defect can be suppressed. Thereby, the reliability of a semiconductor device can be improved.
    Moreover, according to invention of Claim 9,
    By setting the thickness of the adhesive used for mounting the semiconductor chip on the tape substrate to a thickness dimension of 100 µm to 150 µm, the external connection is caused due to the thermal expansion difference between the semiconductor chip and the mounting substrate after the semiconductor device is mounted on the mounting substrate. The terminal can be prevented from being damaged.
    That is, when the thermal expansion coefficients of the semiconductor chip and the mounting substrate are different, a large stress is concentrated on the external connection terminals due to the thermal expansion difference during heating, and in the worst case, there is a possibility that the external connection terminals are broken.
    By setting the thickness of the adhesive remodeled between the semiconductor chip and the tape substrate to a thickness dimension of 100 µm to 150 µm, the adhesive functions as a cushioning material, thus relieving stress concentrated on the external connection terminal. can do. As a result, damage to the external connection terminal due to the thermal expansion difference between the semiconductor chip and the mounting substrate can be prevented.
    Moreover, according to invention of Claim 10,
    When the heat treatment is performed on the adhesive in the chip mounting step, the semiconductor chip is subjected to heat treatment in a direction in which the semiconductor chip is located below, so that the self-weight of the semiconductor chip is reduced during the heat treatment. To space apart from the tape-like substrate. Thereby, an adhesive with a large thickness can be formed easily and reliably.
    Moreover, according to invention of Claim 11, the stress by the thermal expansion difference which acts on the wiring pattern located between a board | substrate and a semiconductor chip can be reduced by optimizing the linear expansion coefficient of an adhesive agent. Therefore, disconnection and breakage failure of the wiring pattern can be suppressed, and high mounting reliability can be achieved.
    According to the invention of claim 12, by forming a strain preventing pattern for preventing unnecessary deformation of the wiring board at positions other than the position where the electrode film is formed, it is possible to prevent an unbalance from occurring in the thickness of the adhesive. Therefore, it is possible to reliably suppress the disconnection failure of the wiring pattern.
    According to the invention described in claim 13, the thickness of the adhesive layer can be made a predetermined uniform thickness by adding particles having a particle size equal to the distance between the wiring board and the semiconductor element to the adhesive. Therefore, unnecessary deformation of the wiring board can be prevented, and it is possible to reliably suppress the breakage of the wiring pattern.
    Embodiment
    EMBODIMENT OF THE INVENTION Next, embodiment of this invention is described with drawing.
    FIG. 10 is an enlarged cross-sectional view showing a main part of a semiconductor device 20A as a first embodiment of the present invention. As shown in the figure, the semiconductor device 20A according to the present embodiment has a package structure of the FBGA type, and thus fine pitch is achieved. This semiconductor device 20A is generally a tape-shaped substrate 22 (hereinafter simply referred to as a substrate 22), a semiconductor chip 23, a wire 26, a resin package 28, and a plating bump 41 ( External connection terminal) or the like.
    The substrate 22 is composed of a resin tape 48 and an electrode film 25. The resin tape 48 is, for example, a resin tape such as polyimide, and the semiconductor chip 23 is mounted on the surface 22A through the adhesive 24A.
    Moreover, the opening part 27 is formed in the predetermined position of the board | substrate 22, and copper or gold (Au) is formed in the opening edge of the side in which the semiconductor chip 23 of this opening part 27 is mounted, for example. ) Is formed by plating, and an electrode film 25 that functions as an electrode is formed. Therefore, the opening edge on the surface 22A side of the opening 27 is closed by the electrode film 25. In addition, in forming the opening part 27, it can form easily, for example by performing a laser process with respect to the board | substrate 22. FIG.
    When the semiconductor chip 23 is mounted on the mounting surface 22A, in this embodiment, the semiconductor chip 23 is mounted so as to face up. Therefore, the circuit formation surface of the semiconductor chip 23 is located in the upper part of the figure, and the pad to which the wire 26 is bonded is also located in the upper part of the semiconductor chip 23.
    One end of the wire 26 is bonded to a pad formed above the semiconductor chip 23, and the other end is bonded to the electrode film 25. In addition, the resin package 28 is formed using the transfer molding method, for example, and has the function of protecting the semiconductor chip 23, the electrode film 25, the wire 26, and the like.
    The plating bump 41 functions as an external connection terminal. In this embodiment, at least one of nickel, copper, and gold is grown on the electrode film 25 using the plating method. The plating method used at this time can also use either an electroplating method or an electroless plating method.
    FIG. 11A shows the state where the plating bump 41A is formed to the electrode film 25 for a predetermined time, and the plating bump 41A is formed up to the position of the predetermined height in the opening 27. As shown in the figure, the plating bumps 41A grow to fill the opening 27.
    11B shows an enlarged view of the plating bumps 41 in the state where the plating process is completed. As shown in the figure, at the time when the plating process is completed, the plating bumps 41 are configured to protrude outward from the openings 27 by a predetermined amount. In addition, in this embodiment, the diameter dimension S1 in the site | part which protruded from the board | substrate 22 of the formed plating bump 41 becomes small with respect to the diameter dimension S2 of the opening part 27 (S1 <S2). Is composed).
    The diameter dimension S1 at the portion projecting from the substrate 22 of the plating bump 41 can be realized by controlling the plating speed, the plating time, and the like when the plating bump 41 is plated. Specifically, for example, when the plating time is set longer than the formation time of the plating bumps 41 shown in FIG. 11 (B), plating is further performed on the outer peripheral portion of the plating bumps 41 shown in FIG. 11 (B). This is performed continuously, and the plating bump 41B as shown in FIG. 12 is formed. The diameter dimension at the site | part which protruded from the board | substrate 2 of this plating bump 41B becomes the magnitude | size shown by the arrow S3 in a figure, and becomes large with respect to the diameter dimension S2 of the opening part 27 (S3>). S2).
    By the way, when the diameter dimension S3 of the site | part which protruded from the board | substrate 2 of the plating bump 41B becomes large, the separation distance (pitch) of each adjacent plating bump 41B inevitably becomes large. On the other hand, in this embodiment, the diameter dimension S1 in the site | part which protruded from the board | substrate 2 of the plating bump 41 becomes small with respect to the diameter dimension S2 of the opening part 27, including the same case. It is configured. For this reason, the pitch between adjacent plating bumps 41A can be made small, and accordingly, even if the number of plating bumps 41A increases because the semiconductor chip 23 becomes high, it can fully cope with this.
    In this embodiment, by using the plating bumps 41 formed by the plating method as the external connection terminals, the solder paste required for the use of the solder balls, the installation processing of the solder balls, the transfer of the solder balls, and the positioning processing are unnecessary. can do. Therefore, the formation process of the plating bump 41 can be facilitated, and the cost can be reduced.
    Next, a second embodiment of the present invention will be described.
    13 and 14 are diagrams for explaining the semiconductor device 20B according to the second embodiment. FIG. 13 is an enlarged cross-sectional view of the main part of the semiconductor device 20B, and FIG. 14 is a view for explaining a bonding method of the solder balls 30.
    In addition, in FIG. 13 and FIG. 14, the same code | symbol is attached | subjected about the same structure as the semiconductor device 20B which concerns on 1st Example demonstrated using FIGS. 10-12, and the description is abbreviate | omitted. The same applies to each of the embodiments described with reference to FIGS. 15 to 24.
    In the present embodiment, the external connection terminal is constituted by the solder ball 30 (second electrode portion) and the base electrode portion 42 (first electrode portion).
    As described above, when the semiconductor device becomes denser and the opening diameter decreases with this, the solder balls cannot be sufficiently inserted into the openings, resulting in open defects. This open defect is attributable to the large distance between the solder ball and the electrode film when the solder ball is attached to the opening.
    In the present embodiment, the base electrode portion 42 is directly formed in the electrode film 25 before the solder ball 30 is provided. As the base electrode portion 42, at least one of nickel, copper, and gold having high bonding properties with the solder balls 30 can be used.
    In addition, since the plating method requires a long time for the formation process, the height of the base electrode portion 42 is preferably as small as possible in terms of improving throughput. Moreover, it is preferable that the height of the base electrode part 42 is as high as possible from the surface which reliably bonds the solder ball 30 with the electrode film 25. As shown in FIG. By the way, in this embodiment, the height (shown by arrow B1 in FIG. 14 (A)) of the base electrode part 42 from the electrode film 25 is indicated by the arrow in the depth of the opening 27 (FIG. 14 (A)). It is smaller than B) and is set larger than the central position of the opening 27 (indicated by the arrow B2 in Fig. 14A) (B2 &lt; B1 &lt; B).
    By setting it as such a structure, when installing the solder ball 30 in the opening part 27, as shown to FIG. 14 (A), the space | interval distance of the solder ball 30 and the base electrode part 42 is short, and is in substantially contacting state. It is. Therefore, in the subsequent heat treatment, as shown in Fig. 14B, the solder balls 30 are securely bonded to the base electrode portions 42, so that the solder balls 30 and the base electrode portions are secured. A gap is not formed between 42 and. Therefore, the solder ball 30 can be reliably connected to the electrode film 25 via the base electrode part 42, and the reliability of the semiconductor device 20B can be improved.
    Next, a third embodiment of the present invention will be described.
    15 and 17 are diagrams for explaining the semiconductor device 20C which is the third embodiment. FIG. 15 is an enlarged cross-sectional view showing a main part of the semiconductor device 20C, and FIG. 16 is a view for explaining a narrowing phenomenon that has conventionally occurred, and FIG. 17 shows a vicinity of the inner wall thin film 43 of the semiconductor device 20C. It is an enlarged drawing.
    The first aspect of the semiconductor device 20C according to the present embodiment is that the inner wall thin film 43 is formed on the inner wall of the opening 27 formed in the substrate 22. In addition, when the diameter dimension of the opening part 27 is A and the thickness dimension of the board | substrate 22 is B, the ratio of the diameter dimension A of the opening part 27 and the thickness dimension B of the board | substrate 22 is ratio. The second feature is that (B / A) is configured such that (B / A) ≤ 0.3.
    Also. The structure by this 1st characteristic and the structure by 2nd characteristic are each independently exhibiting the effect of below-mentioned, and it is not necessary to necessarily provide both to one semiconductor device simultaneously.
    First, the inner wall thin film 43 which is a 1st characteristic is demonstrated. The inner wall thin film 43 is made of a material having both good bondability with solder which is the material of the solder ball 30 and good bondability with PI, which is the material of the substrate 22. Specifically, at least one of nickel, copper, and gold can be used as the material of the inner wall thin film 43.
    Moreover, the inner wall thin film 43 needs to be formed in the inner wall part of the opening part 27 which is a fine small hole. By the way, the inner wall thin film 43 can be easily formed in the inner wall part of the opening part 27 by using a plating method. It is preferable that the film thickness of this inner wall thin film 43 is about 0.5 micrometer-about 10 micrometers, for example.
    As in this embodiment, by forming the inner wall thin film 43 having the above characteristics on the inner wall of the opening 27, it is possible to prevent the constriction 44 from occurring in the via portion 29 in the opening 27. . Here, the constriction part 44 is demonstrated using FIG.
    As shown in the same figure, the constriction part 44 is a site | part narrower than diameter dimension A of the opening part 27 which generate | occur | produces in a part of via part 29 in opening part 27 (it is shown by arrow L5 in drawing). Say. Therefore, when the constriction 44 is formed, a gap 49 is generated between the via portion 29 (solder ball 30) and the inner wall portion of the opening 27.
    Therefore, as a matter of course, if a gap 49 is formed between the via portion 29 (the solder ball 30) and the opening 27, the strength of the via portion 29 (the solder ball 30) decreases, In the worst case, cracks occur in the constriction portion 44 or peeling occurs between the via portion 29 and the electrode film 25.
    The reason for the formation of the constriction portion 44 is not clear, but the connection between the substrate 22 and the via portion 29 (the solder ball 30) is poor and the diameter dimension A of the opening portion 27 (that is, the area). ) And mismatch between the thickness B of the substrate 22 (that is, it is not qualified) and the like are estimated to have an influence.
    The above-mentioned inner wall thin film 43 aims at especially eliminating the above-mentioned cause of generation of the narrowing part. That is, when the inner wall thin film 43 made of a material having good adhesion to the via portion 29 (solder ball 30) is formed on the inner wall of the opening 27, the via portion 29 and the solder are formed in the opening 27. When the ball 30 is formed, the via portion 29 and the solder ball 30 are firmly bonded to the inner wall thin film 43 (that is, the inner wall of the opening 27).
    As a result, a gap (that is, a constriction 44) does not occur between the via portion 29 and the solder ball 30 and the opening 27, and the via portion 29 and the solder ball 30 The state is firmly bonded to the inner wall of the opening 27. Therefore, cracks may occur in the via portion 29 and the solder ball 30 in the opening 27, and peeling between the via portion 29 and the electrode film 25 can be prevented. The reliability of the semiconductor device 20C can be improved.
    Next, the relationship between the thickness dimension B of the board | substrate 22 which becomes a 2nd characteristic, and the diameter dimension A of the opening part 27 is demonstrated. In this embodiment, the second feature is that the ratio (B / A) between the diameter dimension A of the opening 27 and the thickness dimension B of the substrate 22 is (B / A) ≤ 0.3. It is.
    Here, the influence that the diameter dimension A of the opening part 27 contributes to joining the via part 29 and the solder ball 30 to the opening part 27, and the thickness dimension B of the board | substrate 22 are the via part (29) and the influence which contributes to joining the solder ball 30 to the opening part 27 are considered separately.
    First, considering the influence that the diameter dimension A of the opening 27 contributes to joining the via portion 29 and the solder ball 30 to the inner wall of the opening 27, the diameter dimension A of the opening 27 is considered. ), The strength of the via portion 29 and the solder ball 30 in the opening 27 is improved. This is because the larger the diameter dimension A of the opening 27 is, the larger the cross-sectional area of the via 29 and the solder ball 30 in the opening 27 is.
    In addition, considering the influence that the thickness dimension B of the substrate 22 contributes to joining the via portion 29 and the solder ball 30 to the opening 27, the thickness dimension B of the substrate 22 As it becomes smaller, the strength of the via portion 29 and the solder ball 30 in the opening 27 is improved. This is because the smaller the thickness dimension B of the substrate 22 is, the shorter the distance between the solder ball 30 and the electrode film 25 is.
    In this case, the diameter dimension A and the thickness dimension B are independent of each other, the diameter dimension A of the opening 27 is increased, and the thickness dimension B of the substrate 22 is reduced. Assuming that the semiconductor chip 23 cannot cope with a higher density (corresponding to the diameter dimension A), the strength of the substrate 22 itself decreases (due to the thickness dimension B).
    By the way, the diameter dimension of the opening 27 has a correlation between the diameter dimension A of the opening 27 and the thickness dimension B of the substrate 22, and the diameter dimension of the opening 27 is (B / A) ≤ 0.3 as described above. By setting the A and the thickness dimension B of the substrate 22, the densification of the semiconductor chip 23 and the substrate (while suppressing the occurrence of open defects due to breakage of the via portion 29 and the solder ball 30) are performed. 22, the strength can be improved.
    25 shows the results of experiments carried out by the present inventors. In the same figure, Example 1, 2, 3 which satisfy | fills the conditions of said (B / A) <= 0.3 is shown with the comparative examples 1 and 2 which do not satisfy the condition of (B / A) <= 0.3. In addition, in Example 3, the mounting pitch of the solder balls is 0.8 mm, and in each other example, the mounting pitch of the solder balls is 0.5 mm.
    From the drawings, it can be seen that in Examples 1, 2, and 3 in which (B / A) In addition, despite the installation pitch of the solder balls, it is understood that the generation of defective products is suppressed by satisfying the condition of (B / A) ≤ 0.3. Therefore, by forming the ratio (B / A) of the diameter dimension (A) of the opening portion 27 and the thickness dimension (B) of the substrate 22 to be (B / A) ≤ 0.3, the occurrence of open defects is prevented. Prove that you can.
    Next, the manufacturing method of the semiconductor device which is 3rd Example of this invention is demonstrated. 18 shows a semiconductor device manufacturing apparatus used in the manufacturing method of the present embodiment. Hereinafter, the manufacturing method of the semiconductor device which concerns on a present Example is demonstrated with description of the structure of the manufacturing apparatus shown in FIG.
    The semiconductor manufacturing apparatus shown in FIG. 18 is generally comprised by the paste printing part 31, the ball mounting part 33, etc. In FIG.
    The paste printing part 31 has the printing mask 34, the skid 35, and the heater 36. When the substrate 22 on which the semiconductor chip 23, the resin package 28, and the like are mounted is mounted on the paste printing unit 31, the mask 34 for printing is mounted on the substrate 22, and the skid 35 is formed. The printing process of the solder paste 13 is performed by this.
    At this time, the heater 36 heats the area where printing is performed, and thus the printing process is performed under a heating atmosphere. The heating temperature at this time is set at a temperature such that the solder paste 13 can be softened, in other words, a temperature at which the solder paste 13 has a softening degree that is easy to fill in the opening 27.
    Moreover, the mask hole is formed in the printing mask 34 in the position which opposes the opening part 27 formed in the board | substrate 22, Therefore, the solder paste 13 prints in the opening part 27 by performing the said printing process. (Solder paste printing step).
    In this embodiment, in the solder paste printing step, the printing process is performed such that the solder paste 13 is deeply inserted to the position where the solder paste 13 is in contact with the electrode film 25 located deep in the opening 27. Specifically, the solder paste 13 is deeply inserted to the depth of the opening 27 by optimizing the pressing force, the inclination angle, and the like of the skid 35 to the printing mask 34. have.
    In addition, as described above, the printing process is performed under a heating atmosphere in which the solder paste 13 is softened, whereby the solder paste 13 can also be inserted deep into the opening 27. In addition, the pressing force, inclination angle, etc. of the skid 35 change with the magnitude | size of the board | substrate 22, the viscosity of the solder paste 13, the heating temperature by the heater 36, etc. By each of these parameters, the pressing force, the inclination angle, and the like of the skid 35 are appropriately set.
    When printing of the solder paste 13 is complete | finished in the paste printing part 31, the board | substrate 22 on which the solder paste 13 was printed is conveyed to the ball mounting part 33 by the conveying apparatus which is not shown in figure. This ball mounting part 33 is provided with the ball conveying fixture 37 which conveys the solder ball 30. As shown in FIG. This ball conveying fixture 37 has a suction hole in the position corresponding to the opening part 27 formed in the board | substrate 22, and it is set as the structure which can vacuum-suction the solder ball 30 in this suction hole.
    Then, the ball conveying fixture 37 is positioned with the substrate 22 and then lowered, and the solder ball 30 is provided above the opening 27 (ball mounting step). 19A illustrates a state where the solder ball 30 is provided on the upper portion of the opening 27 (upper portion of the solder paste 13).
    As described above, in the solder paste printing step, the solder paste 13 is deeply inserted into the opening 27 formed in the substrate 22 to a position where the electrode film 25 is in contact with the electrode layer 25. Therefore, after the solder ball 30 is provided on the opening 27 in the ball mounting step, as shown in Fig. 19A, the solder ball 30 is in direct contact with the solder paste 13, so that both The gap is not formed between the gaps.
    Subsequently, by the conveying apparatus which is not shown in figure, the board | substrate 22 returns to the paste printing part 31 again, and the heat processing which melts the solder in the solder ball 30 and the solder paste 13 is performed. Thereby, the solder ball 30 and the via part 29 are formed, as shown to FIG. 19 (B). In addition, in the melting process with respect to the solder ball 30 and the solder paste 13, the said printing mask 34, the skid 35, etc. are comprised so that it may retract from the paste printing part 31. FIG. .
    As described above, in the present solder paste printing step, the solder paste 13 is deeply inserted to the position where the electrode paste 25 is in contact with the electrode film 25 of the opening 27, so that the solder ball ( 30 and the via portion 29, when forming the via portion 29, the open defect between the via portion 29 and the electrode film 25, and between the solder ball 30 and the via portion 29 is surely generated. It can prevent. Thereby, the reliability of the manufactured semiconductor device can be improved.
    Next, a fourth embodiment of the present invention will be described.
    20 is an enlarged cross-sectional view showing a main part of a semiconductor device 20D which is a fourth embodiment of the present invention. The same figure shows a state in which the semiconductor device 20D is mounted on the mounting substrate 50.
    The semiconductor device 20D according to the present embodiment has a thickness of 100 μm (indicated by arrow W in the drawing) of the adhesive 24B used as the die attaching material when the semiconductor chip 23 is mounted on the substrate 22. The thickness is set to a thickness dimension of ˜150 μm.
    In this embodiment, although the adhesive agent 24B which has such a thickness dimension is formed, the method mentioned later in the chip mounting process is used. That is, as shown in Fig. 21A, first, the adhesive 24B is provided at the chip mounting position on the substrate 22 using the dispenser 45.
    At this time, since the adhesive agent 24B has higher viscosity and higher thixotropy than the adhesive agent used normally, as described later, it is provided with a predetermined thickness without spreading widely. In addition, when installing this adhesive agent 24B, the structure which prevents the expansion of the adhesive agent 24B may be provided in advance on the board | substrate 22 by dam 51 (it shows with a dashed-dotted line in drawing). .
    When the installation process of the adhesive agent 24B is completed as mentioned above, the semiconductor chip 23 is mounted on the adhesive agent 24B continuously. Then, heat treatment is performed to cure the adhesive 24B. However, in this embodiment, when the heat treatment is performed, as shown in FIG. 21 (B), the semiconductor chip 23 is lowered with respect to the substrate 22. The heat treatment is performed in a direction positioned at.
    Moreover, at this time, the jig | tool 46 is provided in parallel with the board | substrate 22, and heat processing is performed. The separation distance H between the substrate 22 and the jig 46 is a distance between the substrate 22 and the semiconductor chip 23 in the state where the semiconductor chip 23 is in contact with the jig 46. Among them, the arrow W is configured so as to be equal to the predetermined thickness dimension (100 µm to 150 µm) of the adhesive 24B.
    Thereby, the self weight of the semiconductor chip 23 at the time of heat processing acts to isolate the semiconductor chip 23 from the board | substrate 22. As shown in FIG. Thereby, large adhesive 24B can be formed easily and reliably. Moreover, since the board | substrate 22 and the jig | tool 46 are comprised so that it may have high parallelism, the thickness dimension W of the adhesive agent 24B hardened | cured after heat processing is uniform thickness in the whole installation position. Becomes
    As in this embodiment, the thickness W of the adhesive agent 24B is set to a thickness dimension of 100 µm to 150 µm, so that the semiconductor device 20D is mounted on the mounting substrate 50, and then the semiconductor chip 23 and It is possible to prevent the solder ball 30 from being damaged due to the difference in thermal expansion of the mounting substrate 50 (usually, the thermal coefficient of thermal expansion of the semiconductor chip 23 is about 4 ppm, and the thermal expansion of the mounting substrate 50 is also achieved. Modulus is about 16 ppm). This reason will be described below.
    If the thermal expansion coefficients of the semiconductor chip 23 and the mounting substrate 50 are different, in the heat treatment performed when the semiconductor device 20D is mounted on the mounting substrate 50 or the like, solder balls ( A large stress is applied to 30). In the worst case, the solder ball 30 is broken due to this stress, and the solder ball 30 is peeled off from the substrate 22 or the mounting substrate 50.
    By the way, the adhesive agent 24B is set by setting the thickness of the adhesive agent 24B remodeled between the semiconductor chip 23 and the board | substrate 22 to the thickness dimension of 100 micrometers-150 micrometers like this embodiment. It can function as a shock absorber. As a result, stress concentrated on the solder ball 30 can be alleviated, and damage to the solder ball 30 due to the thermal expansion difference between the semiconductor chip 23 and the mounting substrate 50 can be prevented. The mounting reliability of the semiconductor device 20D can be improved.
    Here, attention will be given to the fillet 47A formed on the adhesive agent 24B, which will be described below. The fillet 47A refers to a curved portion that the adhesive 24B forms on the side surface portion of the semiconductor chip 23 when the semiconductor chip 23 is mounted on the substrate 22 by the adhesive 24B (FIG. 22).
    In this embodiment, the height of the side surface 23A of the semiconductor chip 23 is set to T, and the height at the lower end surface of the semiconductor chip 23 of the fillet 47A on which the adhesive 24B is formed is set to t1. In this case, the height t1 of the fillet 47A is configured such that (0.2 x T) &lt; = t1 &lt; (0.6 x T). As described above, by setting the height t1 of the fillet 47A to satisfy the condition of (0.2 x T) &lt; = t 1 &lt; (0.6 x T), the semiconductor device 20D can be miniaturized. This reason will be described below.
    The height t of the fillet 47A of the adhesive agent 24B has a relationship with the installation area of the adhesive agent 24B on the substrate 22. That is, as shown in FIG. 22, the fillet 47A is formed in a curved shape toward the side surface 23A of the semiconductor chip 23 on the surface 22A of the substrate 22, and thus the semiconductor chip of the fillet 47A. As the height t1 at the lower side of the side surface of the 23 is larger, the curved shape is formed longer, so that the amount of protrusion of the adhesive 24B protruding on the outer periphery of the semiconductor chip 23 on the substrate 22 (Fig. 22). The amount indicated by arrow X1) becomes large.
    In addition, other components (for example, an electrode film, a wire, etc.) cannot be provided in the site | part in which the adhesive agent 24B was provided on the board | substrate 22. FIG. Therefore, when the height t of the fillet 47A of the adhesive agent 24B becomes large, the semiconductor device 24D will be enlarged.
    By the way, in this embodiment, the height t1 at the lower end of the side surface of the semiconductor chip 23 of the fillet 47A is set small as (0.2 x T) &lt; = t1 &lt; (0.6 x T). For this reason, since the protrusion amount X1 which the adhesive agent 24B protrudes on the outer periphery of the semiconductor chip 23 becomes small, therefore, the board | substrate 22 can be miniaturized, and also the semiconductor device 20D can be miniaturized. .
    Here, the characteristic of the adhesive agent 24B used by a present Example is demonstrated.
    As for the adhesive agent 24B used in the present Example, the adhesive agent which has high viscosity and high thixotropy is selected compared with the adhesive agent 4 generally used as a die attaching material conventionally. Specifically, in the conventional adhesive 4, the viscosity was 5000 cps to 30000 cps and the thixotropy was 4.0 to 6.0. In the adhesive 24B used in the present embodiment, the viscosity is 30000 cps to 70000 cps and the thixotropic property. The 1.0 to 4.0 thing is used.
    FIG. 23 shows the shape of the fillet 47B when the adhesive 4 used in the past is used and the thickness W1 of the adhesive 4 is set to a thickness dimension of 100 µm to 150 µm. As shown in the same figure, in the adhesive agent 4 which has the conventional low viscosity and low thixotropy, the fluidity | liquidity of the adhesive agent 4 is high, and therefore, the height t2 in the lower side of the side surface of the semiconductor chip 23 of the fillet 47B. ) Is approximately equal to the height T of the semiconductor chip 23 (t 2 ≒ T).
    Therefore, as shown in FIG. 23, even if the adhesive 4 used conventionally is used as it is, and the thickness of an adhesive agent may be made thick as 100 micrometers-150 micrometers like this embodiment, the semiconductor chip 23 of the fillet 47B is carried out. Height t2 at the lower side of the side surface of the side) becomes large. For this reason, the curved shape of the fillet 47B becomes long, and therefore the protrusion amount (the amount indicated by arrow X2 in FIG. 23) of the adhesive agent 4 protruding on the outer circumference of the semiconductor chip 23 on the substrate 22 is increased. This increases the size of the semiconductor device.
    On the other hand, in the present embodiment, since the adhesive 24B having high viscosity and high thixotropy is used as described above, even when the thickness W of the adhesive 24B is set to a thickness dimension of 100 µm to 150 µm, The height t1 of the fillet 47A can be made small, thereby miniaturizing the semiconductor device 20D.
    In addition, as shown in FIG. 24, when the thickness W2 of an adhesive agent is thin, since the fillet 47C formed is originally small, the protrusion amount X3 of the adhesive agent 4 which protrudes on the outer periphery of the semiconductor chip 23 is X3. ) Is also small. Therefore, when the thickness W2 of an adhesive agent is thin, the influence which the fillet 47C has on miniaturization of a semiconductor device is small.
    In addition, when using the adhesive agent 24B as a member which relieves stress concentration as mentioned above, the elasticity modulus and thermal coefficient of thermal expansion of the adhesive agent 24B also become an important factor.
    That is, when the adhesive agent 24B is made of a material having high elastic modulus (that is, a hard material hard to deform), the stress generated due to the thermal expansion difference between the semiconductor chip 23 and the mounting substrate 50 is the adhesive agent 24B. ), The solder ball 30 may be broken or peeled off.
    In addition, when the thermal expansion coefficient of the adhesive agent 24B is very small with respect to the thermal expansion coefficient of the semiconductor chip 23, or when the thermal expansion coefficient of the mounting substrate 50 is very large, the adhesive agent 24B and the semiconductor chip 23 are used. ) And a new stress due to the thermal expansion difference is generated between the adhesive 24B and the mounting substrate 50, and the solder ball 30 cannot be protected again.
    By the way, in the present Example, the elasticity modulus was 200kgf / mm <2> -800kgf / mm <2> and the linear expansion coefficient was 6 * 10 <-6> / degreeC / 15 * 10 <-6> / degreeC as the adhesive agent 24B. This prevented damage or peeling of the solder balls 30.
    On the other hand, in the semiconductor device 20D according to the present embodiment, the adhesive agent 24B is formed to have a constant thickness as described with reference to Fig. 21B. Specifically, the adhesive agent 24B is formed to have a uniform thickness within an error range of ± 20 μm. Thus, by making adhesive 24B constant thickness, the deflection of the stress which arises in adhesive 24B can be suppressed.
    That is, if an imbalance exists in the thickness of the adhesive 24B, a difference occurs in the stress generated between the thick portion and the thin portion. Therefore, due to the thickness imbalance, stress concentration occurs in a particularly thin portion, and problems such as peeling off of the adhesive 24B occur in this portion. Therefore, the stress which concentrates on the solder ball 30 also cannot be effectively performed. By equalizing the thickness of the adhesive 24B as in the present embodiment, the deflection of the stress generated in the adhesive 24B can be prevented, so that the peeling of the adhesive 24B can be prevented and the solder can be prevented. The ball 30 can be protected reliably.
    As mentioned above, it is important to equalize the thickness of the adhesive agent 24B. The method for equalizing the thickness of the adhesive 24B is not limited to the method described using Fig. 21 (B). For example, as shown in Fig. 26, the particle size of the adhesive 24B is 100 µm to 150. It can also be realized by adding a spherical spacer 55 having a thickness of 占 퐉. Also in this case, the thickness of the adhesive agent 24B is made uniform as mentioned above, and therefore the peeling prevention of the adhesive agent 24B and the protection of the solder ball 30 can be aimed at.
    In addition, the thickness imbalance of the adhesive agent 24B also arises by the deformation | transformation of the board | substrate 22. FIG. Therefore, it is also important to prevent deformation in the substrate 22. As a method for preventing the deformation of the substrate 22 from occurring, for example, as shown in FIG. 27, deformation to prevent the occurrence of unnecessary deformation of the substrate 22 at a position other than the formation position of the electrode film 25. The structure which forms the prevention pattern 57 can be considered.
    This deformation prevention pattern 57 may be formed collectively at the time of forming the electrode film 25 (in this case, the deformation prevention pattern 57 is made of the same material as the electrode film 25), and It is also possible to set it as the structure formed separately (in this case, the deformation prevention pattern 57 can be formed from the material suitable for deformation prevention). In this way, by providing the deformation preventing pattern 57, the deformation of the substrate 22 can be suppressed, and thus an unbalance can be prevented from occurring in the thickness of the adhesive 22. Therefore, the peeling prevention of the adhesive agent 24B can be aimed at, and the solder ball 30 can be protected reliably.
    Next, a fifth embodiment of the present invention will be described.
    FIG. 28 is a diagram for describing a semiconductor device according to a fifth embodiment of the present invention. FIG. In the semiconductor device 20E according to the present embodiment, the electrode film 25 formed on the substrate 22 by setting the linear expansion coefficient of the adhesive 60 for fixing the semiconductor chip 23 to the substrate 22 to an appropriate value. This is to prevent disconnection of wiring patterns.
    Here, the adhesive agent 60 for fixing the semiconductor chip 23 to the board | substrate 22 contains the additive material 62, and the linear expansion coefficient of the adhesive agent 60 is adjusted by the action | action of this additive material 62. FIG. .
    That is, the adhesive agent 60 is provided between the semiconductor chip 23 and the board | substrate 22, and is bonded to each of them. For this reason, if the linear expansion coefficient (alpha) d of the adhesive agent 60 is the same as the linear expansion coefficient (alpha) c of the semiconductor chip 23, the stress resulting from a thermal expansion difference will not generate | occur | produce. Similarly, if the linear expansion coefficient αd of the adhesive agent 60 is the same as the linear expansion coefficient α i of the substrate 22, no stress due to the thermal expansion difference does not occur.
    By the way, generally, the linear expansion rate of the semiconductor chip 23 and the linear expansion rate of the board | substrate 22 differ, and the linear expansion rate (alpha) of the board | substrate 22 is much larger than the linear expansion rate (alpha) of the semiconductor chip 23. It is a value. Therefore, it is preferable to set the coefficient of linear expansion αd of the adhesive 60 to a value between the coefficient of linear expansion αc of the semiconductor chip 23 and the coefficient of linear expansion αi of the substrate 22 (αc <αd < αi). In other words, it is preferable to select an adhesive having a linear expansion coefficient of a value between the linear expansion coefficient αc of the semiconductor chip 23 and the linear expansion coefficient αi of the substrate 22.
    In other words, the larger the difference in the linear expansion rate is, the larger the generated stress is. Therefore, the linear expansion rate of the adhesive 60 is set to a value between the linear expansion rate of the semiconductor chip 23 and the linear expansion rate of the substrate 22, thereby increasing the linear expansion rate of the adhesive 60. And the difference between the linear expansion rate of the semiconductor chip 23 and the difference between the linear expansion rate of the adhesive agent 60 and the linear expansion rate of the substrate 22 are linear expansion rates of the semiconductor chip 23 and linear expansion rate of the substrate 22. It is configured to be smaller than the difference of.
    In addition, since the adhesive agent 60 is also in close contact with the resin package 28, the coefficient of linear expansion αd of the adhesive 60 is equal to or close to the coefficient of linear expansion αm of the encapsulating resin forming the resin package 28. Preferred (αd ≒ αm).
    According to the semiconductor device 2E according to the present embodiment configured as described above, since the difference between the linear expansion rate of the adhesive 60 and the linear expansion rate of the component in close contact with the adhesive 60 is made extremely small, the adhesive 60 ) And stress caused by the difference in thermal expansion acting between each component can be suppressed. Therefore, according to the semiconductor device 2E according to the present embodiment, it is possible to suppress the disconnection of the wiring pattern and the breakage of the external connection terminal due to the thermal expansion difference of the component, so that a highly reliable semiconductor device can be realized.
    In this embodiment, the linear expansion coefficient of the adhesive 60 is adjusted to an appropriate value by adding the additive 62 to the adhesive 60. That is, by adding the additive material 62, the linear expansion rate of the adhesive is reduced to a value between the linear expansion rate of the semiconductor chip and the linear expansion rate of the substrate and approximated by the linear expansion rate of the sealing resin. The particles of silicon oxide (SiO 2) is suitable as the material of the additive (62), but not limited to this, so long as it is possible to reduce the coefficient of thermal expansion may be used other materials. Moreover, although the epoxy resin adhesive is suitable as a material of the adhesive agent 60, it is not limited to this, You may use other adhesive agents, such as a phenol resin adhesive.
    In addition, the elasticity modulus of the adhesive agent 60 increases by adding the additive 62. However, in order to absorb and alleviate the thermal expansion difference between the semiconductor chip 23 and the substrate 22, it is preferable to reduce the coefficient of linear expansion while keeping the elastic modulus of the adhesive 60 as low as possible. That is, it is preferable to reduce the coefficient of linear expansion while maintaining the flexibility of the adhesive.
    Next, the glass transition temperature of the sealing resin of the adhesive agent 60 and the resin package 28 is demonstrated.
    In general, above the glass transition temperature, the coefficient of linear expansion of the material increases by three times or more. Therefore, when an evaluation test such as applying a temperature higher than the glass transition temperature to a semiconductor device is performed, the thermal stress of the adhesive is remarkably increased, resulting in an extremely rapid timing of failure.
    As an evaluation test which adds the temperature more than glass transition temperature, there exists an environmental acceleration test, for example. In the environmental accelerated test, the semiconductor device is repeatedly subjected to a temperature cycle, for example, held at -65 ° C for 30 minutes, then at room temperature for 1 minute, and at 150 ° C for 30 minutes. Investigate.
    Therefore, it is preferable that the glass transition temperature of an adhesive agent and sealing resin is higher than 150 degreeC. Moreover, even when the glass transition temperature of an adhesive agent is lower than 150 degreeC, it is preferable to make glass transition temperature as close to 150 degreeC as possible. In the present embodiment, since the glass transition temperature of the adhesive 60 can be increased by adding the additive 62 to the adhesive 60, the occurrence of failure can be suppressed.
    Next, the experimental results of the semiconductor device 2E according to the present embodiment will be described.
    In the experiment, semiconductor devices A, B, and B-improved were produced. The semiconductor device A is an example in which the linear expansion coefficient between the adhesive and the sealing resin is suitable. The semiconductor device B is an example in which the linear expansion rate of the adhesive is too large relative to the linear expansion rate of the sealing resin. The semiconductor device (B-improvement) is an example in which the linear expansion rate is reduced by adding an additive to the adhesive of the semiconductor device (B).
    In each of the semiconductor devices A, B, and B-improved, the substrate 22 is formed of a polyimide tape having a linear expansion coefficient of 20 [pm / ° C], and the semiconductor chip 23 mounted on the substrate 20. ) Was formed of a silicon wafer having a linear expansion coefficient of 3.6 [pm / ° C.]. Therefore, it is preferable that the linear expansion rate of the adhesive agent 60 to be used is a value between 3.6 [pm / degreeC] and 20 [pm / degreeC]. The wiring pattern including the electrode film 25 is formed of a copper plate having a linear expansion coefficient of 17.7 [pm / ° C], and the solder ball 30 as an external connection terminal is formed of solder having a linear expansion coefficient of 25.4 [pm / ° C]. It was. 29 shows the coefficients of linear expansion and modulus of elasticity of these components. In addition, the "mounting substrate" in FIG. 29 represents the average linear expansion coefficient and elastic modulus of the substrate on which the semiconductor device is mounted.
    FIG. 30 is a diagram for explaining the coefficient of linear expansion and the glass transition temperature of the adhesive and the sealing resin used in each of the semiconductor devices A, B, and B-improved.
    Regarding the semiconductor device A, the linear expansion coefficient of the adhesive was 10 to 16 [pm / ° C], and was a value between the linear expansion coefficients of the substrate 22 and the semiconductor chip 23. Moreover, the linear expansion rate of sealing resin is 6-10 [pm / degreeC], and approximates the linear expansion rate of an adhesive agent. Moreover, the glass transition temperature of the adhesive agent of the semiconductor device A was 135-145 degreeC, and was nearly the same as the glass transition temperature of 130 degreeC of sealing resin. Thus, the combination of the adhesive agent and sealing resin of the semiconductor device A was suitable for the conditions of the semiconductor device 2E which concerns on the present Example mentioned above.
    Regarding the semiconductor device (B), the linear expansion coefficient of the adhesive was 40 to 50 [pm / ° C], which was considerably higher than 20 [pm / ° C], which is the linear expansion rate of the substrate 22. Moreover, the linear expansion rate of the sealing resin was 12-16 [pm / degreeC], and was considerably lower than the linear expansion rate of an adhesive agent. Moreover, the glass transition temperature of the adhesive agent of the semiconductor device (B) was 130-140 degreeC, and was considerably lower than the glass transition temperature of 210 degreeC of the sealing resin. Thus, the combination of the adhesive agent and sealing resin of the semiconductor device B was not suitable for the conditions of the semiconductor device 2E which concerns on the present Example mentioned above.
    The semiconductor device (B-improvement) was formed by adjusting the coefficient of linear expansion by adding an additive to the adhesive of the semiconductor device (B). That is, the linear expansion coefficient of the adhesive agent was reduced to 10-20 [pm / degreeC] by adding an additive. As a result, the coefficient of linear expansion of the adhesive became a value between the coefficient of linear expansion of the substrate and the semiconductor chip, and became a value approximating the coefficient of linear expansion of the sealing resin. Moreover, the glass transition temperature of the adhesive agent was 135-145 degreeC by the addition of an additive material, but it increased slightly, and was close to the glass transition temperature of 210 degreeC of the sealing resin.
    FIG. 31 is a diagram for explaining the relationship between the amount of the additive added to the adhesive of the semiconductor device B, the coefficient of linear expansion, and the modulus of elasticity, and FIG. 32 is a graph showing the relationship between the amount of the additive, the coefficient of linear expansion, and the modulus of elasticity. As the addition amount of the additive was increased, the linear expansion rate of the adhesive was reduced, and the addition amount was 10 to 20 [pm / ° C] at 80 wt%, resulting in a value between the linear expansion rate of the substrate and the semiconductor chip. At this time, the increase in elastic modulus was slow.
    Regarding each of the semiconductor devices A, B, and B-improved as described above, semiconductor devices having two types of package sizes of 10 mm and 14 mm angles were produced and subjected to an environmental acceleration test. In the environmental acceleration test, a temperature cycle held at −65 ° C. for 30 minutes, then at room temperature for 1 minute, and at 150 ° C. for 30 minutes was repeatedly applied to the semiconductor device, and the presence or absence of failure occurred every 100 cycles.
    33 is a diagram for explaining a result of the environmental acceleration test. In the package size of 10 mm square), the defect generation cycle of the semiconductor device A was 1200 times. That is, the defect, such as a wiring pattern disconnection, was detected when the temperature cycle was repeated 1200 times. The defect generation cycle of the semiconductor device B was 700 times, which was considerably lower than the number of defect occurrences of the semiconductor device A. FIG. That is, the semiconductor device B had about half the occurrence time of failure compared with the semiconductor device A. FIG. On the other hand, the defect generation cycle of the semiconductor device (B-improved) is 1000 times, and it is considerably improved compared with 700 defect generation cycles of the semiconductor device (B). This is considered to be an effect by the linear expansion coefficient of an adhesive agent being reduced by addition of the additive material to the adhesive agent, and becoming a value between the linear expansion coefficients of a board | substrate and a semiconductor chip.
    Although the same test was done also about the package size of a 14 mm square, the result was substantially the same as the case of the package size of a 10 mm square, and the effect of the reduction of the linear expansion rate by an additive was confirmed.
    As described above, in the semiconductor device 2E according to the present embodiment, by optimizing the linear expansion coefficient of the adhesive, the stress due to the thermal expansion difference acting on the wiring pattern located between the substrate and the semiconductor chip can be reduced. In addition, by increasing the glass transition temperature of the adhesive, even when the interface between the adhesive and the encapsulation resin is located directly above or near the wiring pattern, stress generated at the interface due to the thermal expansion difference can be reduced. Therefore, disconnection and breakage failure of the wiring pattern can be suppressed, and high mounting reliability can be achieved.
    It is a figure for demonstrating the method of forming an adhesive bond layer in predetermined uniform thickness. A part of the additive material 60 used in the present embodiment is made into the additive material 62A having the same particle diameter as the predetermined thickness between the semiconductor chip 23 and the substrate 22, so that the thickness of the adhesive layer can be easily determined. The thickness can be made. According to such a structure, since an adhesive bond layer is formed in uniform thickness, the deformation | transformation of a semiconductor device by thermal stress can be prevented, and failures, such as disconnection of a wiring pattern, can also be suppressed.
    It is a figure for demonstrating the structure which makes uniform the change of the thickness of an adhesive bond layer. In a semiconductor device having a structure in which external connection terminals (solder balls 30) are arranged around the semiconductor device, the electrode film 25 is formed on the substrate 22 corresponding to the peripheral portion of the semiconductor chip 23. In FIG. 35, the electrode films 25 on which the solder balls 30 are formed are arranged in two peripheral rows. Therefore, although the electrode film 25 does not need to be provided under the center part of the semiconductor chip 23, in the semiconductor device shown in FIG. 35, the dummy pattern 64 of the same shape as the electrode film 25 has an electrode film. It is formed over the whole surface of the board | substrate 22 except the area | region in which 25 is formed (refer FIG. 36).
    According to such a structure, the thick part and thin part of the thickness of an adhesive bond layer are formed regularly, and the bias of the thickness of an adhesive agent is suppressed substantially. Therefore, deformation of the semiconductor device due to uneven thickness of the adhesive can be prevented, and occurrence of failure such as disconnection of the wiring pattern can be suppressed.
    In addition, the dummy pattern 64 as a deformation | transformation prevention pattern is not limited to the shape and arrangement | sequence shown in FIG. 36, Any shape and arrangement may be sufficient as long as the deflection of the thickness of an adhesive bond layer can be substantially reduced. The dummy pattern 64 may be formed of the same material as the electrode film 25 at the same time, or may be formed in another process.
    According to the present invention described above, various effects described later can be realized.
    According to the invention of claim 1,
    By forming the external connection electrode on the electrode film by plating, the installation process of the solder paste, the transfer of the solder ball, the positioning process, etc. are unnecessary as compared with the configuration using the solder ball. Can be facilitated and the cost can be reduced.
    Further, by configuring the diameter dimension S1 of the portion protruding from the tape-shaped substrate of the external connection electrode to be smaller than the diameter dimension S2 of the opening (S1 S2), the pitch between adjacent external connection electrodes can be reduced. have. Therefore, even if the semiconductor chip is densified and the number of external connection electrodes increases, this can be coped with. In addition, as described above, S1 S2 can be realized by appropriately controlling the plating speed, the plating time, and the like of the external connection electrode.
    In addition, as described in claim 2, at least one of nickel, copper, and gold can be used as a material of the external connection electrode.
    Moreover, according to invention of Claim 3,
    A first electrode portion formed directly on the electrode film and having a height smaller than the depth of the opening portion and larger than a central position of the opening portion, and one end portion joined to the first electrode portion and the other end portion projecting outward from the opening portion; By forming the external connection electrode by the two-electrode portion, when the second electrode portion is formed, it is in a state formed in the first electrode portion in the opening portion. Therefore, the second electrode portion and the electrode film can be electrically connected by bonding the second electrode to the first electrode portion.
    As described above, since the first electrode portion has a height that does not protrude from the opening portion, the distance between the first electrode portion and the second electrode portion is shortened when the second electrode portion is formed. Therefore, a 2nd electrode part can be reliably connected to a 1st electrode part, and a clearance gap is not formed between a 1st electrode part and a 2nd electrode part. Therefore, since the second electrode portion can be reliably connected to the first electrode portion (that is, the electrode film), the reliability of the semiconductor device can be improved.
    As described in claim 4, at least one of nickel, copper, and gold can be used as the material of the first electrode portion, and solder can be used as the material of the second electrode portion.
    Moreover, according to invention of Claim 5,
    By forming a thin film made of a material having good bonding property with the external connection electrode on the inner wall of the opening formed in the tape type substrate, a constriction portion (caused by a gap between the opening inner wall and the external connection terminal) is formed in the external connection terminal in the opening. It can be prevented from occurring. Therefore, due to this, damage such as cracks can be prevented from occurring in the external connection terminal, and the reliability of the semiconductor device can be improved.
    That is, when the external connection electrode is formed in the opening in which a thin film made of a material having good adhesion to the external connection electrode is formed on the inner wall, the external connection terminal is bonded to the thin film (ie, the inner wall) in the opening. Therefore, no gap is generated between the external connection terminal and the opening, and the external connection terminal is firmly bonded to the inner wall of the opening, thereby preventing damage to the external connection terminal from occurring in the opening. Can be.
    As described in claim 6, the thin film can be formed by plating, and at least one of nickel, copper, and gold can be used as the material.
    Moreover, according to invention of Claim 7,
    When the diameter dimension of the opening formed in the tape-shaped substrate is A and the thickness dimension of the tape-shaped substrate is B, the ratio (B / A) of the diameter dimension (A) of the opening and the thickness dimension (B) of the tape-shaped substrate Is (B / A) ≤ 0.3 to prevent the occurrence of an open defect (a state in which a gap is formed between the external connection terminal and the electrode film and not electrically connected) between the external connection terminal and the electrode film. In response to the increase in density of the semiconductor chip, the strength of the tape-type substrate itself can be maintained, and the strength of the external connection terminal can be improved.
    That is, as the diameter dimension A of the opening is increased, the strength of the external connection electrode in the opening is improved, and as the thickness dimension B of the tape substrate is smaller, the strength of the external connection electrode in the opening is Is improved. By the way, when the diameter dimension A and the thickness dimension B are independent, the diameter dimension A of the opening is made larger, and the thickness dimension B of the tape-shaped substrate is made smaller. It becomes impossible to cope with this (this is related to the diameter dimension A), and at the same time, the strength of the tape-shaped substrate itself decreases (this is due to the thickness dimension B).
    By the way, the diameter dimension (A) of the opening and the thickness dimension (B) of the tape-shaped substrate are correlated, and the diameter dimension (A) of the opening and the tape-type substrate are adjusted so that (B / A) ≤ 0.3 as described above. By setting the thickness dimension B, it is possible to suppress the occurrence of open defects due to breakage of the external connection terminal, to cope with high density of the semiconductor chip, to maintain the strength of the tape-type substrate itself, and to The strength can be improved.
    Moreover, according to invention of Claim 8,
    In the solder paste printing step of printing and filling the solder paste into the openings formed in the tape type substrate, the printing process is performed such that the solder paste is inserted deeply to the position where the solder paste is in contact with the electrode film. When joining the solder and the solder ball in the gap, no gap is formed between them, so that the occurrence of an open defect can be suppressed. Thereby, the reliability of a semiconductor device can be improved.
    Moreover, according to invention of Claim 9,
    By setting the thickness of the adhesive used for mounting the semiconductor chip on the tape substrate to a thickness dimension of 100 to 150 µm, the external connection is caused by the difference in thermal expansion between the semiconductor chip and the mounting substrate after the semiconductor device is mounted on the mounting substrate. The terminal can be prevented from being damaged.
    In other words, when the thermal expansion coefficients of the semiconductor chip and the mounting substrate are different, a large stress is concentrated on the external connection terminals due to the difference in thermal expansion during heating, and in the worst case, the external connection terminals may be broken.
    By the way, by setting the thickness of the adhesive interposed between the semiconductor chip and the tape substrate to a thickness dimension of 100 µm to 150 µm, the adhesive functions as a cushioning material, and thus stress that concentrates on the external connection terminal can be alleviated. As a result, damage to the external connection terminal due to the thermal expansion difference between the semiconductor chip and the mounting substrate can be prevented.
    Moreover, according to invention of Claim 10,
    When heat treatment is performed on the adhesive in the chip mounting step, the semiconductor chip is subjected to heat treatment in a direction in which the semiconductor chip is located below, so that the self-weight of the semiconductor chip is tape-shaped during the heat treatment. Act to separate from the substrate. Thereby, an adhesive with a large thickness can be formed easily and reliably.
    Moreover, according to invention of Claim 11, the stress by the thermal expansion difference which acts on the wiring pattern located between a board | substrate and a semiconductor chip can be reduced by optimizing the linear expansion coefficient of an adhesive agent. Therefore, disconnection and breakage failure of the wiring pattern can be suppressed, and high mounting reliability can be achieved.
    Further, according to the invention of claim 12, by forming a strain preventing pattern for preventing unnecessary deformation of the wiring board at positions other than the position where the electrode film is formed, it is possible to prevent an unbalance from occurring in the thickness of the adhesive. Therefore, it is possible to reliably suppress the disconnection failure of the wiring pattern.
    According to the invention described in claim 13, the thickness of the adhesive layer can be made a predetermined uniform thickness by adding particles having a particle size equal to the distance between the wiring board and the semiconductor element to the adhesive. Therefore, unnecessary deformation of the wiring board can be prevented, and it is possible to reliably suppress the breakage of the wiring pattern.
    The applicant discloses the following matters in addition to the above disclosure.
    (1) tape type substrate,
    A semiconductor chip mounted on a surface of the tape type substrate,
    An adhesive for fixing the semiconductor chip to the tape type substrate,
    An electrode film formed on the tape substrate and electrically connected to the semiconductor chip;
    A semiconductor device comprising an external connection electrode connected to the electrode film through an opening formed in the tape type substrate.
    The thickness of the said adhesive agent from the said tape-shaped board | substrate was 100 micrometers-150 micrometers, The semiconductor device characterized by the above-mentioned.
    (2) The semiconductor device according to (l), wherein the height of the side surface of the semiconductor chip is T;
    In addition, when the height in the lower end of the side surface of the said semiconductor chip of the fillet formed in the said semiconductor chip outer peripheral position of the said adhesive agent is t,
    And a height t of the fillet is set to (0.2 x T) &lt; t &lt; (0.6 x T).
    (3) The semiconductor device according to (1) or (2), wherein
    A semiconductor device having a viscosity of 30000 cps to 70000 cps and a thixotropy of 1.0 to 4.0 as the adhesive.
    (4) The semiconductor device according to any one of (1) to (3), wherein
    A semiconductor device, characterized in that as the adhesive used to the elastic modulus of 200kgf / mm 2 ~ 800kgf / mm 2.
    (5) The semiconductor device according to any one of (1) to (4), wherein
    A semiconductor device having a linear expansion coefficient of 6 × 10 −6 / ° C. to 15 × 10 −6 / ° C. as the adhesive.
    (6) The semiconductor device according to any one of (1) to (5), wherein
    And a strain preventing pattern for preventing unnecessary deformation of the tape-shaped substrate at positions other than the position where the electrode film is formed.
    (7) wiring board,
    A semiconductor device mounted on a surface of the wiring board,
    An adhesive for fixing the semiconductor element to the wiring board,
    An electrode film formed on the wiring board and electrically connected to the semiconductor element;
    A semiconductor device comprising a sealing resin for sealing the semiconductor element and the electrode film,
    And the linear expansion rate of the adhesive is larger than the linear expansion rate of the semiconductor element and smaller than the linear expansion rate of the wiring board, and the linear expansion rate of the adhesive is approximated to the linear expansion rate of the encapsulating resin.
    (8) The semiconductor device according to (7), wherein
    The adhesive includes an additive, and the linear expansion coefficient and the glass transition temperature of the adhesive are adjusted by changing the content of the additive.
    (9) The semiconductor device according to (8), wherein
    The amount of the additive added is an amount in the range of increasing the linear expansion coefficient of the adhesive but keeping the elastic modulus substantially constant.
    According to the invention described in the above (1),
    By setting the thickness of the adhesive used for mounting the semiconductor chip on the tape substrate to a thickness dimension of 100 to 150 µm, the external connection is caused by the difference in thermal expansion between the semiconductor chip and the mounting substrate after the semiconductor device is mounted on the mounting substrate. The terminal can be prevented from being damaged.
    That is, when the thermal expansion coefficients of the semiconductor chip and the mounting substrate are different, a large stress is concentrated on the external connection terminals due to the difference in thermal expansion during heating, and in the worst case, the external connection terminals may be broken.
    However, by setting the thickness of the adhesive interposed between the semiconductor chip and the tape substrate to a thickness dimension of 100 µm to 150 µm, the adhesive functions as a cushioning material, and thus stress that concentrates on the external connection terminal can be alleviated. As a result, damage to the external connection terminal due to the thermal expansion difference between the semiconductor chip and the mounting substrate can be prevented.
    According to the invention described in the above (2),
    The height T of the side surface of the semiconductor chip and the height t from the lower side of the side surface of the semiconductor chip of the fillet formed at the peripheral position of the semiconductor chip of the adhesive are such that (0.2 x T) T (0.6 x T) By configuring, the semiconductor device can be miniaturized.
    In other words, the height t of the fillet of the adhesive has a relationship with the installation area of the adhesive on the tape-shaped substrate. Specifically, since the fillet is formed in a curved shape toward the semiconductor chip outer peripheral position on the tape-shaped substrate, the larger the height t at the lower side of the side face of the semiconductor chip of the fillet, the longer the curved shape is, so the tape The area in contact with the type substrate is also widened. Moreover, other components (for example, an electrode film, a wire, etc.) cannot be provided in the site | part in which the adhesive agent was installed on the tape-shaped board | substrate, Therefore, when the height t of the fillet of an adhesive agent becomes high, a semiconductor device will be enlarged. .
    However, by setting the height t at the lower side of the side face of the fillet semiconductor chip to be smaller than (0.2 × T) ≦ t <(0.6 × T) as described above, the area of the adhesive contacting the tape-shaped substrate is reduced. Therefore, the semiconductor device can be miniaturized. The height t at the lower end side face of the semiconductor chip of the fillet can be controlled by appropriately selecting the viscosity, thixotropy, elastic modulus, and the like of the adhesive.
    In addition, as in the invention according to item (3),
    By using an adhesive having a viscosity of 30000 cps to 70000 cps and a thixotropy of 1.0 to 4.0, it is possible to effectively prevent damage to external connection terminals and to miniaturize a semiconductor device.
    In addition, like the invention according to item (4),
    By using that the elastic modulus of 200kgf / mm 2 ~ 800kgf / mm 2 as the adhesive, it is possible effectively to reduce the size of the damage prevention and the semiconductor device of the external connection terminal.
    Moreover, according to invention of Claim (5),
    By using an adhesive having a linear expansion coefficient of 6 × 10 −6 / ° C. to 15 × 10 −6 / ° C. as an adhesive, it is possible to effectively prevent damage to external connection terminals and to downsize a semiconductor device.
    Moreover, according to invention of Claim (6),
    By forming a deformation preventing pattern that prevents unnecessary deformation of the tape-shaped substrate at positions other than the position where the electrode film is formed, it is possible to prevent an unbalance from occurring in the thickness of the adhesive, thus preventing the peeling of the adhesive and the external connection terminal. Protection can be reliably performed.
    Moreover, according to invention of Claim (7),
    By optimizing the linear expansion coefficient of the adhesive, the stress due to the thermal expansion difference acting on the wiring pattern located between the substrate and the semiconductor chip can be reduced. Therefore, disconnection and breakage failure of the wiring pattern can be suppressed, and high mounting reliability can be achieved.
    Moreover, according to invention of Claim (8),
    By adding the additive to the adhesive, it is possible to easily adjust the linear expansion coefficient and the glass transition temperature of the adhesive to a suitable value or a value close thereto. In this way, by optimizing the linear expansion coefficient of the adhesive, the stress due to the thermal expansion difference acting on the wiring pattern located between the substrate and the semiconductor chip can be reduced. In addition, by increasing the glass transition temperature of the adhesive, even when the interface between the adhesive and the encapsulation resin is located directly above or near the wiring pattern, the stress generated at the interface due to the thermal expansion difference can be reduced. Therefore, disconnection and breakage failure of the wiring pattern can be suppressed, and high mounting reliability can be achieved.
    Moreover, according to invention of Claim (9),
    Since the linear expansion rate of the adhesive increases but the elastic modulus remains substantially constant, the linear expansion rate is reduced while maintaining the flexibility of the adhesive. Therefore, the suppression of the stress due to thermal expansion can be achieved while maintaining the effect of stress relaxation due to the flexibility of the adhesive.
    权利要求:
    Claims (13)
    [1" claim-type="Currently amended] Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    The external connection electrode is formed on the electrode film by plating;
    The semiconductor device is characterized in that S1 S2 when the diameter dimension of the portion protruding from the tape-shaped substrate of the external connection electrode is S1 and the diameter dimension of the opening is S2.
    [2" claim-type="Currently amended] The method of claim 1,
    The material of the external connection electrode is a semiconductor device, characterized in that at least one of nickel, copper, and gold.
    [3" claim-type="Currently amended] Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    The external connection electrode,
    A first electrode portion formed directly on the electrode film and having a height smaller than a depth of the opening and larger than a central position of the opening; And
    And a second electrode portion formed so that one end thereof is joined to the first electrode portion and the other end portion protrudes outwardly from the opening portion.
    [4" claim-type="Currently amended] The method of claim 3, wherein
    At least one of nickel, copper, and gold is used as a material of the first electrode portion,
    Moreover, solder is used as a material of a said 2nd electrode part, The semiconductor device characterized by the above-mentioned.
    [5" claim-type="Currently amended] Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    And a thin film made of a material having good adhesion to the external connection electrode on the inner wall of the opening.
    [6" claim-type="Currently amended] The method of claim 5,
    The thin film is formed by plating,
    Moreover, at least any one of nickel, copper, and gold was used as the material.
    [7" claim-type="Currently amended] Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An electrode film formed on the surface of the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device provided on the back surface of the tape substrate and provided with an external connection electrode connected to the electrode film through an opening formed in the tape substrate.
    And (B / A) ≤ 0.3 when the diameter dimension of the opening portion is A and the thickness dimension of the tape substrate is B.
    [8" claim-type="Currently amended] A solder paste printing step of printing a solder paste on a resin substrate having an opening formed in a tape-shaped substrate on which a semiconductor chip is mounted, and having an opening formed by covering a conductive film at one edge of the opening, and loading the solder paste into the opening; And
    In the manufacturing method of the semiconductor device which has a ball mounting process which joins the said solder ball to the said electrode film by providing and heating the solder ball which becomes an external connection terminal after completion | finish of the said solder paste printing process,
    In the solder paste printing step, a printing process is performed such that the solder paste is inserted deeply to a position where the solder paste is in contact with the electrode film.
    [9" claim-type="Currently amended] Tape-type substrates;
    A semiconductor chip mounted on a surface of the tape type substrate;
    An adhesive for fixing the semiconductor chip to the tape type substrate;
    An electrode film formed on the tape substrate and electrically connected to the semiconductor chip; And
    A semiconductor device comprising an external connection electrode connected to the electrode film through an opening formed in the tape type substrate.
    The thickness of the said adhesive agent from the said tape-shaped board | substrate was 100 micrometers-150 micrometers, The semiconductor device characterized by the above-mentioned.
    [10" claim-type="Currently amended] In the manufacturing method of the semiconductor device which manufactures the semiconductor device of any one of Claims 1-9,
    A chip mounting step of mounting the semiconductor chip on the tape-shaped substrate is performed by attaching an adhesive to the tape-type substrate, then mounting the semiconductor chip on the adhesive, and then performing heat treatment to cure the adhesive. Equipped,
    Further, when the heat treatment is performed on the adhesive in the chip mounting step, the heat treatment is performed in a direction in which the semiconductor chip is located below the tape-shaped substrate.
    [11" claim-type="Currently amended] Wiring board;
    A semiconductor device mounted on a surface of the wiring board;
    An adhesive fixing the semiconductor device to the wiring board;
    An electrode film formed on the wiring board and electrically connected to the semiconductor element; And
    A semiconductor device comprising a sealing resin encapsulating the semiconductor element and the electrode film,
    And the linear expansion rate of the adhesive is larger than the linear expansion rate of the semiconductor element and smaller than the linear expansion rate of the wiring board, and the linear expansion rate of the adhesive is approximated to the linear expansion rate of the encapsulating resin.
    [12" claim-type="Currently amended] The method of claim 11,
    And a strain preventing pattern for preventing unnecessary deformation of the wiring board at positions other than the position where the electrode film is formed.
    [13" claim-type="Currently amended] The method according to claim 11 or 12,
    The additive material includes particles having a particle size equal to the distance between the wiring board and the semiconductor element.
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    同族专利:
    公开号 | 公开日
    US6281571B1|2001-08-28|
    JP3844936B2|2006-11-15|
    TW457528B|2001-10-01|
    KR100533203B1|2005-12-05|
    JP2000349199A|2000-12-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-03-26|Priority to JP99-084591
    1999-03-26|Priority to JP8459199
    2000-03-09|Priority to JP2000065536A
    2000-03-09|Priority to JP2000-65536
    2000-03-24|Application filed by 아끼구사 나오유끼, 후지쯔 가부시끼가이샤
    2000-12-26|Publication of KR20000076950A
    2005-12-05|Application granted
    2005-12-05|Publication of KR100533203B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP99-084591|1999-03-26|
    JP8459199|1999-03-26|
    JP2000065536A|JP3844936B2|1999-03-26|2000-03-09|Semiconductor device|
    JP2000-65536|2000-03-09|
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