Method for manufacturing dynamic random access memory cell

专利摘要:
PURPOSE: A method for manufacturing a DRAM cell to use a self align contact in which a capacitor plate electrode is utilized as an etching stopping layer in forming a bit line contact, the bit line contact and the plate electrode being electrically insulated. CONSTITUTION: A method for manufacturing a DRAM cell comprises the steps of: forming an isolation layer(2) in a field region of a silicon substrate(1); forming a gate electrode having a stacked structure of a gate oxidation layer, a gate conductive layer(4) and an insulation layer in an active region of the silicon substrate; forming a junction between a source and a drain, and a spacer layer(7) on the side wall the gate electrode; forming a store electrode(9) in contact with the source/drain regions(6); forming an insulation layer for blocking etching in a bit line(15) contact region; forming a thick interlayer dielectric and planarizing the interlayer dielectric to be even on the uppermost surface of the store electrode; etching the interlayer dielectric in the region other than the bit line contact region and a plate electrode, performing an etching process by using a mask for patterning a bit line contact hole and a plate electrode; forming an oxidation layer by oxidizing a predetermined portion of a conductive layer for a plate electrode of which the side wall is exposed in the bit line(15) contact hole; and forming a bit line in the bit line contact hole.
公开号:KR20000027653A
申请号:KR1019980045610
申请日:1998-10-28
公开日:2000-05-15
发明作者:박재범
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

DRAM cell manufacturing method
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM cell manufacturing method of a semiconductor memory device. In particular, in a cell structure in which a capacitor is formed under a bit line, a capacitor plate electrode and a bit line contact hole are formed using one mask, and a plate electrode is formed. The present invention relates to a method for fabricating a DRAM cell using a self alignment contact method using an insulating layer and a spacer formed on an upper surface of a gate electrode and a gate electrode, and a spacer, respectively.
In the prior art, after forming a plate electrode in a structure in which a capacitor is formed below the bit line, a portion of the plate electrode is formed to be spaced apart from the contact hole to isolate the bit line contact region from the plate electrode and the bit line. An insulating film is deposited on the entire structure. In addition, an etching process must be performed to form a bit line contact hole.
This process, however, must be spaced apart for plate electrode and bit line contact and isolation. This has the disadvantage of increasing the cell area. In addition, the plate electrode and bitline contact mask must be aligned exactly in the desired area. However, when the contact mask is not aligned correctly, an unwanted area, for example, a gate electrode or the like is etched, or an insulating film on the sidewall of the gate is etched, resulting in a problem of low insulation.
In order to solve the above problems, a method of manufacturing a DRAM cell by using a capacitor plate electrode as an etch stop layer when forming a bit line contact, and applying a self-aligned contact method to electrically insulate the bit line and the plate electrode The purpose is to provide.
1 to 6 are cross-sectional views illustrating a process of manufacturing a DRAM cell according to an embodiment of the present invention.
※ Explanation of Codes on Major Parts of Drawings
1: silicon substrate 2: device isolation film
3: gate insulating film 4: gate conductive layer
5 insulating film 6 source / drain region
7: spacer film 8: antioxidant film
9 storage electrode 10 capacitor dielectric film
11 conductive layer for plate electrode 12 insulating film for preventing oxidation and etching
13 interlayer insulation film 14 oxide film
15: bitline
The present invention for achieving the above object in the DRAM cell manufacturing method,
Forming an isolation layer in the field region of the silicon substrate;
Forming a gate electrode having a stacked structure of a gate oxide film, a gate conductive layer, and an insulating film in an active region of the silicon substrate,
Forming a source and drain junction and forming a spacer film on sidewalls of the gate electrode;
Forming a storage electrode in contact with the source / drain region;
Forming an etching prevention insulating film in the bit line contact region;
Stacking a capacitor dielectric film, a conductive layer for plate electrodes, an insulating film for preventing oxidation and etching on the entire structure;
Forming a thick interlayer insulating film, and then performing a planarization process so as to be flat on an uppermost surface of the storage electrode;
Etching the interlayer insulating layer in a portion other than the bit line contact region and the plate electrode by performing an etching process using a mask patterning the bit line contact hole and the plate electrode;
Subsequently, the exposed oxidizing and etching prevention insulating film, the plate electrode conductive layer, the capacitor dielectric film, and the oxidation preventing insulating film are sequentially removed, and the bit line contacts self-aligned by the insulating films and spacers on the upper and side surfaces of the gate electrode. Forming a plate electrode at the same time as forming a hole,
Forming an oxide film by oxidizing a portion of the conductive layer for a plate electrode having sidewalls exposed from the bit line contact hole;
Forming a bit line in the bit line contact hole.
The etching and anti-oxidation insulating film is a nitride film, the capacitor dielectric film is Ta2O5, SrTO3 or BST, the conductive layer for plate positive electrode is one of Ti, TiN, W, WN, Pt, Ru, RuO2 or a stacked structure thereof, The bit line may be one of Ti, TiN, W, and WN or a stacked structure thereof.
In order to solve two problems of the prior art, the present invention forms a plate electrode at the same time as forming a bit line contact and insulates the plate electrode exposed to sidewalls of the bit line contact hole before the bit line is formed. Let's do it.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 to 6 are cross-sectional views showing a process for manufacturing a DRAM cell according to an embodiment of the present invention.
1 shows the device isolation film 2 in the field region on the silicon substrate 1, and then the gate insulating film 3, the gate conductive layer 4, and the insulating film 5 in the active region of the silicon substrate 1. It is a cross-sectional view which forms the gate electrode and the source / drain area | region 6 which consist of a laminated structure, and the spacer film 7 for insulation is formed in the gate electrode side wall.
Fig. 2 forms an antioxidant film 8 over the entire structure, removes the antioxidant film 8 in an area excluding the bit line contact area, opens the area where the storage electrode is to be contacted, and then conducts the conductive layer for the storage electrode. And a storage electrode 9 formed by an etching process using a mask. Here, the storage electrode 9 can be manufactured in a cylindrical shape as shown in order to increase the surface area.
FIG. 3 shows a capacitor dielectric film 10, a plate electrode conductive layer 11, and an oxidation and etching prevention insulating film 12 sequentially formed on the entire structure surface including the storage electrode 9, and then the interlayer insulating film 13 Is formed in a thick layer, and the top surface of the interlayer insulating film 13 is planarized by a planarization process. The planarization process is performed using chemical-mechanical polishing or an etch back process.
4, the interlayer insulating film 13 in the bit line contact region is etched using the bit line contact and the plate electrode mask, and then the conductive layer 11 for the plate electrode, the capacitor dielectric film 10 and the insulating film for preventing oxidation and etching (12) is sequentially etched, but the bit line contact hole 20 and the plate electrode (not shown) which are self-aligned by the insulating film 5 and the spacer 7 on the top and side of the gate electrode are shown.
Here, the interlayer insulating layer 13 is formed of an oxide film, and the etching ratio is different from that of the nitride film formed of the insulating film 12 for preventing oxidation and etching. For reference, the bit line contact and plate electrode mask may be exposed to a photoresist film using a bit line contact hole and a plate electrode designed on a reticle, or may be exposed to the photoresist film using respective reticles. There is a way to proceed.
5 oxidizes a portion of the plate electrode conductive layer 11 exposed on the wall of the bit line contact hole 20 to form an oxide film 14 to electrically insulate the bit line to be formed in a subsequent process. . Subsequently, the anti-oxidation insulating film 8 is etched to form a contact hole 20 in which the source / drain regions are exposed.
FIG. 6 is a cross-sectional view of the bit line 15 formed by depositing a conductive layer for bit lines and then patterning using a bit line mask.
As described above, the present invention can reduce the number of processes and minimize the cell area by using a process of sequentially exposing one mask or each mask in forming a bit line contact hole and a mask process for forming a plate electrode. .
The present invention reduces the cell size by self-aligned contact and forms a plate electrode when forming a bit line contact hole in an effective manner in a device having a capacitor at a lower portion of a bit line suitable for a metal-based bit line structure to be used in a DRAM device. In the process of forming the bit line contact hole, the patterning process may be simultaneously performed in the process of forming the bit line contact hole, thereby reducing the number of processes, thereby improving productivity.

权利要求:
Claims (6)
[1" claim-type="Currently amended] In the DRAM cell manufacturing method,
Forming an isolation layer in the field region of the silicon substrate;
Forming a gate electrode having a stacked structure of a gate oxide film, a gate conductive layer, and an insulating film in an active region of the silicon substrate,
Forming a source and drain junction and forming a spacer film on sidewalls of the gate electrode;
Forming a storage electrode in contact with the source / drain region;
Forming an etching prevention insulating film in the bit line contact region;
Stacking a capacitor dielectric film, a conductive layer for plate electrodes, an insulating film for preventing oxidation and etching on the entire structure;
Forming a thick interlayer insulating film, and then performing a planarization process so as to be flat on an uppermost surface of the storage electrode;
Etching the interlayer insulating layer in a portion other than the bit line contact region and the plate electrode by performing an etching process using a mask patterning the bit line contact hole and the plate electrode;
Subsequently, the exposed oxidizing and etching prevention insulating film, the plate electrode conductive layer, the capacitor dielectric film, and the oxidation preventing insulating film are sequentially removed, and the bit line contacts self-aligned by the insulating films and spacers on the upper and side surfaces of the gate electrode. Forming a plate electrode at the same time as forming a hole,
Forming an oxide film by oxidizing a portion of the conductive layer for a plate electrode having sidewalls exposed from the bit line contact hole;
And forming a bit line in the bit line contact hole.
[2" claim-type="Currently amended] The method of claim 1,
The etching and oxidation prevention insulating film is a DRAM cell manufacturing method characterized in that the nitride film.
[3" claim-type="Currently amended] The method of claim 1,
And the capacitor dielectric film is Ta2O5, SrTO3 or BST.
[4" claim-type="Currently amended] The method of claim 1,
The conductive layer for positive electrode plate is one of Ti, TiN, W, WN, Pt, Ru, RuO 2 or a DRAM cell manufacturing method characterized in that the laminated structure thereof.
[5" claim-type="Currently amended] The method of claim 1,
And the bit line is one of Ti, TiN, W, and WN or a stacked structure thereof.
[6" claim-type="Currently amended] The method of claim 1,
The planarization process is a method of manufacturing a DRAM cell, characterized in that using a chemical-mechanical polishing method or an etch back process.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1998-10-28|Application filed by 김영환, 현대전자산업 주식회사

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1998-10-28|Priority to KR1019980045610A

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2000-05-15|Publication of KR20000027653A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019980045610A|KR20000027653A|1998-10-28|1998-10-28|Method for manufacturing dynamic random access memory cell|