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    • 专利摘要:
    Since the interface device according to the present invention guarantees a data rate of about 1 to 2 Mbps, it is suitable for use for interfacing between low-speed function devices and a serial bus. The interface device also ensures stable operation against load changes. Furthermore, the bus interface device of the present invention has a simple structure and a small chip size, which makes it suitable for forming into a single chip.
    公开号:KR19990074302A
    申请号:KR1019980007784
    申请日:1998-03-09
    公开日:1999-10-05
    发明作者:한상현；이재점
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    BIDIRECTIONAL TRANSCEIVER AND BUS INTERFACE WITH THE SAME
    FIELD OF THE INVENTION The present invention relates to bidirectional transceiver circuits used in data transmission systems, and more particularly to circuits for transmitting or receiving data in series with or from transmission lines. It is about.
    The invention also relates to a circuit for providing an interface between a bus and a device connected to the bus in digital data processing systems, more specifically. General-purpose serial buses, such as wire cables and the like, which facilitate the connection of computers and their peripherals, and circuitry for performing the interface between the devices connected to these buses. will be.
    In spite of the quantum leap in computers (especially personal computers) from the mid '90s, there have been few major changes to their peripherals.
    But now, peripherals of personal computers or workstations are changing significantly. This change is due to the emergence of new general-purpose buses such as USB, Fire Wire (also called 'IEEE1394'), Fiber Channel (FC), and Serial Storage Architecture (SSA). It is becoming possible. Among them, USB is promising as a next-generation computer peripheral interface with FW (i.e., IEEE1394) which is very suitable for a multimedia environment. In particular, unlike conventional parallel buses, the USB has various characteristics as follows. That is, no setting by terminator or jumper is necessary in Plug and Play (PnP) environment, and automatic assignment of IDs and hot plugs can be done by removing the device when the computer is in a power-on state. Is possible. Moreover, the USB cable has only four lines, two signal lines D + and D−, a power line and a ground line. Thus, it is possible to make fine cables and small connectors, thereby reducing the production cost and further developing low cost peripherals. According to the "USB specification Revision 1.0" (Jan. 15, 1996), a USB cable connects USB devices to a USB host. There is only one host in any USB system. USB systems have a multi-tiered star topology. USB devices include Hubs, which provide additional points of addition to the USB system, and Functions, which provide capabilites, to the system (e.g., display, keyboard, digital joystick, Speaker, etc.). The host must have a root hub. A plurality of nodes, that is, other hubs or function devices, are connected to one hub. Data transfer between functions that do not pass through the host is not possible. All USB devices are controlled by the host controller.
    It is a primary object of the present invention to provide a data transmitter for transmitting a data signal via a serial bus in a digital data processing system.
    Another object of the present invention is to provide a data receiver for receiving a data signal through a serial bus in a digital data processing system.
    It is still another object of the present invention to provide a serial bus connecting a host of a digital data processing system and its peripheral devices and a serial bus interface device providing an interface between the peripheral devices.
    It is still another object of the present invention to provide a low speed bus interface device for a universal serial bus (USB).
    1 is a block diagram of a bus interface according to the present invention;
    2 is a detailed circuit diagram of the voltage regulator of FIG.
    3 is a circuit diagram of the transceiver of FIG.
    4 is a circuit diagram showing a preferred embodiment of the receiver of FIG.
    5A and 5B are detailed circuit diagrams of the receiver of FIG. 4;
    6 is a detailed circuit diagram of each active filter of FIGS. 5A and 5B;
    7 is a circuit diagram showing a preferred embodiment of the transmitter of FIG.
    8A-8D are detailed circuit diagrams of the transmitter of FIG. And
    9A-9H are waveform diagrams of signals on the major components of the transmitter of FIG.
    * Description of the symbols for the main parts of the drawings *
    100: bus interface 100: voltage regulator
    120: data transceiver 310: data transmitter
    330: data receiver 710: state controller
    720: tilt controller 730, 740: output driver
    According to one aspect of the present invention for achieving the above objects, a bus interface device for providing communication between a serial bus and a functional device has a circuit configuration suitable for integration into a single chip. The interface device includes a voltage regulator for supplying a second power supply voltage within a second voltage range using a first power supply voltage within a first voltage range, and a bus using the first and second power supply voltages. And a transceiver for converting the plurality of first signals in the directional format into the plurality of second signals in the interface oriented format and vice versa. In addition, the interface apparatus includes an interface engine for executing an interface between the second signals of the interface oriented format and a plurality of third signals of the device oriented format, and the third signal of the device oriented format. And a device controller for controlling the functional device in response to these.
    According to another feature of the invention, a data transmission circuit for transmitting first and second electrical data signals onto a pair of first and second data lines comprises: a plurality of input signals applied from outside; In response to the state controller generating a plurality of state control signals that determine when the first and second data signals will be driven to their predetermined data states, and in response to the state control signals. A tilt controller for generating a plurality of tilt control signals for controlling an edge rate of the data signals; and a first data signal to be transmitted on the first data line in response to the state control signals and the tilt control signals. A first output driver for generating and the first in response to the state control signals and the tilt control signals A second output driver for generating said second data signal to be transmitted on a second data line. Each of the first output drivers has only one operational amplifier.
    According to another feature of the invention, the first and second electrical input data signals from a pair of first and second data lines in response to an enable signal, wherein the input data signals are two predetermined values. Swinging within a range of voltage levels, the data receiving circuitry comprising: amplifying the difference between the first input data signal and the second input data signal to swing within the same range as the input data signals; A differential amplifier for generating a differential signal, a first level shifter for shifting the swing voltage levels of the differential signal to generate a differential signal level-shifted equal to the first output data signal, and the first input A first Schmitt trigger for generating an output signal having hysteresis characteristics in response to the swing of the data signal; A second level shifter for shifting the swing voltage levels of the output signal of the Schmitt trigger to generate a first level-shifted output data signal, and having a hysteresis characteristic in response to the swing of the second input data signal. A second Schmitt trigger for generating an output signal, a third level shifter for shifting swing voltage levels of the output signal of the second Schmitt trigger to generate a second level-shifted output data signal, and Output drive logic for generating second and third output data signals in response to an enable signal and the first and second level shifted output data signals.
    According to another feature of the invention, a data transmission / reception circuit for transmitting or receiving electrical data signals to or from a pair of first and second data lines comprises: a first swing range each; A first coded input data signal within, a data end signal indicating the end of the first coded input data signal, and a selection signal, each of the first and second being within a second swing range; A transmitter for generating coded output data signals to provide to the data line pair, an inverter for logically inverting the selection signal, and the second swing range from the data line pair in response to the inverted selection signal; Accepts second and third coded input data signals to form a third to fifth within the first swing range. And a receiver for generating a coded signal. One of the third to fifth coded output data signals is a differential signal of the other signals.
    According to the present invention as described above, the data transmitter for the serial bus is composed of only two operational amplifiers and the output drive stage of the novel structure is advantageous for the integration of the bus interface.
    Hereinafter, with reference to the accompanying drawings will be described in detail preferred embodiments of the serial bus interface device according to the present invention.
    1 is a block diagram illustrating a bus interface device according to an exemplary embodiment of the present invention. Referring to FIG. 1, the bus interface device 100 is connected between the serial bus 200 and the function device 300. The interface device 100 is comprised of a voltage regulator 110, a data transceiver 120, a serial bus interface engine 130, and a device controller 140. The voltage regulator 110 uses a first power supply voltage V DD within a first voltage range (eg, 0-5V) to provide a second power source within a second voltage range (eg, 0-3.3V). Supply the voltage (V RR ). The transceiver 120 uses a plurality of first encoded data signals modulated in a bus-specific format using the two supply voltages V DD and V RR Converts the " bus oriented data signals " into a plurality of second coded data signals in the interface oriented format (hereinafter abbreviated as " interface oriented data signals ") or vice versa. The interface engine 130 executes an interface between the interface-oriented signals and a plurality of third signals in a device-oriented format (hereinafter, abbreviated as device-oriented data signals). The device controller 140 controls the functional device 300 in response to the device oriented data signals.
    Since the interface apparatus 100 according to the present invention assures a data rate of about 1 to 2 Mbps, it is suitable for being used for interfacing between low-speed function devices such as a mouse, a keyboard of a computer, and a serial bus. In addition, the interface device 100 ensures stable operation against load changes. Furthermore, since the bus interface device 100 of the present invention has a simple structure and a small chip size, it is suitable to form a single chip.
    The interface device 100 according to the invention is a serial data bus of digital data processing systems such as personal computers or workstations and function devices providing various additional functions to the system. ) (Eg, keyboard, mouse, joystick, microphone, speakers, etc.). Serial buses that connect their peripherals to personal computers or workstations include USB and FW. Here, for convenience of explanation, the case where the bus interface device according to the present invention is applied to a USB system will be described, but it should be noted that the present invention is not limited thereto.
    USB carries signals and power through a four wire cable. Signaling occurs through two wires and point-to-point segments. The signals on each segment are driven differentially with a cable of 90Ω intrinsic impedance. USB supports three-state operation for bi-directional half duplex operation, and its maximum transfer rate is 124 Mbps.
    There are two modes of USB signaling: full speed mode with a data rate of 12 Mbps ± 0.25% and low speed mode with a data rate of 1.5 Mbps ± 1.5%. These two modes can be supported simultaneously by mode switching in the same USB system. The low speed USB connection is made via an unshielded, untwisted pair cable with a maximum length of 3m. In low speed mode, the rise and fall time of signals on the cable must be greater than 75ns to suppress RFI emissions, with timing delays and signaling skews and It should be less than 300ns to limit distortions. In addition, the low speed bus driver must reach the specific signal levels with smooth rise and fall times.
    USB function devices are, in terms of their power supply, a self-powered device with its own power supply unit and a bus-powered 5V supply voltage via a cable. powered) device. Data signals transmitted between each device and the USB cable swing within a voltage range of 0 to 3.3V, while signals processed within each device swing within a voltage range of 0 to 5V. Therefore, it is necessary to supply at least a 3.3V voltage to each device for the processing of data signals.
    2 shows a preferred embodiment of the voltage regulator 110 of FIG. 1 having a circuit configuration suitable for integrating a USB interface device into a single chip. Referring to FIG. 2, the voltage regulator 110 includes a reference level generator 210, a current amplifier 220, an output driver 230, capacitors 240 and 250, and 3.0 to 300. An output terminal 260 for providing a regulated voltage (V RR ) of 3.6V (preferably 3.3V) and a noise canceling circuit 270 are provided.
    The reference level generator 210 consists of resistors 211-216 connected between a supply voltage V DD of 4.5 to 5.4 V (preferably 5 V) and a ground voltage. The supply voltage V DD is divided by the resistors 211 to 216. Two reference voltages V REF and V BN are output from the nodes 217 and 218 of the reference level generator 210. The reference voltage V REF is about V DD / 3 and the reference voltage V BN is about V DD /4.5. The capacitors 240 and 250 are those provided to remove ripple components of the reference voltages V REF and V BN .
    Current amplifier 220 is configured as a tail-down differential amplifier. The amplifier 220 includes transistors 221 and 222 that function as current mirrors or active loads, transistors 225 and 226 forming differential pairs, and current sinkers. A transistor 227, a feedback resistor 228, and a capacitor 229 serving as a sinker are provided. Reference voltages V REF , V BN are applied to the gates of transistors 225 and 227, respectively. A feedback resistor 234 is connected between the gate of the transistor 220 in the current amplifier 220 and the output terminal 260. Capacitor 229 is connected between node 224 of current amplifier 220 and the output terminal 260. This capacitor 229 is provided to compensate for the difference between the phase of the input voltage of the current amplifier 220 and the phase of the output voltage.
    The output driver 230 is composed of a pull-up transistor 231 and a pull-down transistor 232. The gate of the pull-up transistor 231 is connected to the node 224 of the current amplifier 220. The reference voltage V BN is applied to the gate of the pull-down transistor 232.
    The noise canceling circuit 270 on the output terminal 260 consists of a resistor 271 and a capacitor 272 as shown. The resistor 271 is for preventing the capacitor 272 from being destroyed by the electrostatic discharge (ESD).
    3 is a circuit diagram illustrating the transceiver 120 of FIG. 1. Referring to FIG. 3, the transceiver 120 includes a receiver 310, a transmitter 330, and a control logic 320. As is well known, in a USB system, data strings are coded in a Non Return to Zero Inverted (NRZI) coded fashion and then transmitted over a USB cable.
    Receiver 310 accepts a pair of bus oriented data signals DM and DP (i.e., NRZI signals swinging in the voltage range of 0 to 3.3V) from a USB cable to interface for serial interface engine 130. Generate directed data signals RXDM, RXD and RXDP (ie, signals swinging in the voltage range of 0-5V). The interface oriented data signals RXDM and RXDP are signals corresponding to the bus oriented data signals DM and DP, respectively. The interface oriented data signal RXD is a differentially amplified signal of the bus oriented data signals DM and DP. These interface oriented data signals RXDM, RXD and RXDP are provided to the serial interface engine 130.
    The USB transmitter 330 receives interface oriented data signals NRZI and EOP (eg, signals swinging in a voltage range of 0 to 5V) from the serial interface engine 130 to allow bus oriented data signals DM and DP. (E.g., signals swinging in the voltage range of 0 to 3.3V). The bus oriented data signals DM and DP are transmitted over a USB cable.
    Receiver 310 and transmitter 330 are controlled by serial interface engine 130 to be mutually exclusive. The control logic 320 configured by the inverter 321 selectively activates the receiver 310 or the transmitter 330 in response to the selection signal SEL # from the serial interface engine 130. In detail, when the select signal SEL # from the serial interface engine 130 is activated, the control logic 320 enables the USB transmitter 330. On the other hand, when the select signal SEL # is deactivated, the control logic 320 enables the USB receiver 310. The control logic 320 may include a first signal EN # having a phase difference of 180 degrees with a phase of the selection signal SEL #, and a second signal having a phase equal to that of the selection signal SEL #. Generates (OE #). The first signal EN # is provided to the receiver 310, and the second signal EO # is provided to the transmitter 330. Receiver 310 and transmitter 330 are activated in response to the first and second signals EN # and OE # at a low level, respectively.
    4 is a circuit diagram illustrating a preferred embodiment of the receiver 310 of FIG. In FIG. 4, reference numeral 410 denotes a circuit for differentially amplifying bus oriented data signals DM and DP to generate an interface oriented differential signal RXD, and reference numeral 420 denotes a bus oriented data signals DM. And a circuit for converting DP) into interface-oriented data signals RXDM and RXDP. The circuit 410 includes a differential amplifier 411 and a level shifter 423. The circuit 410 further includes inverters 412 and 414. Each of the inverters 412 and 414 functions as a signal buffer. Circuit 420 includes two Schmitt triggers 421 and 421 ', two level shifters 423 and 423', and output drive logic 425. This circuit 420 also includes inverters 422, 424, 422 'and 424' as signal buffers.
    The differential amplifier 411 is provided with data signals DM and DP from the bus and a select signal EN # from the control logic 320. The data signals DM and DP are also provided to the level shifters 421 'and 421, respectively. In addition, the selection signal EN # is provided to the output driving logic 425. Table 1 below is a truth table of the receiver 310 according to the present invention.
    inputPrintcondition EN #DMDPRXDMRXDPRXD OneXXOne00Rx Disable 00000XSingle Ended Zero 0One0One00Differential Zero (J-State) 00One0OneOneDifferential One (K-State) Where X represents Don't Care.
    5A and 5B are circuit diagrams showing a detailed circuit configuration of the receiver 310 of FIG. 4 implemented according to Table 1 above.
    First, referring to FIG. 5A, the differential amplifier 411 is composed of transistors 11 to 19. The differential pairs 13 and 14 of the amplifier 411 are connected to the USB data lines 343 and 344 through resistors 510 and 511 respectively. The node N1 of the differential amplifier 411 is supplied with a regulated voltage V RR from the voltage regulator 110. Node N2 of the differential amplifier is provided with a select signal or enable signal EN # from control logic 320. The level shifter 413 is composed of transistors 22-29. Between the differential amplifier 411 and the level shifter 413 is a CMOS inverter 412 consisting of transistors 20 and 21. As shown in the figure, the output stage of the circuit 410 is provided with an active filter circuit 513 for noise removal. Another CMOS inverter 414 consisting of transistors 30 and 31 is also connected between the level shifter 413 and the active filter circuit 513. The level shifter 413, the inverters 414 and 514, and the active filter circuit 513 are provided with supply voltages of V DD , respectively. The signal filtered by the active filter circuit 513 is output as an interface directed signal through the inverter 514. The filter circuit 513 will be described later in detail. The output of the inverter 514 is provided to the serial interface engine 130 as a differential signal RXD of bus oriented data signals DM and DP.
    FIG. 5B shows a detailed circuit configuration of the circuit 420 of FIG. 4 according to Table 1. Referring to FIG. 5B, the schmitter trigger 421 includes transistors 32 to 42. The schmitt trigger 421 'is composed of transistors 32-42, and as shown in Fig. 5B, the circuit configuration of the schmitt trigger 421' is the same as that of the schmitt trigger 421. The schmitt triggers 421 and 421 ′ are provided with the output voltage V RR of the voltage regulator 110. The select signal EN # from the control logic 320 is applied to the schmitter triggers 421 and 421 ′ through the active filter circuit 515. More specifically, the output of the filter circuit 512 is provided to the schmitter trigger 421 through the inverter 516. The output of the filter circuit 512 is directly provided to the schmitter trigger 421 ′. The schmitter trigger 421 is enabled / disabled by its transistors 36 and 37 being turned on / off in response to the output of the inverter 516. Similarly, the schmitter trigger 421 'is enabled / disabled as its transistors 36' and 37 'are turned on / off in response to the select signal NE #. Furthermore, bus oriented data signals DM and DP are applied to input nodes N3 and N4 of the schmitter triggers 421 and 421 ', respectively. The schmitter trigger 421 generates an output signal with hysteresis in response to the swing of the bus oriented data signal DM. Similarly, the schmitter trigger 421 'also generates an output signal with hysteresis in response to the swing of the bus oriented data signal DP. Output signals of the schmitter triggers 421 and 421 'are provided to the level shifters 423 and 423', respectively, via inverters 422 and 422 '.
    The level shifter 423 is composed of transistors 46-54. The level shifter 423 'is composed of transistors 46'-54', and the circuit configuration of the level shifter 423 'is the same as that of the level shifter 423, as shown in FIG. 5B. . The level shifters 423 and 423 'are provided with supply voltages of V DD , respectively. By these level shifters 423 and 423 ', bus oriented data signals in the voltage range of 0 to 3.3 V are level-shifted to interface oriented data signals in the voltage range of 0 to 5 V, respectively. Output signals of the level shifters 423 and 423 'are provided to the output drive logic 425 via inverters 56 and 56' and active filter circuits 517 and 518, respectively.
    The output drive logic 425 consists of a NAND gate 60, a NOR gate 62, and inverters 59, 61, 63. This output drive logic 425 corresponds to bus directed data signals DM and DP, respectively, in response to the select signal (or enable signal) EN # and the output signals of the level shifters 423 and 423 '. Generating interface-oriented data signals RXDM and RXDP.
    Referring back to Table 1, when the select signal OE # is deactivated, the differential signal RXD is in a logical 0 state, and the signals RXDM and RXDP are in logical 1 and 0 states, respectively. At this time, the signal receiving operation is not performed. When the selection signal OE # is activated and the signals DM and DP are brought into logical zero states, both the signals RXDM and RXDP are brought into logical zero states. This state is commonly referred to as a "single ended zero state". When the selection signal OE # is activated and the signals DM and DP become the states of logical 1 and 0, respectively, the signals RXDM and RXDP become the states of logical 1 and 0, respectively and the signal RXD Becomes logical zero. This state is commonly referred to as a "differential zero state" or "J-state". Further, when the selection signal OE # is activated and the signals DM and DP become states of logical 0 and 1, respectively, the signals RXDM and RXDP become states of logical 0 and 1, respectively, and The signal RXD is brought to the logical one state. This state is commonly referred to as a "differential one state" or "K-state".
    FIG. 6 is a circuit diagram showing a detailed circuit configuration of each of the active filter circuits 513, 515, 517, or 518 shown in FIGS. 5A and 5B. Referring to FIG. 6, the active filter circuit includes a delay circuit 610, a combinational logic 620, and capacitors 630 and 640. Delay circuit 610 is composed of inverters 611-617. Combination logic 620 is comprised of AND gate 621, NOR gates 622, 623 and 624, and inverter 625. As shown, NOR gates 623 and 624 are latched to each other. The filter circuit having the above configuration exhibits excellent performance in removing noise and glitches in the signal.
    FIG. 7 is a circuit diagram illustrating a preferred embodiment of the transmitter 330 of FIG. 3. Referring to FIG. 7, the transmitter 330 includes a state controller 710, a tilt controller 720, and output drivers 730 and 740. The transmitter 330, as shown in the figure, output signals of bus oriented format in response to the input signals NRZI, EOP and EO # of the interface oriented format provided from the serial interface engine 130. DM and DP). Two of the components of the transmitter 330 except for the state controller 710 are provided with two supply voltages V DD and V RR . However, only the power supply voltage of V DD is provided to the state controller 710.
    The tilt controller 720 determines when the bus oriented format output signals DM and DP will be driven to their defined data states in response to the input signals NRZI, EOP and EO # in the interface oriented format. Generate state control signals. The tilt controller 720 generates slope control signals for controlling slopes, that is, edge rates, of the output signals DM and DP in bus-oriented format in response to the state control signals. The output drivers 730 and 740 generate bus oriented data signals DM and DP, respectively, to be transmitted over a USB cable in response to the state control signals and the tilt control signals.
    Table 2 below is a truth table of the transmitter 330 according to the present invention.
    inputPrintcondition OE #NRZIEOPDMDP OneXXZZHigh impedance 0XOne00Single Ended Zero 000One0Differential Zero 0One00OneDifferential one Where X and Z represent Don't Care and High Impedacne, respectively.
    8A-8D are detailed circuit diagrams of the transmitter 330 of FIG. 7 implemented according to Table 2 above.
    First, FIG. 8A is a detailed circuit diagram of the state controller 710. Referring to FIG. 8A, input signals NRZI, EOP and EO # in interface oriented format from serial interface engine 130 are provided to state controller 710. The state controller 710 may include the input signals, i.e., the coded data signal NRZI, the data end signal EOP indicating the end of the coded data signal NRZI, and the selection signal (or output enable signal). The first to sixth state control signals FNI, FNI #, which determine when the output signals DM and DP of the bus oriented format will be driven to their defined data states in response to (EO #). PEN_DM, NENL_DM, PEN_DP, and NENL_DP). As shown, this state controller 710 includes inverters 821, 824, 825, 826, 829, 831, 833, 834, 837, 839, and 841, and AND gates 827, 832, 835, and 840. ), Filter circuits 823, 828 and 836, and NOR gates 830 and 838.
    The inverter 821 logically inverts the output enable signal OE # to generate the first state control signal FNI. This state control signal FNI is provided to the inverter 824 through the filter circuit 823. The inverter 824 logically inverts the state control signal FNI filtered by the filter circuit 823 to generate the second state control signal FNI #. The inverter 825 logically inverts the data end signal EOP. Inverter 351 logically inverts the coded data signal NRZI. AND gate 827 performs logical ANDing of the outputs of inverters 825 and 826. The output of this inverter 351 is provided to the inverter 829 through the filter circuit 828. The inverter 829 logically inverts the filtered output of the AND gate 827.
    The NOR gate 830 performs logical NORing on the state control signal FNI # and the output of the inverter 829. The output of the NOR gate 830 is output as the third state control signal PEN_DM through the inverter 831. The NAND gate 832 performs logical NANDing on the state control signal FNI and the output of the inverter 829. The output of the NAND gate 832 is output as the fourth state control signal NENL_DM through the inverter 833. Inverter 834 logically inverts the output of inverter 826. AND gate 835 performs logical endings to the outputs of inverters 825 and 834. The output of this AND gate 835 is provided to inverter 837 via filter circuit 836. The inverter 837 logically inverts the filtered output of the AND gate 835.
    The NOR gate 838 performs logical knocking on the state control signal FNI # and the output of the inverter 837. The output of the NOR gate 838 is output as the fifth state control signal PEN_DP through the inverter 839. The NAND gate 840 performs logical NAND on the state control signal FNI and the output of the inverter 837. The output of the NAND gate 840 is output as the sixth state control signal NENL_DP through the inverter 841. Signals PEN_DM and NENL_DM are maintained at high and low levels, respectively, when transmitter 330 transmits data signals onto bus 200. At this time, the signals PEN_DP and NENL_DP are also maintained at high and low levels, respectively.
    In the state controller 710 as described above, each of the filter circuits 823, 828, and 836 has the same or similar configuration as the filter circuit of FIG.
    8B is a detailed circuit diagram of the tilt controller 720. Referring to FIG. 8A, the tilt controller 720 is supplied with the output voltage V RR (ie, 3.3V) of the voltage regulator 110 as its power supply voltage. In addition, the tilt controller 720 receives the state control signals FNI and FNI # in the interface-oriented format (ie, 5V) from the state controller 710 so that the first to the bus-oriented format (ie, 3.3V) are provided. Generate third slope control signals PBIAS, HVDD and NBIAS. As shown, the tilt controller 720 includes power nodes 350 and 360 and state controller 710 to which the supply voltage V RR and the ground voltage V SS from the voltage regulator 110 are applied, respectively. Input nodes 801 and 802 for receiving the state control signals FNI and FNI # respectively, and output nodes 811 and 812 for outputting the gradient control signals PBIAS, HVDD and NBIAS, respectively. And 813) or (811 ', 812' and 813 '), p-channel type MOS transistors 851, 852 and 853, n-channel type MOS transistors 856 and 857, resistor 854 and 855 and MOS capacitor 858.
    One end of the current path (ie, source-drain channel) of the transistor 851 is connected to the power supply node 350, and its control terminal (ie, gate) is input. Is connected to node 801. One end of the current path of transistor 852 is connected to the other end of the current path of transistor 851, and its control terminal is connected to input node 802. The current path of transistor 853 is connected between a power node 350 and an output node 811 or 811 ', the control terminal of which is the junction of the current paths of the transistors 851 and 852 and the output node ( 811 or 811 '). Resistor 854 is connected between output node 811 or 811 'and output node 812 or 812'. Resistor 855 is connected between output node 812 or 812 'and output node 813 or 813'. The current path of transistor 856 is connected between output node 813 or 813 'and the power supply node 360, and its control terminal is connected to input node 802. The current path of transistor 856 is connected between output node 813 or 813 'and the power supply node 360, and its control terminal is connected to output node 813 or 813'.
    The tilt controller 720 is enabled / disabled by its transistors 851 and 856 being turned on / off in response to input signals FNI and FNI #. Capacitor 858 is provided to remove the ripple component of signal HVDD on output node 812 or 812 '. The signal HVDD is maintained at approximately V RR / 2. The signal PBIAS is used to control the slopes of the rising edges of the signals DM and DP, and the signal NBIAS uses the slopes of the falling edges of the signals DM and DP. Used to control Signals PBIAS and NBIAS turn on the transistors in output drivers 730 and 740 (see 861, 864, 867, 868, 861 ', 864', 867 'and 868' in FIGS. 8C and 8D). It is maintained at constant voltage levels sufficient to make it work. These signals will be described later in detail. In the tilt controller 720, the transistor 852 functions to minimize power consumption in the standby state.
    8C is a detailed circuit diagram of the output driver 730. Referring to FIG. 8C, the output driver 730 is supplied with the output voltage V RR of the voltage regulator 110. This driver is provided with one operational amplifier 731 having a novel structure. The operational amplifier 731 has a first input terminal 732 for receiving the tilt control signal PBIAS, a second input terminal 733 for receiving the tilt control signal HVDD, and a tilt control signal NBIAS Third input terminal 734 to accept), first output terminal 735 to provide output drive signal PDRVM, second output terminal 736 to provide output drive signal NDRVM And a feedback terminal 737.
    The operational amplifier 731 is composed of transistors 861 to 868. One end of the current path of the transistor 861 serving as a constant current source is connected to the power supply node 350, and its control terminal is connected to an input terminal 732 to which the slope control signal PBIAS is applied. One end of the current path of transistor 862 is connected to the other end of the current path of transistor 861, and its control terminal is connected to input terminal 733 to which the slope control signal HVDD is applied. One end of the current path of the transistor 864 serving as a constant current source is connected to the power supply node 360, and its control terminal is connected to the input terminal 734 to which the slope control signal NBIAS is applied. The current path of transistor 865 is connected between the current paths of transistors 862, 864, and its control terminal is connected to input terminal 733. The current path of transistor 867 serving as a constant current source is connected between power supply node 350 and output terminal 735, and its control terminal is connected to input terminal 732. The current path of transistor 866 is connected between the other end of the current path of transistor 864 and the output terminal 735, and its control terminal is connected to input terminal 733. One end of the current path of transistor 868 serving as a constant current source is connected between power supply node 360 and output terminal 736, and its control terminal is connected to input terminal 734. The current path of transistor 863 is connected between the other end of the current path of transistor 861 and the output terminal 736, the control terminal of which is connected to input terminal 733. In operational amplifier 731, the current gain of each of transistors 861 and 864 is several times greater (preferably two to four times) than that of each of transistors 867 and 868.
    The output driver 730 further includes an output pull-up transistor 869, a current source transistor 871, an output pull-down transistor 870, a current sink transistor 872, and at least one feedback capacitor 783. Equipped.
    The output pull-up transistor 869 has a current path connected between the power supply node 350 and the data line 343, and a control terminal connected to the output terminal 735 of the operational amplifier 731. The current source transistor 871 includes a current path connected between the output terminal 735 of the operational amplifier 731 and the power supply node 350 and a control terminal connected to the node 803 to which the state control signal PEN_DM is applied. Has The output pull-down transistor 870 has a current path connected between the power supply node 360 and the data line 343 and a control terminal connected to the output terminal 736 of the operational amplifier 731. The current sink transistor 872 has a current path connected between the output terminal 736 of the operational amplifier 731 and the power supply node 360 and a control terminal connected to the node 804 to which the state control signal NENL_DM is applied. Has At least one feedback capacitor 738 is connected between the feedback terminal 737 of the operational amplifier 731 and the data line 343.
    In addition, the output driver 730 further includes circuits 877 and 878 for compensating for the change in load capacitance on the data line 343. The resistor 877 is provided to prevent the capacitor 878 from being destroyed by the electrostatic discharge (ESD). The capacitor increases the capacitance inside the circuit. This allows the transmitter circuit to have stable output characteristics against many changes in load.
    8D is a detailed circuit diagram of the output driver 740. Referring to FIG. 8D, the output driver 740 is also supplied with the output voltage V RR of the voltage regulator 110. This driver 740 also has one operational amplifier 741 having a novel structure. This operational amplifier 741 is provided with first to third input terminals 732 ', 733' and 734 'for receiving gradient control signals PBIAS, HVDD and NBIAS, respectively, output drive signals PDRVP and First and second output terminals 735 'and 736' and a feedback terminal 737 'for providing an NDRVP, respectively. The operational amplifier 741 is composed of transistors 861 'to 868', and has the same configuration as the operational amplifier 731. In operational amplifier 741, the current gain of each of transistors 861 ′ and 864 ′ is several times greater (preferably two to four times) than that of each of transistors 867 ′ and 868 ′.
    This output driver 740 also includes an output pull-up transistor 869 ', a current source transistor 871', an output pull-down transistor 870 ', a current sink transistor 872', and at least one feedback capacitor ( 783 '). The output pull-up transistor 869 'is connected to the current path connected between the power supply node 350 and the data line 344 for providing the signal DP and to the output terminal 735' of the operational amplifier 741. Take control terminal. The current source transistor 871 ′ is connected to a current path connected between the output terminal 735 ′ of the operational amplifier 741 and the power supply node 350, and to a node 805 to which the state control signal PEN_DP is applied. Has a control terminal. The output pull-down transistor 870 'has a current path connected between the power supply node 360 and the data line 344, and a control terminal connected to the output terminal 736' of the operational amplifier 741. The current sink transistor 872 'is connected to a current path connected between the output terminal 736' of the operational amplifier 741 and the power supply node 360, and to a node 806 to which the state control signal NENL_DP is applied. Has a control terminal. At least one feedback capacitor 738 ′ is connected between the feedback terminal 737 ′ of the operational amplifier 741 and the data line 344.
    In addition, the output driver 740 further includes circuits 877 'and 878' for compensating for the change in load capacitance on the data line 344. Resistor 877 'is provided to prevent capacitor 878' from being destroyed by electrostatic discharge (ESD).
    In Figs. 8C and 8D, reference numeral A denotes a circuit portion for controlling the rising slope of the signal DM, and reference numeral B denotes a circuit portion for controlling the falling slope of the signal DM. The signals associated with the respective components of the circuit portion indicated by the reference A and the signals associated with the respective components of the circuit portion indicated by the reference B are only in reverse phase relation with each other, and their principle of operation is the same. Therefore, for the convenience of explanation, only the operation principle of the portion A will be described in detail with reference to FIG. 8C.
    First, referring to FIG. 8C, it is assumed initially that the voltage V F on the node 737 is set to V RR / 2. In this case, a virtual ground is established on the node 737. When transmitter 330 transmits data signals DM and DP on bus 200, signals PEN_DP and NENL_DP as well as signals PEN_DM and NENL_DM remain at high and low levels, respectively. do. Also, at this time, the signals PBIAS, HVDD and NBIA from the tilt controller 720 are maintained at their predetermined levels. Thus, transistors 871 and 872 are turned off and transistors 861, 864, 867 and 868 are turned on.
    The edge rate (i.e., slope) dV / dt of the output signal DM determines the current flowing through the feedback capacitor 738 (hereinafter referred to as 'feedback current') I F as shown in Equation 1 below. do.
    Here, C 738 represents the capacitance of the feedback capacitor 738.
    When the slope of the signal DM on the data line 343 matches the target slope or edge rate, the voltage V F on the node 737 is maintained at V RR / 2. In this case, the current (hereinafter, referred to as a “supply current”) I 862 supplied to the node 737 through the transistor 862 is the same as the feedback current I F. Therefore, the voltage of the node 737 does not change. In this case, no voltage change occurs at the output nodes 735 and 736 of the amplifier 731. As a result, the signal DM increases at a constant rate of change.
    During the rising edge of the signal DM, if its slope is significantly smaller than the target slope, the feedback current I F is reduced so that the voltage V F of the node 737 becomes greater than V RR / 2. Thus, the conductivity of the NMOS transistor 862 is reduced, which results in a decrease in current flowing through the transistor 865. As a result, the current I 866 flowing through the transistor 866 increases relatively. This results in a voltage drop at the output terminal 735 of the amplifier 731. This voltage drop increases the amount of current I 869 flowing through the transistor 869 to the data line 343. As a result, the voltage change rate of the signal DM becomes relatively larger.
    During the falling edge of the signal DM, if its slope is significantly less than the target slope, it increases the amount of current I 870 flowing through the transistor 870 from the data line 343. As a result, the voltage change rate of the signal DM becomes relatively larger.
    During the rising edge of the signal DM, if its slope is significantly larger than the target slope, the feedback current I F is increased so that the voltage V F of the node 737 becomes smaller than V RR / 2. . Thus, the conductivity of the NMOS transistor 862 increases, which results in an increase in the current flowing through the transistor 865. As a result, the current I 866 flowing through the transistor 866 is relatively reduced. This results in a voltage rise of the output terminal 735 of the amplifier 731. This increase in voltage reduces the amount of current I 869 flowing through the transistor 869 to the data line 343. As a result, the voltage change rate of the signal DM becomes relatively smaller.
    During the falling edge of the signal DM, if its slope is significantly greater than the target slope, the amount of current I 870 flowing from the data line 343 through the transistor 870 is reduced. As a result, the voltage change rate of the signal DM becomes relatively larger.
    As such, the waveforms of the signals on the major components of the transmitter of FIG. 7 are shown in FIGS. 9A-9H. 9A shows the waveform of the NRZI modulated signals DM and DP transmitted to the bus. FIG. 9B shows the waveform of the HVDD signal, FIG. 9C shows the waveform of the NDRVM signal, and FIG. 9D shows the waveform of the PDRVM signal. 9E shows a feedback signal V F , and FIGS. 9F to 9G show waveforms of the signals NDRVP, PDRVP, and V F ′, respectively.
    Although the invention has been described herein with reference to the preferred embodiments, it will be understood that the invention is not limited thereto.
    As described above, the interface device of the present invention is suitable for use for interfacing between low speed function devices and a serial bus. The interface device also ensures stable operation against load changes. Furthermore, the bus interface device of the present invention has a simple structure and a small chip size, which makes it suitable for forming into a single chip.
    权利要求:
    Claims (37)
    [1" claim-type="Currently amended] A data transmission circuit for transmitting first and second electrical data signals on a pair of first and second data lines:
    First means for generating a plurality of state control signals in response to a plurality of input signals applied from outside to determine when the first and second data signals will be driven to their predetermined data states and;
    Second means for generating a plurality of tilt control signals for controlling an edge rate of the data signals in response to the state control signals;
    Third means for generating the first data signal to be transmitted on the first data line in response to the state control signals and the tilt control signals;
    Fourth means for generating the second data signal to be transmitted on the second data line in response to the state control signals and the tilt control signals;
    And said third and fourth means each comprise only one operational amplifier.
    [2" claim-type="Currently amended] The method of claim 1,
    And the input signals comprise a coded data signal, a data end signal indicative of the end of the coded data signal, and an output enable signal.
    [3" claim-type="Currently amended] The method of claim 2,
    The first and second transmitted data signals are:
    Is driven to a first data state when the data end signal and the output enable signal are activated;
    Is driven into a second data state when the coded data signal is in a first logic state, when the data end signal is inactive, and when the output enable signal is activated; And
    A data transmission circuit driven to a third data state when the coded data signal is in a second logic state, when the data end signal is deactivated, and when the output enable signal is activated.
    [4" claim-type="Currently amended] The method of claim 2,
    And said first and second transmitted data signals are driven to a high impedance state when said output enable signal is deactivated.
    [5" claim-type="Currently amended] The method of claim 2,
    The first means includes a first inverter for logically inverting the output enable signal to generate a first one of the state control signals;
    A second inverter for logically inverting the first state control signal to generate a second one of the state control signals;
    A third inverter for logically inverting the data end signal;
    A fourth inverter for logically inverting the coded data signal;
    A first AND gate to perform logical endings on the outputs of the third and fourth inverters;
    A fifth inverter for logically inverting the output of the first AND gate;
    A third one of the state control signals, the output of the second state control signal and the fifth inverter;
    Second gate logic for receiving the first state control signal and the fifth inverter and generating a fourth one of the state control signals;
    A sixth inverter for logically inverting the output of the fourth inverter;
    A second AND gate to perform logical endings on the outputs of the third and sixth inverters;
    A seventh inverter for logically inverting the output of the second AND gate;
    Third gate logic to receive the second state control signal and the seventh inverter and generate a fifth one of the state control signals;
    And fourth gate logic for receiving the first state control signal and the output of the seventh inverter to generate a sixth of the state control signals.
    [6" claim-type="Currently amended] The method of claim 5,
    The first means are connected between the first and fourth inverters, between the first and gate inverters and between the fifth inverter, and between the second AND gate and the seventh inverter, respectively. And a data transmission circuit additionally comprising filters.
    [7" claim-type="Currently amended] The method of claim 5,
    The second means is:
    First and second power supply nodes to which the first and second power supply voltages are respectively applied from the outside;
    First and second input nodes for receiving the first and second state control signals, respectively;
    First to third output nodes for providing first to third signals of the tilt control signals, respectively;
    A first transistor of a first type having a current path, one end of which is connected to the first power node, and a control terminal, which is connected to the first input node;
    A second transistor of the first type having a current path connected between the other end of the current path of the first transistor and the first output node, and a control terminal connected to the second input node;
    A current path connected between the first power node and the first output node, a connection point of current paths of the first and second transistors, and a control terminal connected to both the first output node. A third transistor of the first type;
    A first resistor connected between the first output node and the second output node;
    A second resistor connected between the second output node and the third output node;
    A capacitor connected to the second output node and the second power node;
    A fourth transistor of the second type having a current path connected between the third output node and the second power node and a control terminal connected to the second input node;
    And a fifth transistor of said second type having a current path connected between said third output node and said second power supply node and a control terminal connected to said third output node.
    [8" claim-type="Currently amended] The method of claim 7, wherein
    The third means is:
    A first input terminal non-inverting terminal for receiving said first tilt control signal, a second input terminal for accepting said second tilt control signal, and a third input terminal for accepting said third tilt control signal An operational amplifier comprising a first output terminal for providing a first output drive signal and a second output terminal and a feedback terminal for providing a second output drive signal;
    A current source transistor having a current path connected between the first output terminal of the operational amplifier and the first power supply node and a control terminal connected to the third state control signal;
    An output pull-up transistor having a current path connected between the first power node and the data line and a control terminal connected to a first output terminal of the operational amplifier;
    A current sink transistor having a current path connected between the second output terminal of the operational amplifier and the second power supply node and a control terminal connected to the fourth state control signal;
    An output pull-down transistor having a current path connected between the second power supply node and the data line and a control terminal connected to a second output terminal of the operational amplifier;
    At least one feedback capacitor connected between said feedback terminal of said operational amplifier and said data line.
    [9" claim-type="Currently amended] The method of claim 8,
    The operational amplifier is:
    A first transistor of the first type having a current path, one end of which is connected to the first power node, and a control terminal connected to the first input terminal to which the first tilt control signal is applied;
    A second type of second type having a current path having one end connected to the other end of the current path of the first transistor and a control terminal connected to the second input terminal to which the second slope control signal is applied; A transistor;
    A third transistor of the second type having a current path having one end connected to the second power node and a control terminal connected to the third input terminal to which the third slope control signal is applied;
    A fourth transistor of the first type having a current path connected between the other ends of the current paths of the second and third transistors and a control terminal connected to the second input terminal;
    A fifth transistor of the second type having a current path connected between the first power node and the first output terminal, and a control terminal connected to the first input terminal;
    A sixth transistor of the first type having a current path connected between the other end of the current path of the third transistor and the first output terminal, and a control terminal connected to the first input terminal;
    A seventh transistor of the first type having a current path, one end of which is connected between the second power node and the second output terminal, and a control terminal connected to the first input terminal;
    An eighth transistor of the second type having a current path connected between the other end of the current path of the first transistor and the second output terminal, and a control terminal connected to the second input terminal; Data transmission circuit.
    [10" claim-type="Currently amended] The method of claim 8,
    And said third means further comprises means for compensating for a change in load capacitance on said first data line.
    [11" claim-type="Currently amended] The method of claim 10,
    Said means for compensating for said change in said load capacitance comprises a resistor and a capacitor connected in series between said output pad and said second power supply node.
    [12" claim-type="Currently amended] The method of claim 7, wherein
    The fourth means is:
    A first input terminal for accepting said first tilt control signal, a second input terminal for accepting said second tilt control signal, and a third input terminal for accepting said third tilt control signal An operational amplifier having a first output terminal for providing a first output drive signal, a second output terminal for providing a second output drive signal, and a feedback terminal;
    A current source transistor having a current path connected to the first power node and the first output terminal of the operational amplifier, and a control terminal connected to the fifth state control signal;
    An output pull-up transistor having a current path connected between the first power supply node and a second output terminal of the second data line, and a control terminal connected to the first output terminal of the operational amplifier; ;
    A current sink transistor having a current path connected between the second power supply node and the second output terminal of the operational amplifier and a control terminal connected to the sixth state control signal;
    An output pull-down transistor having a current path connected between the second power node and the second data line, and a control terminal connected to the second output terminal of the operational amplifier;
    At least one feedback capacitor connected between said feedback terminal of said operational amplifier and said second data line.
    [13" claim-type="Currently amended] The method of claim 12,
    The operational amplifier is:
    A first transistor of the first type having a current path, one end of which is connected to the first power node, and a control terminal connected to the first input terminal to which the first tilt control signal is applied;
    A second type of the second type having a current path having one end connected to the other end of the current path of the first transistor and a control terminal connected to the second input terminal to which the second tilt control signal is applied; With a transistor;
    A third transistor of the second type having a current path having one end connected to the second power node and a control terminal connected to the third input terminal to which the third slope control signal is applied;
    A fourth transistor of the first type having a current path connected between the other ends of the current paths of the second and third transistors, and a control terminal connected to the first input terminal;
    A fifth transistor of the second type having a current path, one end of which is connected between the first power node and the first output terminal, and a control terminal connected to the first input terminal;
    A sixth transistor of the first type having a current path connected between the other end of the current path of the third transistor and the first output terminal, and a control terminal connected to the second input terminal;
    A seventh transistor of the first type having a current path, one end of which is connected between the second power node and the first output terminal, and a control terminal connected to the third input terminal;
    Data comprising an eighth transistor of the second type having a current path connected between the other end of the current path of the first transistor and the second output terminal and a control terminal connected to the second input terminal; Transmission circuit.
    [14" claim-type="Currently amended] The method of claim 12,
    And said fourth means further comprises means for compensating for a change in load capacitance on said second data line.
    [15" claim-type="Currently amended] The method of claim 14,
    Said means for compensating for said change in said load capacitance comprises a resistor and a capacitor connected in series between said output pad and said second power supply node.
    [16" claim-type="Currently amended] The method of claim 2,
    And said transmitted data signal and coded data signals are non-return signals.
    [17" claim-type="Currently amended] The method of claim 1,
    And the data line pairs are data lines of a USB cable.
    [18" claim-type="Currently amended] A data receiving circuit for receiving first and second electrical input data signals from a pair of first and second data lines in response to an enable signal:
    A differential amplifier for generating a differential signal that amplifies a difference between the first input data signal and the second input data signal and swings within the same range as the input data signals;
    A first level shifter for shifting the swing voltage levels of the differential signal to generate a differential signal level-shifted equal to the first output data signal;
    A first Schmitt trigger for generating an output signal having hysteresis characteristics in response to the swing of the first input data signal;
    A second level shifter for shifting swing voltage levels of the output signal of the first Schmitt trigger to generate a first level-shifted output data signal;
    A second Schmitt trigger generating an output signal having hysteresis characteristics in response to the swing of the second input data signal;
    A third level shifter for shifting swing voltage levels of the output signal of the second Schmitt trigger to generate a second level-shifted output data signal;
    And output drive logic for generating second and third output data signals in response to the enable signal and the first and second level shifted output data signals.
    [19" claim-type="Currently amended] The method of claim 18,
    The second and third output data signals are driven to a first data state when both of the input data signals are in a first logic state and when the enable signal is inactive;
    When the first input data signal is in a second logic state, when the second input data signal is in the second logic state, and when the enable signal is activated, in a second data state. Driven; And
    A third data state when the first input data signal is in the first logic state, when the second input data signal is in the second logic state, and when the enable signal is activated Driven data reception circuit.
    [20" claim-type="Currently amended] The method of claim 18,
    The differential amplifier and the Schmitt triggers are disabled when the enable signal is deactivated.
    [21" claim-type="Currently amended] The method of claim 18,
    And the input data signals are coded data signals.
    [22" claim-type="Currently amended] The method of claim 21,
    And the coded data signals are non-return signals.
    [23" claim-type="Currently amended] The method of claim 18,
    Each of the first and second input data signals swings within a range of -0.5V to 3.8V with respect to a reference ground potential.
    [24" claim-type="Currently amended] The method of claim 18,
    And the data line pairs are data lines of a USB cable.
    [25" claim-type="Currently amended] A data transmission / reception circuit for transmitting or receiving electrical data signals to or from a pair of first and second data lines:
    In response to a first coded input data signal, each of which is within a first swing range, a data end signal indicating an end of the first coded input data signal, and a selection signal, each in the second swing range; A transmitter for generating first and second coded output data signals present in the data line pair;
    An inverter for logically inverting the selection signal;
    Receiving the second and third coded input data signals within the second swing range from the pair of data lines in response to the inverted select signal to form a third to fifth coded within the first swing range. A receiver for generating signals;
    One of said third to fifth coded output data signals is a differential signal of other signals.
    [26" claim-type="Currently amended] The method of claim 25,
    The first and second coded output data signals are driven to a first data state when the data end signal and the selection signal are activated;
    Is driven into a second data state when the first coded input data signal is brought into a first logic state, when the data end signal is deactivated, and when the selection signal is activated; And
    And a data transmission / reception circuit driven to a third data state when the first coded input data signal is brought into the second logic state, when the data end signal is deactivated, and when the selection signal is activated.
    [27" claim-type="Currently amended] The method of claim 25,
    And the first and second coded output data signals are driven in a high impedance state when the select signal is deactivated.
    [28" claim-type="Currently amended] The method of claim 25,
    The second and third coded output data signals are both driven to a first data state when the second and third coded input signals are all in a first logic state and the inverted select signal is deactivated. ;
    Is driven to a second data state when the second and third coded input data signals are brought into a second logic state and when the inverted select signal is activated; And
    When the second coded input data signal is in the first logic state, when the third coded input data signal is in the second logic state, and when the inverted select signal is activated. A data transmission / reception circuit driven in a third data state.
    [29" claim-type="Currently amended] The method of claim 25,
    The receiver is a data transmission and reception circuit that is disabled when the inverted selection signal is deactivated
    [30" claim-type="Currently amended] The method of claim 25,
    The data transceiver circuit further includes a voltage regulator for supplying a power supply voltage within the first oscillation range to both the transmitter and the receiver.
    [31" claim-type="Currently amended] The method of claim 25,
    And the transmitter, receiver and voltage regulator are formed on a single semiconductor chip.
    [32" claim-type="Currently amended] In the bus interface to provide communication between the serial bus and the functional device:
    A voltage regulator for supplying a second power supply voltage in the second voltage range using the first power supply voltage in the first voltage range;
    A transceiver that converts the plurality of first signals in a bus oriented format into a plurality of second signals in an interface oriented format using the first and second power voltages and vice versa Wow;
    An interface engine for executing an interface between the second signals in the interface oriented format and a plurality of third signals in a device oriented format;
    A device controller for controlling the functional device in response to the third signals in the device oriented format.
    [33" claim-type="Currently amended] The method of claim 32,
    The transceiver is:
    A first and a first of the bus oriented format, each in response to a data end signal representing an end of the first coded input data signal and the first coded input data signal from the interface engine; A transmitter for generating two coded output data signals and providing them to the serial bus;
    Generating and providing to the interface engine third to fifth coded output data signals of the interface oriented format in response to the second and third coded input data signals of the bus oriented format from the serial bus. With a receiver;
    Control logic to selectively activate the transmitter or receiver in response to a selection signal from the interface engine.
    [34" claim-type="Currently amended] The method of claim 33, wherein
    One of said third to fifth coded output data signals is a differential signal of other signals.
    [35" claim-type="Currently amended] The method of claim 32,
    The voltage regulator, transceiver, interface engine and device controller are formed on a single semiconductor chip.
    [36" claim-type="Currently amended] The method of claim 32,
    And the bus and interface oriented formats are non-return signals.
    [37" claim-type="Currently amended] The method of claim 32,
    The bus is a bus interface.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-03-09|Application filed by 윤종용, 삼성전자 주식회사
    1998-03-09|Priority to KR1019980007784A
    1999-10-05|Publication of KR19990074302A
    2000-11-15|Application granted
    2000-11-15|Publication of KR100272671B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980007784A|KR100272671B1|1998-03-09|1998-03-09|Bidirectional transceiver and bus interface with the same|
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