• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An electronic memory device is disclosed that includes a memory array having a plurality of memory cells arranged in a plurality of units. Each unit is divided into a first portion containing even addressed memory cells and a second portion containing odd addressed memory cells. The column decoder and the row decoder are connected to a memory array for selecting a plurality of memory cells. The sense amplifier is coupled to the memory array to perform read and write operations from the selected memory cell. The address line is a split for applying the split of the even and odd addressed memory cells.
    公开号:KR19990063185A
    申请号:KR1019980055972
    申请日:1998-12-18
    公开日:1999-07-26
    发明作者:카를 페터 페퍼를
    申请人:피터 토마스；지멘스 악티엔게젤샤프트；
    IPC主号:
    专利说明:

    Memory device and its addressing method
    The present invention relates generally to electronic memory devices and more particularly to synchronous dynamic random access memory having an improved structure for operating in burst mode without substantially increasing the size of the memory.
    Dynamic random access memory (DRAM) is used in various electronic systems to store large amounts of digitally encoded information. The speed of DRAMs has become more important because electronic systems using these devices operate at ever increasing speeds. This requires the DRAM device to have faster access times for read and write functions.
    Several techniques have been developed to increase the performance of these devices. One such technique is known as pre-fetching, which is named SCHEME FOR ELIMINATING PAGE BOUNDARY LIMITTATION ON INITIAL ACCESS OF A SERIAL CONTIGUOUS ACCESS MEMORY and is disclosed in U.S. Patent No. 5,285,421, issued February 8, 1994. . Pre-fetching techniques are used in certain types of DRAM types, commonly known as synchronous dynamic random access memory (SDRAM). In this type of device, contiguously located contiguous memory addresses are accessed.
    Pre-fetching techniques take advantage of the sequential access pattern by latching additional data in registers in addition to the data corresponding to a particular address. Additional data is located adjacent to the specific address. By storing additional data fetched in a register, subsequent data can be used as the time required to read the register shorter than the initial access time. Thus, the overall time for multiple sequential accesses is significantly reduced.
    Another known technique is the burst-mode technique disclosed in US Pat. No. 5,392,239, entitled BURST MODE DRAM and licensed to Margulis on February 21, 1995. This technique involves large blocks of data that must be read or written at high speed in successive groups of data. The use of consecutive addresses increases DRAM performance because addressing methods can be simplified. This technique only requires a single initial address to be specified, where additional addresses can be generated by incrementing the initial address. Thus, it is no longer necessary to send a full address with every word of data. Margulis implements burst mode technology using burst mode detectors, counters and buffers.
    SDRAM devices and other types of memory devices require faster access times. For example, a clock frequency of 256M SDRAM is expected to be between 200 MHz and 250 MHz. In order to realize such a device, two bit pre-fetch is generally required. These clock rates require data to be transferred from and to a device using burst mode technology, with one data transfer per clock cycle (4-5 ns). The number of clock cycles or burst length is typically determined by the SDRAM mode register.
    In SDRAM devices, there are two different burst types, likewise determined by the SDRAM mode register. One burst type is sequential mode and the other type is interleaved mode. 1 is a table showing two different burst types with a burst length of four. As shown, the burst type determines the order in which data is accessed depending on the start address. In sequential mode, data is accessed with consecutive addresses, whereas in interleaving mode only the upper or lower addresses are accessed first.
    Implementing burst types in large SDRAM devices such as 256M chips can be difficult and expensive. This is because these devices require very large structures to support themselves.
    It is therefore an object of the present invention to provide an improved structure that enables an SDRAM device to operate in sequential burst mode without substantially increasing the size of the SDRAM device.
    1 is a table illustrating an addressing order for sequential and interleaving burst types.
    2 is a circuit block diagram supporting an SDRAM structure according to the present invention.
    3 illustrates as possible an address path for a DRAM device.
    4 shows a possible data path for a DRAM device.
    5 is a diagram of an SDRAM structure in accordance with the present invention.
    6 illustrates a unit structure of an interleaving burst mode for an SDRAM device in accordance with the present invention.
    7 illustrates a unit structure in sequential burst mode for an SDRAM device in accordance with the present invention.
    8 is a table illustrating an addressing method in sequential burst mode for an SDRAM device having a 4-burst length in accordance with the present invention.
    9 is a table illustrating an addressing method in sequential burst mode for an SDRAM device having a 4-burst length in accordance with the present invention.
    Explanation of symbols on the main parts of the drawings
    10; SDRAM structure support circuit 18; Line address buffer
    14; Column address buffer / counter 16; Thermal decoder
    18; Row address buffer 20; Row decoder
    22; Mode set register 24; Memory array
    26; Sense amplifier 28; I / O Multiplexer
    30; I / O control section 34; Timing unit
    An electronic memory device includes a plurality of memory cells arranged in a plurality of units, each unit including a first portion having a memory cell addressed to an even address and a second portion having a memory cell addressed to an odd address, the plurality of memory cells A column decoder and a row decoder coupled to the memory cell for selecting two memory cells, a sense amplifier coupled to the memory array for performing read and write operations from the selected memory cell and a plurality of address lines coupled to the column decoder. A plurality of address bits, wherein at least one of the address bits is divided into two split bits for application via a split address line to memory cells addressed to the even and odd addresses, wherein the split during memory access Bit for each access in burst mode 1 It is incremented.
    The above objects and other features and advantages of the present invention are described in detail below in connection with the accompanying drawings.
    The present invention focuses on an improved structure for a memory device. Devices of this type include, for example, DRAMs, SDRAMs, and other types of high speed DRAMs and other memory devices. In accordance with the present invention, this structure enables two bit pre-fetching to be used in interleaving mode or sequential mode without substantially increasing the size of the device. However, before describing the details of the present invention, a block diagram of a circuit that can support the improved structure and other DRAM structures is described.
    Referring to Figure 2, a block diagram of a circuit supporting an improved memory structure in accordance with the present invention is shown. The circuit 10 has a terminal 12 that receives an address for selecting a particular memory location of the memory array 24. This address consists of a row address and a column address. The column address portion is received by the column address buffer / counter 14, while the row address portion is received by the row address buffer 18.
    The column address buffer / counter 14 is used to store and increment the column address portion, and the row address buffer is used only to store the row address portion. The column address is increased to enable the use of burst mode techniques in the present invention. As mentioned above, the burst mode technique is an improved method for transmitting address information to the memory device since only one address has to be transmitted for every burst length of the address to be accessed. As an example, a burst length of four requires the column address buffer / counter 14 to increase the column address portion three times to access four memory locations per burst cycle.
    The column address buffer / counter 14 may operate in sequential burst mode and interleaving burst mode as described in the prior art paragraph. Connected to both column address buffers / counters 14 is a mode set register 22, which provides control signals for switching the address buffers / counters 14 between the entire burst modes. In the interleaving mode, the address buffer / counter 14 increments the column address portion according to the third column of FIG. In sequential mode, address buffer / counter 14 increments the column address portion according to the second column of FIG. It should be noted that the description of the invention with a burst length of 4 is meant to be illustrative only. The invention may be configured to operate with larger burst lengths, such as eight or full pages.
    The row address buffer 18 is connected to the row decoder 20, and the column address buffer / counter 14 is connected to the column decoder 16. Decoders 16 and 20 receive addresses stored by column address buffer / counter 14 and row address buffer 18 to access specific memory locations in memory array 24. Decoder 16 and 20 are both connected to memory array 24 as shown to perform this function. In particular, the column decoder 16 is connected to a plurality of column select lines located in the memory array described later. The memory array 24 consists of a plurality of memory cells arranged in a predetermined order, which will be described later in detail. In the present invention, these cells are preferably DRAM cells. Also connected to the memory array 24 is a sense amplifier 26 that performs read and write operations when a particular memory cell is accessed.
    The sense amplifier 26 is connected to an I / O multiplexer 28 which is used to support the pre-fetching operation of the present invention. As mentioned above, high speed DRAM devices as in the present invention require at least two bits of pre-fetch to be used. Pre-fetching improves the performance of these devices because data for adjacent memory locations is transferred to and from memory array 24. In the case of 2-bit pre-fetching, data for two adjacent memory locations is transmitted at once. I / O multiplexer 28 includes a latch that is used to gate pre-fetch data for read and write cycles. Pre-fetch data can be retrieved at I / O terminal 32.
    The I / O control unit 30 connected to the I / O multiplexer 28 supplies timing and control signals for the pre-fetching operation. Timing for the entire SDRAM device circuit is supplied by timing unit 34. Timing unit 34 preferably has a clock frequency between 200 and 250 MHz.
    Referring to FIG. 3, one possible address path for a DRAM device is shown. This DRAM device 36 includes 256M memory subdivided into 16 individual units. Each unit 38 is arranged to include 512 rows individually selected by 512 column select lines CSL. The 512 CSLs are connected to a column decoder 42 as described above that selects columns from the memory array based on the column addresses it receives. When selected, each CSL 40 transmits eight data bits per unit. Up to four units are selected to transmit 32 bits per device. The column decoder 42 and the appropriate address 44 are located near the center of the device known as the spine 46 to minimize the address wire length.
    Referring to FIG. 4, a data path for the same DRAM device 36 as shown in FIG. 3 is shown. An important improvement in this particular device 36 is that it is divided into two parts, the left part 48 and the right part 50 for data purposes. This allows the data connection to be separated between the left eight units 48 and the left sixteen I / O pads 52. Similarly, the data connection is separated between the right eight units 50 and the right sixteen I / O pads 54. This configuration increases the speed of the device due to reduced power consumption and size and shortened wiring for data.
    5, a diagram of an SDRAM structure in accordance with the present invention is shown. This device 56 preferably includes many of the features described with reference to FIGS. 3 and 4. Thus, the device comprises a memory array divided into sixteen individual units arranged in a left portion 58 and a right portion 60. Each unit preferably includes 512 rows that can be individually addressed by 512 CSLs. Wiring for addressing purposes is located in the spine of the device 61.
    Additional features of this device 56 include further subdividing the memory array of the present invention into four banks. This configuration is realized by using four units for each bank. Each bank may preferably be configured to include two units from the left side 62 of the device and two other units from the right side 64.
    In the present invention, each memory bank 62, 64 is individually accessed per each burst length of address. As an example, a burst length of four requires a burst length of four which requires four separate memory locations to be accessed to a particular memory bank 62,64 before the next memory bank is accessed. In addition, for each individual burst address, all four units of memory banks 62 and 64 are preferably accessed. Thus, by selecting one CSL per unit 66, each memory bank 62, 64 is preferably 32 bits long and is configured to supply computer words that form 64 data bit words.
    The device 56 of the present invention preferably utilizes two bit pre-fetch. This is preferably done by selecting two CSLs 66, 68 per each memory unit.
    6, a diagram of a unit structure of interleaving burst mode for an SDRAM device according to the present invention is shown. This particular structure preferably includes 512 column addresses in each unit. Each unit 70 is divided into a first portion and a second portion, where the first portion 72 includes an even addressed memory location and the second portion 76 is an odd addressed memory location. It includes. Corresponding CSLs 79 and 90 and sense amplifiers 80 and 94 are connected to columns 74 and 88. CSLs 79 and 90 are correspondingly connected to column decoders 78 and 92.
    An address line 84 is connected to each of the column decoders 78 and 92. The address line 84 preferably has a bit length of 8 bits. Activating the column decoders of each unit portion 72 and 76 simultaneously is used, which selects odd and even address pairs corresponding to each unit 70 along the row decoder. This requires 64 bits for 2 bits pre-fetch, as described above. Data lines 85 and fetch lines 82 are connected to each of the sense amplifiers 80 and 94. This data line 85 is preferably 8 bits wide and is used to transfer data. Fetch line 82 is preferably one bit wide and provides a timing signal that determines when data from each of the selected address pairs are gated to data line 85 via corresponding sense amplifiers 80 and 94. Is used. This is only because data line 85 is configured to transfer data from a single address at a time.
    During operation, an address, received by the first portion 72 and the second portion 76 of the unit 70 at the same time, is sent over the address line 84. This activates one of the column decoders 78 with the even address of each unit 70 and one of the column decoders 92 with the odd address. In Fig. 6, even and odd address column decoders 78,92 are shown with numbers increasing from left to right. However, this configuration is not necessary. What is needed is that any particular address from address line 84 activates a unique pair of column decoders, and selects a unique even and odd address pair with alternating adjacent ordered addresses.
    The sequence, along with activating the row decoder, selects even and odd addresses in each unit 70 to supply two computer words. The selected even and odd addresses are numbered as interleaving burst mode as described above.
    Data included in the selected even and odd addresses is sent over the data line 85 at the appropriate time. This is accomplished by sending the appropriate signal through the fetch line 82 to the corresponding sense amplifier of each unit 70.
    Implementing the sequential burst mode with two bit pre-fetch is more difficult than implementing the interleaving burst mode described with reference to FIG. This difficulty occurs when an odd address is used to access the first burst data and outputs the second 8 bits of the first 16 bit line. The second burst data outputs the first eight bits of the second sixteen bit line. According to a representative embodiment of the present invention, this problem is solved by dividing one or more address bits.
    7 shows a unit structure in sequential burst mode for an SDRAM device according to the present invention. This structure 96 excludes the addressing method of the column decoder that includes dividing the least significant significant bits applied to each unit 96 (if the count bits are included as addresses, the next least significant address bit). Similar to the structure of 6. 7 shows a configuration in which the burst length is four.
    As shown, 9 bits represent an address (8 address bits and 1 count bit) and there are 8 bit data bits. Line 82 is the count bit or least significant bit of the 9 bit address. Lines 100 and 102 represent the division bits, which are the divisions for the least significant bits of the 9 bit address. Line 98 represents the seven remaining high significant bits of the nine bit address. Line 85 represents an 8 bit data line.
    The operation of the unit structure in sequential burst mode is the same as that of interleaving burst mode except for the different addressing methods described above. This operation portion has been described with reference to FIG. 8, which is a table showing the addressing method for the unit structure in sequential burst mode with a burst length of four. The table of FIG. 8 includes a left column corresponding to an address applied to the left portion 72 of the unit structure 96 and a right column corresponding to the address applied to the right portion 76 of the unit structure 96. Because the present invention incorporates a two bit pre-fetch, the memory array of this device is accessed twice for a burst length of four, indicated by two rows in the table of FIG.
    During operation, a start address is applied to each unit as shown in FIG. Since this description assumes that the burst length is 4, the next least significant bit 130 of the start address needs to be split. The next least significant bit 130 is split by applying it separately to the first and second portions 72 and 76 of the unit structure 96. The least significant bit 104 applied to the first portion 108 is incremented by one, followed by the least significant bit applied to the first portion 112 when the carryover for the increment of the least significant bit 104 occurs. do. The seven high significant address bits (applied to line 98 of FIG. 7) remain unchanged. The second part is identical to the start address. These addresses, as applied to the unit structure, cause the sequentially numbered even and odd addresses to be selected to provide the two computer words needed for the first two bit pre-fetch operation.
    After the first two bit pre-fetch is performed, the address of the first access is incremented to perform the second access. This is accomplished by increasing the second or next least significant bit 112 and 110 of the first access performed by the address buffer / counter 14 described in FIG. Referring to FIG. 8, incrementing the address causes other sequentially numbered even and odd addresses to be selected and provides two computer words for the second two bit pre-fetch operation. In the second access of the SDRAM device according to the invention, the least significant bits 106 and 108 do not change. Thus, the least significant bits remain unchanged from the first access.
    The above described addressing method for the present invention can be generalized for any burst length. First, as described above, the length of the burst determines the number of bits that need to be divided. The number of bits (SB) required to be divided is one less than the square of two and the burst length can be raised, which is expressed as follows.
    Using the above equation for a burst length of 8, two bits are divided. For a full page or burst length of 512, 8 bits are divided. Regardless of the burst length, the bits to be split are applied individually to each part of the unit structure, where the least significant bits applied to the first or left part are incremented by one and the bits applied to the second or right part are started. It remains unchanged from the address.
    The above-described outline is illustrated in FIG. 9, which is a table of addressing methods for the unit structure in sequential burst mode with a burst length of eight. Since a burst length of 8 is assumed, the next two bits 114,116 of the least significant bit are divided. As can be seen, the count bits applied to the first portion 120 are incremented by one and the start address remains unchanged as applied to the first portions 118 and 122. In addition, the address from the first access is incremented for each of the subsequent pre-fetching operations by continuously increasing the first least significant bit by one.
    Although the invention has been shown and described in detail with reference to preferred embodiments thereof, those skilled in the art will recognize that various changes may be made in form and detail without departing from the scope and spirit of the invention.
    The configuration of the present invention as described above enables the memory device to be implemented at low cost without increasing the size of the memory device and can significantly reduce the access time of the memory device.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] A memory array having a plurality of memory cells arranged in a plurality of memory units divided into a first portion having memory cells addressed to an even address and a second portion having memory cells addressed to an odd address;
    A column decoder and a row decoder coupled to the memory array for selecting a plurality of memory cells of the plurality of memory cells;
    A sense amplifier coupled to the memory array for performing read and write operations from a plurality of memory cells of the selected plurality of memory cells; And
    A plurality of address bits coupled to the column decoder via a plurality of address lines, wherein the plurality of address bits are provided for application through a split address line to memory cells addressed at least one of the even and odd addresses. Partitioned into division bits, wherein during the memory access the division bits are incremented for subsequent sequential accesses in burst mode.
    [2" claim-type="Currently amended] The method of claim 1,
    And at least one of the plurality of address lines is a second least significant bit of a 9 bit address for a burst length of four.
    [3" claim-type="Currently amended] The method of claim 1,
    The number of address bits to be split is determined by taking a value less than one power of 2 of the burst length value to be multiplied, where the burst length value is equal to the number of memory cells accessed for a given burst length of address. And a memory device.
    [4" claim-type="Currently amended] The method of claim 1,
    An address line for providing an address to said column decoder and a row decoder that simultaneously selects an even addressed memory location and an odd addressed memory location for each of said plurality of units for a given access cycle of said memory array; And a memory device further comprising.
    [5" claim-type="Currently amended] The method of claim 1,
    And the plurality of memory cells are a plurality of DRAM cells.
    [6" claim-type="Currently amended] The method of claim 1,
    And the memory array is divided into two parts, each comprising eight units, each of which is individually connected to an I / O pad.
    [7" claim-type="Currently amended] The method of claim 1,
    And a pre-fetch structure.
    [8" claim-type="Currently amended] Address a memory device including a memory array having a plurality of memory cells arranged in a plurality of memory units divided into a first portion having only memory cells addressed to an even address and a second portion having only memory cells addressed to an odd address In the designation method,
    Providing an initial starting address;
    Selecting a predetermined number of least significant bits of the starting address;
    Generating a modified address by incrementing the selected number of least significant bits by one;
    Apply the start address to the second portion of each unit to simultaneously address an even addressed memory location and an odd addressed memory location to each of the units for a given access cycle of the memory array; Applying the modified address to the first portion of each unit; And
    Increasing the selected predetermined number of least significant bits by one for each sequential access in burst mode.
    [9" claim-type="Currently amended] The method of claim 8,
    The selected predetermined number of least significant bits (SB),

    And wherein the burst length is equal to the number of memory cells accessed for the burst length of a given address for the electronic memory device.
    [10" claim-type="Currently amended] The method of claim 8,
    And wherein the selected number of least significant bits of the starting address is applied to the first portion and the second portion of the unit for a split address line.
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    同族专利:
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    EP0924707A3|1999-09-29|
    EP0924707A2|1999-06-23|
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    CN1285077C|2006-11-15|
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    KR100571435B1|2006-07-25|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-12-19|Priority to US8/994,829
    1997-12-19|Priority to US08/994,829
    1997-12-19|Priority to US08/994,829
    1998-12-18|Application filed by 피터 토마스, 지멘스 악티엔게젤샤프트
    1999-07-26|Publication of KR19990063185A
    2006-07-25|Application granted
    2006-07-25|Publication of KR100571435B1
    优先权:
    申请号 | 申请日 | 专利标题
    US8/994,829|1997-12-19|
    US08/994,829|US6138214A|1997-12-19|1997-12-19|Synchronous dynamic random access memory architecture for sequential burst mode|
    US08/994,829|1997-12-19|
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