• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a frequency converter. In the conventional apparatus, since a first-in first-out method is used, a large number of gates are required and not only a large area is required in chip design, but also a circuit for read / write control of the first-in first-out memory is complicated. There was a problem. Accordingly, the present invention includes a linear filter for receiving and filtering a linear signal at a clock a cycle; A counter unit for outputting a selection signal at a clock cycle; By configuring the signal output from the linear filter as a selection output unit for outputting a value selected by the selection signal of the counter unit, not only the first-in first-out memory is used, but also the circuit is simplified and the control circuit can be simplified to reduce the chip size. To reduce latency.
    公开号:KR19990060123A
    申请号:KR1019970080344
    申请日:1997-12-31
    公开日:1999-07-26
    发明作者:황성훈
    申请人:구본준；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Frequency inverter
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency converter, and more particularly, to a frequency converter that minimizes delay time without using a first-in, first-out memory in transmitting data from devices having different operating frequencies.
    1 is a configuration diagram of a conventional frequency converter, and a linear filter 1 for receiving and filtering a linear signal IN, as shown therein; An enable signal generator 2 for generating an enable signal en; A write address generator (3) which receives the enable signal (IN) from the enable signal generator (2) and is enabled and outputs a write address (wa); A read address generator 4 for generating a read address; The signal IN filtered by the linear filter 1 and the write address wa output from the write address generator 3 are received and stored, and the read address output from the read address generator 4 The operation of the conventional apparatus configured as described above, which is constituted by the first-in, first-out memory 5 for outputting the data of ra).
    The signal IN passing through the linear filter 1 receives the enable signal en from the enable signal generator 2 and is first-in first-out memory by the write address wa output from the write address generator 3. Stored in (5). At this time, the linear filter, the write address generator and the enable signal generator 2 operate at a cycle of clock a (cka), and the dummy values of the coefficients α and β of the linear filter 1 are different from each other. Since it is for correcting the period difference between the clocks cka and ckb, it is not stored in the first-in, first-out memory 5.
    The read address generator 4 outputs the read address ra to the first-in first-out memory 5 at a clock ratio ckb having a different period, and outputs the data at the read address ra to the clock ratio ckb. Will print out accordingly.
    Therefore, the value stored in the first-in, first-out memory 5 in the period of the clock cka is output by the clock ratio ckb of another period.
    FIG. 2 is a coefficient table of the linear filter of FIG. 1, in which a dummy value is not written to the first-in first-out memory 5 according to the enable signal en of the enable signal generator 2. As shown in FIG.
    However, in the conventional apparatus, since a first-in, first-out method is used, a large number of gates are required, and a large area is required in chip design, and a circuit for read / write control of the first-in-first-out memory is complicated.
    Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and the frequency converter device not only simplifies the circuit by using the first-in, first-out memory but also makes the control circuit simple and reduces the chip size. The purpose is to provide.
    1 is a block diagram of a conventional frequency converter.
    FIG. 2 is a coefficient table of the linear filter of FIG.
    3 is a configuration diagram of the frequency converter of the present invention.
    4 is a configuration diagram of the selective output unit in FIG. 3;
    5 is a timing diagram of each part of FIG. 4;
    * Description of the symbols for the main parts of the drawings *
    10: linear filter 20: counter part
    30: Selective output unit D1 to D5: Reservoir
    MUX: Multiplexer
    According to an aspect of the present invention, there is provided a frequency converter including: a linear filter configured to receive and filter a linear signal at a clock a cycle; A counter unit for outputting a selection signal at a clock cycle; This is achieved by configuring the signal output from the linear filter as a selection output section for outputting a value selected by the selection signal of the counter section.
    The selection output unit may include: a first storage unit configured to store an output signal of the linear filter at a cycle of clock ai; Second and fourth storage units configured to sequentially store the output of the first storage device at a falling edge of a clock ratio; Third and fifth storage units configured to sequentially store the output of the first storage device at the rising edge of the clock ratio; It consists of a multiplexer which receives the output signals of the fourth and fifth reservoirs and selectively outputs them by a selection signal, which will be described in detail with reference to the accompanying drawings. .
    3 is a configuration diagram of the frequency converter of the present invention, and a linear filter 10 for receiving and filtering a linear signal IN at a cycle of clock a as shown in FIG. A counter unit 20 for outputting a selection signal sel at a period of clock a clock cka; The signal output from the linear filter 10 includes a selection output unit 30 for outputting a value selected by the selection signal sel of the counter unit 20.
    FIG. 4 is a configuration diagram of the selection output unit 30 in FIG. 3. As shown therein, the first storage unit D1 stores the output signal Oflt of the linear filter 10 at a cycle of a clock acka. )Wow; Second and fourth storage units D2 and D4 for sequentially storing the output X0 of the first storage device D1 at the falling edge of the clock ratio ckb; Third and fifth storage units D3 and D5 for sequentially storing the output X0 of the first storage device D1 at the rising edge of the clock ratio ckb; The multiplexer MUX receives the output signals X11 and X21 of the fourth and fifth reservoirs D4 and D5 and selectively outputs them by the selection signal sel. The operation and operation of the present invention constituted will be described.
    FIG. 5 is a timing diagram of each part of FIG. 4, where the difference between the two clocks cka and ckb is 1, and 'X' is not used among the values of X1, X11, X2, and X21, and this value is a multiplexer (MUX). Is discarded by the selection signal sel.
    The linear signal IN outputs the filtered signal Oflt through the linear filter 10. The output signal Oflt includes a dummy value and is used as an input value of the selective output unit 30 in the conventional manner. The output value X0 is generated through the first reservoir D1, and the output value X0 generates X1 at the falling edge of the clock ratio ckb and X2 at the rising edge. The output values X1 and X2 generate X11 and X21 through fourth and fifth reservoirs D4 and D5, respectively, and the two values X11 and X21 are input to a multiplexer MUX and It is selected and output by the selection signal sel to be output. At this time, the ratio of the clock acre cka to the clock ratio ckb is M / N, and M and N are the number of samples between the same rising edges of the clock acre cka and the clock ratio ckb.
    As described above, the frequency converter of the present invention not only simplifies the circuit by using the first-in, first-out memory but also simplifies the control circuit, thereby reducing the chip size and reducing the delay time.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] A linear filter configured to receive and filter the linear signal at a clock a cycle; A counter unit for outputting a selection signal at a clock cycle; And a selection output section for outputting a value selected by the selection signal of the counter section.
    [2" claim-type="Currently amended] The display device of claim 1, wherein the selection output unit comprises: a first storage unit configured to store an output signal of the linear filter at a clock a cycle; Second and fourth storage units configured to sequentially store the output of the first storage device at a falling edge of a clock ratio; Third and fifth storage units configured to sequentially store the output of the first storage device at the rising edge of the clock ratio; And a multiplexer configured to receive the output signals of the fourth and fifth reservoirs and selectively output the selected signals by the selection signal.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-12-31|Application filed by 구본준, 엘지반도체 주식회사
    1997-12-31|Priority to KR1019970080344A
    1997-12-31|Priority claimed from KR1019970080344A
    1999-07-26|Publication of KR19990060123A
    2001-02-01|Application granted
    2001-02-01|Publication of KR100280426B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970080344A|KR100280426B1|1997-12-31|Apparatus of frequency conversion|
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