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    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier for a wireless communication system, and to linearize a power amplifier having a nonlinear characteristic by an adaptive predistortion scheme to simplify the configuration of the device and to improve the influence and accuracy of noise. The present invention compares the digital baseband signal and the digital signal demodulated from the analog high frequency signal when the digital baseband signal is converted into an analog high frequency signal in a wireless communication system, and generates an error signal according to the comparison result. This error signal is multiplied by the digital baseband signal, and then the multiplication result is converted into an analog baseband signal, and the analog baseband signal is converted into an analog high frequency signal and radiated to the outside so that the analog high frequency signal can pass through a power amplifier. We propose a linearization device that eliminates the nonlinear characteristics that are inherent in the process.
    公开号:KR19990043668A
    申请号:KR1019970064709
    申请日:1997-11-29
    公开日:1999-06-15
    发明作者:하지원
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Apparatus and method for linearizing power amplifier of wireless communication system by adaptive predistortion method
    The present invention relates to a power amplifier in a wireless communication system, and more particularly, to an apparatus and method for linearizing a power amplifier having a nonlinear characteristic by an adaptive predistortion scheme.
    The transmitting end of a wireless communication system such as a mobile communication system is provided with a power amplifier for transmitting analog data or digital data. In general, in implementing the power amplifier, a method of increasing spectral efficiency with high power efficiency is required, which is to construct a wireless communication system consuming less power in a limited frequency band. In order to satisfy these general requirements, the general wireless communication system uses baseband data modulation such as spectral efficiency, Quadrature Phase Shift Keying (QPSK) or Quadrature Amplitude Modulation (QAM). The trend is to use amplifiers as power amplifiers.
    On the other hand, when a modulated signal according to a method such as QPSK or QAM passes through a power amplifier implemented as a class C amplifier, there is a problem that distortion such as side lobe reproduction is caused in the output spectrum. This is because Class C amplifiers have strong nonlinear characteristics, and modulation signals according to methods such as QPSK and QAM do not have constant envelope characteristics.
    Various methods have been devised to prevent distortion of the output spectrum due to the nonlinear characteristics of the power amplifier. For example, a method for preventing distortion of an output spectrum is disclosed under US Patent No. 4,291,277, entitled "ADAPTIVE PREDISTORTION TECHNIQUE FOR LINE ARISING A POWER AMPLIFIER FOR DIGITAL DATA SYSTEMS," issued September 22, 1981. The power amplifier proposed by the patent is configured as shown in FIG. 1, which adaptively tracks the nonlinear characteristics of the power amplifier and displaces the baseband data in a direction opposite to that distorted by the nonlinear characteristics of the power amplifier. By pre-distorting and transmitting, the nonlinear characteristics of the high power amplifier are compensated for. That is, the power amplifier is linearized.
    However, the power amplifier having the configuration as shown in FIG. 1 has a problem in that the influence of noise or accuracy is lowered since the operation for removing the distortion phenomenon is processed in the analog domain. For example, an error signal is used to update the value of PREDISTORT RAM 21. At this time, the necessary error signal is generated by analog signals (outputs of the D / A converters 15I and 15Q and outputs of the quadrature phase demodulator 29). Signal) is used. Therefore, there is a fear that the influence or accuracy of noise may be reduced. To solve this problem, high precision adders 17I and 17Q must be used. However, constructing such an analog circuit is a very difficult problem and also has a limitation in accuracy.
    In addition, the power amplifier having the configuration as shown in FIG. 1 has a problem in that many elements are required in terms of hardware configuration. For example, a shift register 21 for generating an address, a modulation signal selection ROM 13 for obtaining a reference signal (I-REFERENCE, Q-REFERENCE) for generating an error signal, and many A number of D / A converters 15I, 15Q, 23I, 23Q are required.
    In addition, there is a problem that it is difficult to apply a power amplifier having the configuration as shown in FIG. 1 to a code division multiple access (CDMA) communication system requiring high speed data processing commercialized these days. For example, an IS-95 CDMA system is required to process data at 1.228 Mbps, but the high power amplifier shown in FIG. 1 cannot process data at this rate.
    Accordingly, an object of the present invention is to provide an apparatus and method for more accurately eliminating distortion caused by a nonlinear characteristic of a power amplifier in a wireless communication system so that the power amplifier has a more accurate linearization characteristic.
    Another object of the present invention is to provide an apparatus and method for simplifying the number of circuit elements required when linearizing a power amplifier in a wireless communication system.
    It is another object of the present invention to provide an apparatus and method for allowing a power amplifier having a linearization characteristic to enable high speed data processing.
    It is another object of the present invention to provide an apparatus and method for implementing a power amplifier that can be used in a CDMA communication system.
    The present invention for achieving the above object is to compare the digital baseband signal and the digital signal demodulated the analog high frequency signal when the digital baseband signal is converted to an analog high frequency signal in a wireless communication system and transmitted according to the comparison result. Generating an error signal, multiplying the error signal by the digital baseband signal, converting the multiplication result into an analog baseband signal, converting the analog baseband signal as an analog high frequency signal, and radiating the analog signal to the outside We propose a linearization device that eliminates the nonlinear characteristics that are obtained when a power amplifier passes through a power amplifier.
    According to a first aspect of the present invention, an apparatus for linearizing a power amplifier having a nonlinear characteristic includes a digital / analog converter for converting a digital baseband signal into an analog baseband signal, and a quadrature phase of the analog baseband signal. A quadrature phase modulator for modulating and outputting a modulated high frequency signal, a power amplifier having a nonlinear characteristic and amplifying and outputting the high frequency signal, an antenna radiating the output of the power amplifier to the outside, and an output of the power amplifier A quadrature demodulator for outputting an analog baseband signal by quadrature demodulating a portion of a coupler coupling a part, an output of the power amplifier coupled by the coupler, and an analog baseband signal output from the quadrature demodulator An analog-to-digital converter for converting the signal into a digital baseband signal; A delay unit for delaying and outputting the digital baseband signal, a comparator for comparing the output of the delay unit and the output of the analog-to-digital converter and generating an error signal according to the comparison result; And at least a compensator for compensating for the nonlinear characteristics of the non-linear characteristic obtained when passing through the error signal.
    According to a second aspect of the present invention, an apparatus for linearizing a power amplifier having a nonlinear characteristic includes a digital / analog converter for converting an applied digital baseband signal into an analog baseband signal, and quadrature phase modulation of the analog baseband signal. A quadrature phase modulator for outputting a modulated high frequency signal, a power amplifier having a nonlinear characteristic and amplifying and outputting a high frequency signal generated by the quadrature phase modulator, and an antenna radiating a signal output from the power amplifier to the outside And a quadrature demodulator for coupling a portion of the output of the power amplifier, a quadrature demodulator for quadrature demodulating the output of the power amplifier coupled by the coupler as a demodulated analog baseband signal; Analog baseband signal output from quadrature demodulator An analog / digital converter for converting a low band signal, a digital shaping filter for digital shaping filtering a signal for transmission, and a digital baseband signal, a first demultiplexer for demultiplexing and outputting the output of the digital shaping filter; And a second demultiplexer for demultiplexing and outputting the output of the analog / digital converter, a delay unit for delaying and outputting the output of the first demultiplexer, an output of the delay unit and an output of the second demultiplexer. And a comparator for outputting an error signal according to the comparison result, and a plurality of digital signal processors for inputting the output of the first demultiplexer are connected in parallel, each of which outputs the output of the first demultiplexer to the error signal. The high frequency signal generated by the quadrature modulator passes through the power amplifier. A digital signal processor block for removing nonlinear characteristics, a multiplexer for multiplexing the output of the digital signal processor block, and a multiplying result of the output of the multiplexer and the output of the digital shaping filter. It consists of a vector multiplier output to the digital to analog converter.
    1 is a view showing the configuration of a power amplifier according to the prior art.
    2 is a view showing the configuration of a power amplifier according to an embodiment of the present invention.
    3 is a view showing the configuration of a power amplifier according to another embodiment of the present invention.
    DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.
    According to the present invention, an apparatus for linearizing a power amplifier having a nonlinear characteristic may be implemented according to two embodiments. 2 is a diagram illustrating a configuration of a linearization device implemented according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a configuration of a linearization device implemented according to another embodiment of the present invention. The apparatus shown in FIG. 2 is suitable for application when the data rate input to the DSP is low enough for one DSP to process. 3 is a device suitable for application to a wireless communication system (eg, IS-95 CDMA communication system) requiring high speed data processing.
    Referring to FIG. 2, a linearization apparatus according to an embodiment of the present invention includes a digital molding filter 100, a digital signal processor (DSP) 110, a D / A converter 131, 132, an LPF 133, 134, 141, 142, and a frequency oscillator. 135, quadrature modulator 136, power amplifier 137, coupler 138, quadrature demodulator 140, A / D converters 143, 144, and antenna 139. The DSP 110 includes a multiplier 111, 112, 117, 118, an address generator 122, a predistortion lookup table 124, an adder 119, 120, a delay unit 113, 114, and a comparator 115,116. The multipliers 111, 112, 117, 118, the address generator 122, the predistortion lookup table 124, and the adders 119, 120 serve to compensate for the nonlinear characteristics of the RF signal corresponding to the digital baseband signal when the power amplifier 137 is powered. Perform.
    In FIG. 2, the digital shaping filter 100 pulses the baseband digital data IN-I and IN-Q and outputs I1 and Q1 signals by band-limiting. The multipliers 111 and 112 multiply the I1 and Q1 signals output from the digital shaping filter 100 and the predistortion values WEIGHT-I and WEIGHT-Q determined by the predistortion lookup table 124, respectively, and output the result as I6 and Q6 signals. . The digital / analog (D / A) converters 131 and 132 convert the I6.Q6 signals, which are output values of the multipliers 111 and 112, into analog signals. A low pass filter (LPF) 133,134 low-pass filters each output of the D / A converters 131,132. The frequency oscillator 135 oscillates reference frequencies for the modulation and demodulation operations of the quadrature modulator 136 and the quadrature demodulator 140.
    The quadrature modulator 136 inputs and modulates the outputs of the low pass filters 133 and 134 and outputs the modulated radio frequency (RF) signals. The power amplifier (PWR AMP) 137 finally amplifies the RF signal from the quadrature modulator 136. The antenna 139 radiates the RF signal output after being amplified by the power amplifier 137 into the air. The coupler 138 feeds back a portion of the RF signal output after being amplified by the power amplifier 137 to the receiver.
    The quadrature demodulator 140 demodulates the RF signal fed back through the coupler 138. The low pass filters 141 and 142 low pass filter the I and Q signals which are output after being demodulated by the quadrature demodulator 140 and output as an analog signal of a desired baseband. The analog / digital (A / D) converters 143 and 144 convert baseband analog signals output from the low pass filters 141 and 142 as digital signals and output them as I3 and Q3 signals, respectively.
    Comparator 115,116 compares the I3, Q3 signals output from the A / D converter 143,144 with the I2, Q2 signals passed through the delay section 113,114 after being output from the digital shaping filter 100, and compares them with the error signals ERR-I, Output as ERR-Q. The multipliers 117 and 118 multiply the error signals ERR-I and ERR-Q, which are the outputs of the comparators 115 and 116, with the error correction coefficients mu i and mu q, and output the multiplication results as I 4 and Q 4 signals. In this case, the error correction coefficients μi and μq applied to one input of the multipliers 117 and 118 are calculated and applied by an adaptive algorithm, and the stability and data convergence speed are taken into consideration. For example, increasing the value of the error correction coefficient μi, μq increases the data convergence speed, but decreases the stability.Decreasing the value of the error correction coefficient μi, μq increases the stability, but slows down the data convergence speed. . The adders 119 and 120 add the I4 and Q4 signals, which are the outputs of the multipliers 117 and 118, and the signals previously determined and output from the predistortion lookup table 124, respectively, and output the addition result as the I5 and Q5 signals.
    An address generator 122 inputs I1 and Q1 signals, which are outputs of the digital shaping filter 100, to determine an address for determining an output value of the predistortion lookup table 124. Delay units 113 and 114 provide a delay time for synchronizing the I1 and Q1 signals output from the digital shaping filter 100 with the I3 and Q3 signals fed back from the coupler 138.
    Now, it is assumed that digital baseband signals I1 and Q1 for transmission are output from the digital shaping filter 100 shown in FIG. The digital baseband signals I1 and Q1 are output as analog baseband signals via the D / A converters 131 and 132 and then low pass filtered by the LPFs 133 and 134. The low pass filtered analog baseband signal is quadrature phase modulated by the quadrature modulator 136 and then output as an RF signal. The power amplifier 137 power-amplifies and outputs the modulated RF signal, and the antenna 139 radiates the power-amplified RF signal to the outside. At this time, a part of the output of the power amplifier 137 is coupled by the coupler 138 and then fed back to the quadrature demodulator 140.
    The quadrature demodulator 140 demodulates the fed back RF signal coupled by the coupler 138 and outputs the demodulated analog baseband signal. The demodulated analog baseband signal is lowpass filtered to the LPFs 141,142 and then converted to a digital baseband signal by the A / D converters 143,144 and then applied to the comparators 115,116.
    At this time, a digital baseband signal, which is an output of the digital shaping filter 100 delayed by the delay units 113 and 114, is applied to the other input of the comparator 115,116. The comparators 115 and 116 compare the outputs of the delay units 113 and 114 with the outputs of the A / D converters 143 and 144 to generate and output error signals ERR-I and ERR-Q according to the comparison result. The error signals ERR-I and ERR-Q generated in this way are applied to the multipliers 117 and 118, multiplied by the error correction coefficients μI and μQ, respectively, and then to the adders 119 and 120. The adders 119 and 120 receive the I1 and Q4 signals output from the multipliers 117 and 118, and add the predistortion values WEIGHT-I and WEIGHT-Q previously determined on the predistortion lookup table 124, respectively, and add the multiplying results as I5 and Q5 signals. Apply to table 124.
    The predistortion lookup table 124 then determines and stores the I5 and Q5 signals as the predistortion values in the address region indicated by the address generator 122 as the predistortion value. The predetermined and stored predistortion values are multiplied by the multipliers 111 and 112 when the digital baseband signals I1 and Q1 are output from the digital shaping filter 100 and then applied to the D / A converters 131 and 132 as I6 and Q6 signals. In this case, the outputs of the multipliers 111 and 112 are pre-distorted signals to remove the nonlinear characteristics when the RF signals corresponding to the digital baseband signals I1 and Q1 are amplified by the power amplifier 137. Therefore, even though the outputs of the multipliers 111 and 112 are lowpass filtered by the LPF 133 and 134, the quadrature phase modulated by the quadrature modulator 136, and then applied to the power amplifier 137 as an RF signal and then amplified and output, the nonlinear characteristics of the multiplier 137 are Will be removed. As a result, the RF signal from which the nonlinear characteristic by the power amplifier 137 is removed is radiated to the antenna 139.
    Referring to FIG. 3, a linearization apparatus according to another embodiment of the present invention includes a digital shaping filter 101, 102, a 1 × 4 demultiplexer (DEMUX) 151, 152, 161, 162, a delay unit 153, 154, a comparator 155, 156, and a 1 × 4 multiplexer. (MUX; Multiplexer) 159,160, multiple DSP blocks 157, 158, vector multiplier 163, D / A converters 131, 132, A / D converters 143, 144, and a clock generator 164. In this case, the output terminals of the D / A converters 131 and 132 are connected to the input terminals of the LPFs 133 and 134 shown in FIG. 2, and the input terminals of the A / D converters 143 and 144 are connected to the output terminals of the LPFs 141 and 142. Although not shown, the quadrature phase modulator 136, the frequency oscillator 135, the quadrature demodulator 140, the power amplifier 137, the coupler 138, and the antenna 139 are also connected in the same manner. The linearization device according to this structure is implemented using the concept of a multiple DSP block, which is an example suitable for applying to a system such as CDMA where the speed of input data is so high that one DSP cannot handle it.
    In FIG. 3, the digital shaping filters 101 and 102 input and output baseband I, Q channel data after pulse shaping. The 1x4 DEMUX 151,152 demultiplexes the high-speed I, Q channel data output from the digital shaping filter 101,102, and lowers the data rate to 1/4 to output the same. The multiple DSP blocks 157,158 perform an adaptive predistortion algorithm using the outputs of the 1 × 4 DEMUX 151,152 and the outputs of the comparators 155,156. 4 × 1 MUX 159,160 multiplexes the output of the multiple DSP blocks 157,158.
    Each of the plurality of DSPs included in the multiple DSP blocks 157 and 158 connected in parallel is similar to the elements of the DSP 110 illustrated in FIG. 2. More specifically, each of the plurality of DSPs includes an address generator 122, a predistortion lookup table 124, a multiplier 111, 112, 117, 118, and an adder 119, 120 among the components of the DSP 110 shown in FIG. In this case, the delay units 113 and 114 and the comparators 115 and 116 included in the DSP 110 shown in FIG. 2 are not provided because the delay units 153 and 154 and the comparators 155 and 156 perform their roles.
    The A / D converters 143 and 144 are fed back from the coupler 138 of FIG. 2 and low-pass filtered by the LPF 141 and 142 to convert the output analog signal into a digital signal. The 1 × 4 DEMUX 161,162 demultiplexes the outputs of the A / D converters 144,143. Comparators 155 and 156 compare the outputs of the 1 × 4 DEMUX 151 and 152 with the outputs of the 1 × 4 DEMUX 161 and 162. The vector multiplier 163 vectorly multiplies the output of the 4 × 1 MUX 159,160 and the output of the digital shaping filter 101,102 by vector.
    The D / A converter 131 converts the output of the 4x1 MUX 159 multiplied by the vector multiplier 163 and the output of the digital shaping filter 101 into analog signals. The D / A converter 132 converts the output of the 4x1 MUX 160 multiplied by the vector multiplier 163 and the output of the digital shaping filter 102 into analog signals and outputs the analog signals. Delay units 153 and 154 delay the signal output from 1x4 DEMUX 151,152 to synchronize the signal output from 1x4 DEMUX 151,152, which is a signal for transmission, with the signal output from 1x4 DEMUX 161,162, which is received and fed back. And print it out. Clock Generator 164 provides clocks for 1x4 DEMUX 151,152,161,162 and 4x1 MUX 159,160.
    In the linearization apparatus illustrated in FIG. 3, the operation of removing the nonlinear characteristic of the power amplifier is performed in the same manner as the linearization apparatus illustrated in FIG. 2. Therefore, a description of the specific operation will be omitted here.
    As described above, the present invention has the advantage of simplifying the configuration of the system by processing using a DSP while reducing the number of elements (shift register removal, D / A converter number reduction) required in terms of hardware configuration in comparison with the conventional method. In addition, since the predistortion processing operation for removing the nonlinear characteristics of the power amplifier is performed in the digital baseband signal region, there is an advantage over the conventional method in terms of noise effect and accuracy. In addition, when high-speed data processing such as CDMA is required, high-speed data processing is possible by multiplexing multiple DSPs in parallel.
    Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.
    权利要求:
    Claims (12)
    [1" claim-type="Currently amended] A method for linearizing a power amplifier having a nonlinear characteristic in a wireless communication system,
    When converting and transmitting a digital baseband signal to an analog high frequency signal, the digital baseband signal is compared with a digital signal demodulated from the analog high frequency signal to generate an error signal according to the comparison result, and the error signal is converted into the digital baseband signal. And multiplying the band signal by converting the result of the multiplication into an analog baseband signal, and converting the analog baseband signal as an analog high frequency signal to radiate to the outside.
    [2" claim-type="Currently amended] A method for linearizing a power amplifier having a nonlinear characteristic in a wireless communication system,
    A first step of converting the digital baseband signal into an analog baseband signal;
    A second process of outputting a modulated high frequency signal by performing quadrature phase modulation on the analog baseband signal;
    A third step of comparing the digital baseband signal and the digital signal demodulated from the high frequency signal and generating an error signal according to the comparison result;
    A fourth step of multiplying the digital baseband signal by the error signal and converting the multiplication result into an analog baseband signal;
    And performing a second process on the analog baseband signal obtained in the fourth process, and then radiating a high frequency signal to the outside through an antenna.
    [3" claim-type="Currently amended] An apparatus for linearizing a power amplifier of a wireless communication system,
    A digital to analog converter for converting a digital baseband signal into an analog baseband signal;
    A quadrature phase modulator configured to quadrature phase modulate the analog baseband signal to output a modulated high frequency signal;
    A power amplifier having a nonlinear characteristic and amplifying and outputting the high frequency signal;
    An antenna radiating the output of the power amplifier to the outside;
    A coupler coupling a portion of the output of the power amplifier,
    A quadrature phase demodulator for quadrature demodulating a part of the output of the power amplifier coupled by the coupler to output an analog baseband signal;
    An analog / digital converter for converting the analog baseband signal output from the quadrature demodulator into a digital baseband signal;
    A delay unit for delaying and outputting the digital baseband signal;
    A comparator for comparing an output of the delay unit and an output of the analog / digital converter and generating an error signal according to the comparison result;
    And at least a compensator for compensating for the nonlinear characteristic of the digital baseband signal when the digital baseband signal passes through the power amplifier using the error signal.
    [4" claim-type="Currently amended] The method of claim 3, wherein the compensator,
    A predistortion lookup table having a plurality of addresses and storing the output of the comparator in a predistortion value for predistorting the digital baseband signal in an address region determined by the digital baseband signal;
    And a multiplier for multiplying the digital baseband signal by a predistortion value stored in the predistortion lookup table and applying the multiplication result to the digital / analog converter.
    [5" claim-type="Currently amended] The compensator of claim 4, wherein the compensator adds the predistortion value previously determined and stored in the predistortion lookup table and the output of the comparator, and outputs the addition result as a value of an error signal to be stored in the predistortion lookup table. Linearizer, characterized in that further comprises an adder.
    [6" claim-type="Currently amended] 6. The apparatus of claim 5, wherein the compensator further comprises a multiplier that multiplies the output of the comparator by a predetermined error correction coefficient and outputs a multiplication result as a value of an error signal to be stored in the predistortion lookup table. Linearization device.
    [7" claim-type="Currently amended] The dictionary according to any one of claims 4 to 6, wherein the pre-distortion value for determining the predistortion value is determined when the predistortion value for predistorting the digital baseband signal is determined from the predistortion lookup table. And an address generator for generating as an address indicating an address area of the distortion lookup table.
    [8" claim-type="Currently amended] An apparatus for linearizing a power amplifier having a nonlinear characteristic in a wireless communication system,
    A digital to analog converter for converting an applied digital baseband signal into an analog baseband signal;
    A quadrature phase modulator configured to quadrature phase modulate the analog baseband signal to output a modulated high frequency signal;
    A power amplifier having a nonlinear characteristic and amplifying and outputting a high frequency signal generated by the quadrature modulator;
    An antenna radiating the signal output from the power amplifier to the outside;
    A coupler coupling a portion of the output of the power amplifier,
    A quadrature phase demodulator configured to quadrature demodulate a part of an output of the power amplifier coupled by the coupler to output a demodulated analog baseband signal;
    An analog / digital converter for converting the analog baseband signal output from the quadrature demodulator into a digital baseband signal;
    A digital shaping filter for digitally filtering the signal for transmission and outputting the digital baseband signal;
    A first demultiplexer for demultiplexing and outputting the output of the digital shaping filter;
    A second demultiplexer for demultiplexing and outputting the output of the analog / digital converter;
    A delay unit for delaying and outputting the output of the first demultiplexer;
    A comparator for comparing the output of the delay unit with the output of the second demultiplexer and outputting an error signal according to the comparison result;
    A plurality of digital signal processors having an output of the first demultiplexer are connected in parallel, each of which is generated by the quadrature phase modulator by predistorting and outputting the output of the first demultiplexer according to the error signal. A digital signal processor block for removing the nonlinear characteristics that a high frequency signal has when passing through the power amplifier;
    A multiplexer for multiplexing the output of the digital signal processor block;
    And a vector multiplier for multiplying the output of the multiplexer by the output of the digital shaping filter and outputting the multiplication result to the digital / analog converter.
    [9" claim-type="Currently amended] The method of claim 8, wherein each of the digital signal processor,
    A predistortion lookup table having a plurality of addresses and storing the output of the comparator in a predistortion value for predistorting the digital baseband signal in an address region determined by the digital baseband signal;
    And a multiplier for multiplying the digital baseband signal by a predistortion value stored in the predistortion lookup table and applying the multiplication result to the digital / analog converter.
    [10" claim-type="Currently amended] 10. The digital signal processor of claim 9, wherein each digital signal processor adds an output of the comparator and a predistortion value previously determined and stored in the predistortion lookup table, and adds the result of the error signal to be stored in the predistortion lookup table. And an adder for outputting the value.
    [11" claim-type="Currently amended] 11. The digital signal processor of claim 10, wherein each digital signal processor further includes a multiplier that multiplies an output of the comparator by a predetermined error correction coefficient and outputs a multiplication result as a value of an error signal to be stored in the predistortion lookup table. Linearization device, characterized in that made.
    [12" claim-type="Currently amended] The dictionary according to any one of claims 9 to 11, wherein the predetermined value for determining the predistortion value is determined when the predistortion value for predistorting the digital baseband signal is determined from the predistortion lookup table. And an address generator for generating as an address indicating an address area of the distortion lookup table.
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    同族专利:
    公开号 | 公开日
    KR100266795B1|2000-09-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-11-29|Application filed by 윤종용, 삼성전자 주식회사
    1997-11-29|Priority to KR1019970064709A
    1999-06-15|Publication of KR19990043668A
    2000-09-15|Application granted
    2000-09-15|Publication of KR100266795B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970064709A|KR100266795B1|1997-11-29|1997-11-29|Adaptive predistortion apparatus and method for linearizing a power amplifier in wireless communication system|
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