• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a method for processing alarms of a plurality of subordinate matchers provided in multiple devices of a 2.5 Gbps synchronous optical transmitter. The present invention includes a first step of determining the type of the dependent matcher; A second step of determining whether the slave matcher is operated, mounted, and whether a power failure occurs; A third step of reading fault related data from the slave matcher if the slave matcher is operating, mounted, and the power source is normal as a result of the determination of the second step; A fourth step of reading out the fault-related data read in the third step and detecting the fault according to the priority corresponding to the type of the subordinate matcher board determined in the first step, and then determining the occurrence and release of the related alarm. Is repeated for every subordinate matcher periodically at time t1 (where t1> 0) and reports to the operator when an alarm is triggered or released. As a result, the present invention enables rapid failure recovery and maintenance of various failures generated in the subordinate matcher, thereby improving the quality of the communication service.
    公开号:KR19990040084A
    申请号:KR1019970060397
    申请日:1997-11-17
    公开日:1999-06-05
    发明作者:최장권
    申请人:유기범；대우통신 주식회사；
    IPC主号:
    专利说明:

    2.Method of processing alarms of tributary interface unit in 2.5Gbps synchronous multiplexing and optical transmission system
    The present invention relates to a method of managing a plurality of subordinate matcher boards provided in multiple devices of a 2.5 Gbps synchronous optical transmitter (hereinafter referred to as SMOT-16), and more particularly, to a method of processing an alarm of each subordinate matcher. It is about.
    Generally, SMOT-16 is asynchronously multiplexed with 44,736 Kbps DS-3 signal or 155,520 Kbps STM-1 or 622,080 Kbps STM-4 optical signal as a slave signal and multiplexed into 2.488 Gbps STM-16 optical signal. It is a device that transmits optically and performs reverse function (SMOT-16: Synchronous Multiplexing Optical Transmission system level-16, DS-3: Digital Signal level-3, STM-1: Synchronous Transport Module level-1, STM-4 : Synchronous Transport Module level-4, STM-16: Synchronous Transport Module level-16)
    1 shows a multiplex structure diagram of a DS-3 signal, and FIG. 2 shows a multiplex structure diagram of STM-1 and STM-4 signals.
    First, as shown in FIG. 1, the DS-3 signal is mapped to a container to be “C-3”, and when a path overhead (POH: Path OverHead) is added thereto, a virtual container (Virtual) is added. Container) "VC-3", and if a pointer is added thereon, it becomes an Administrative Unit "AU-3".
    Thereafter, three "AU-3" are multiplexed into a management unit group (AUG), and a section overhead (SOH: Section OverHead) is added thereto to generate an STM-16 signal when 16 are multiplexed.
    On the other hand, since the STM-1 or STM-4 signal is already fitted to the synchronous multiplex structure, the process of terminating and generating path overhead is not required as shown in FIG. However, termination and processing of the section overhead of the STM-1 and STM-4 signals are performed to extract only the AU signal (AU-3 or AU-4 signal) corresponding to the STM-16 signal in the form of AUG. Multiplexed to
    On the other hand, the SMOT-16 is a multi-device that transmits the dependent signal (DS-3, STM-1 or STM-4) input from the outside as an STM-16 optical signal and performs the demultiplex function, and the transmitted STM -16 It consists of a repeater that performs the function of playing / relaying an optical signal. Among them, the multi-device is composed of high speed self and slave self.
    The high speed self is specifically
    A system clock supply unit (STGU) for selecting a synchronous clock source, inputting and outputting an external clock, and generating and supplying a system clock to each unit;
    A high speed optical transmitter (HSTU) for performing overhead processing for multiplexing the STM-16 signals and optically transmitting the STM-16 signals;
    A high speed optical receiver (HSRU) for performing overhead processing for demultiplexing the STM-16 signal and receiving the STM-16 optical signal;
    A branch / combination controller (ADCU: Add-Drop Control Unit) for branching / coupling the AU-3 signal and the AU-4 signal;
    A main controller (MPU) for monitoring and controlling the high speed unit system and performing an operation terminal access function;
    A data communication unit (DCU) for processing data communication channel (DCC) data of the high speed unit system and to which a network operation system is connected;
    It consists of an order wire unit (OWU) that processes call signals and voice signals for batting and processes E1 data (external clock) of the STM-16 signal.
    The dependent self
    A DS-3 matcher (TIU: Tributary Interface DS-3 Unit) for inputting and outputting three DS-3 signals and converting or inverting the DS-3 signal to an AU-3 signal;
    STM-1 matcher (TI1U: Tributary Interface STM-1) that inputs and outputs one STM-1 optical signal and converts or inverts the STM-1 optical signal into three AU-3 signals or one AU-4 signal Unit);
    STM-4 matcher (TI4U: Tributary Interface STM-4) that inputs and outputs one STM-4 optical signal and converts or inverts the STM-4 optical signal into 12 AU-3 signals or 4 AU-4 signals. Unit);
    A Tributary Processor Unit (TPU) for monitoring and controlling the slave unit system;
    A low data communication unit (LDCU) for processing DCC data of STM-1 or STM-4 optical signals;
    It consists of a selective combination of low order wire units (LOWUs) that process the E1 data of an STM-1 or STM-4 optical signal.
    The slave matching devices (TIU, TI1U, TI4U) have a higher importance on the entire system than other subordinate units, and thus have a redundant structure of operation boards and spare boards. By switching over to the board, the signal flow is not interrupted, that is, the communication service is not interrupted.
    In addition, the slave controller receives up to eight slave matchers and monitors and controls each of them. Here, the eight subordinate matchers are four pairs of subordinate matchers including an operation board and a spare board.
    On the other hand, since the multiple devices of the SMOT-16 configured as described above operate in close association with each other, when a failure occurs in some units, the system cannot be operated and thus a smooth communication service cannot be provided.
    Therefore, it was necessary to find a method for monitoring the entire unit and quickly detecting and dealing with a failure occurring in each unit.
    The present invention has been made in accordance with the above needs, and periodically detects a failure occurring in a plurality of subordinate matchers to determine the occurrence and release of the associated alarm and report the result to the operator side when the subordinate matcher fails It is an object of the present invention to provide an alarm processing method of a subordinate matcher in a 2.5Gbps synchronous optical transmitter that enables rapid maintenance and repair.
    In order to achieve the above object, in the 2.5Gbps synchronous optical transmission apparatus, the alert processing method of the slave matcher may include a first step of determining a type of the slave matcher; A second step of determining whether the slave matcher is operated, mounted, and whether a power failure occurs; A third step of reading fault related data from the slave matcher if the slave matcher is operating, mounted, and the power source is normal as a result of the determination of the second step; A fourth step of reading out the fault-related data read in the third step and detecting the fault according to the priority corresponding to the type of the subordinate matcher board determined in the first step, and then determining the occurrence and release of the related alarm. Is repeated for every dependent matcher periodically at time t1 (where t1> 0), and reports the fact to the operator when an alarm is generated or released.
    In the fourth step, the first step of detecting a failure by reading the failure-related data read in the third step and the failure detected in the first step are continuously detected for a time t2 (where t2> t1). A second step of determining whether the alarm is detected, a third step of determining the occurrence of an alarm related to the failure when the failure is continuously detected for t2 hours, and a failure of which the alarm has been confirmed in the third step. Continuously monitoring and if the failure is not detected, a fourth process of determining whether the failure is not continuously detected for t3 (where t3> t2) and the determination of the fourth process continuously detects the failure for t3 time. If not, it is desirable to have a fifth process for determining the release of the alarm associated with the failure.
    In addition, it is preferable not to monitor the failure for the alarm having a lower priority than the alarm is confirmed to occur in the third process,
    When the occurrence of the alarm is determined in the third step, it is preferable to turn on the corresponding LED (Light Emitting Diode), and when the release of the alarm is determined in the fifth step, turn off the corresponding LED,
    It is preferable to set t1 to 0.2 seconds, t2 to 2 seconds, and t3 to 10 seconds.
    1 is a multiplex structure diagram of a DS-3 signal;
    2 is a multiplex structure diagram of an STM-1 and STM-4 signal;
    3 is a block diagram showing a part of a configuration of a slave controller applied to an embodiment of the present invention;
    4A-4F are flow diagrams illustrating a process of processing an alert of a slave matcher in accordance with one embodiment of the present invention.
    <Description of Symbols for Main Parts of Drawings>
    10: DC / DC converter 20: memory
    30: processor unit 40: IPC interface unit
    50: slave matching interface
    Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
    According to one embodiment of the present invention, a slave controller (hereinafter referred to as a TPU) included in multiple devices of the SMOT-16 monitors 8 slave matchers allocated to itself periodically every 0.2 seconds (200ms), and then any slave If a fault is detected in the matching device, it is determined whether the detection of the fault lasts for 2 seconds, and if the fault is detected continuously for 2 seconds, after confirming the alarm occurrence, the fact is reported to the operator for quick recovery of the fault. ,
    After any alarm is generated, the relevant fault is continuously monitored, and if the fault is not detected, it is determined whether the fault is not detected continuously for 10 seconds from that point. If the fault is not detected continuously for 10 seconds, the alarm is released. After the decision is made, the fact is reported to the operator so that appropriate measures can be taken.
    A subordinate matcher applied to an embodiment of the present invention is provided with a specific purpose integrated circuit (hereinafter referred to as an ASIC), and the register of the ASIC (Application Specific Integrated Circuit) includes data indicating its current state (subordinate match). Type, operation, mounting, power failure, LOS failure, LOF failure, AIS failure, EXBER failure…) are stored in different addresses. That is, each slave matcher periodically determines its own state and changes the value stored in the register when the state changes.
    3 is a block diagram showing a part of a configuration of a TPU applied to an embodiment of the present invention.
    In FIG. 3, reference numeral 10 denotes a DC / DC converter which supplies 5V necessary for the operation of the system by performing a DC / DC conversion by receiving a -48V power source from the outside.
    20 indicates various system programs and application programs, and various status data of the slave matcher (slave matcher type, operation, mounting, power failure, LOS failure, LOF failure, AIS failure, EXBER failure). Whether or not…) is written into the memory section,
    30 stores OS (Operating System) programs necessary for performing various functions in the memory unit 20 or reads from the memory unit 20 and executes the state data stored in the register of the ASIC of each subordinate matcher. A processor section for reading and storing in the memory section 20 and monitoring and controlling each dependent matcher,
    40 denotes an interprocessor communication (IPC) interface that performs an interface function between the processor unit 30 and the MPU so that the hardware state of the eight subordinate matchers can be reported to the main controller of the high-speed self (hereinafter referred to as MPU). Indicates.
    More specifically, the IPC interface unit 40 performs serial communication with the MPU using a high level data link control (HDLC) method using the MT8952 chip. At this time, the transmit / receive clock is supplied from the MPU and used for transmission and reception after converting TTL level to RS-485 level for noise prevention and high speed data transmission.
    In FIG. 3, reference numeral 50 denotes a slave matcher interface unit that performs an interface function between the eight slave matchers and the processor unit 30.
    In addition, although not shown in the drawings, the subordinate self is provided with a plurality of LEDs that enable the display of various failures of each subordinate matcher.
    The TPU configured as described above will be described in detail with reference to the flowchart shown in FIG. 4 to process the alarm of the eight subordinate matchers assigned thereto according to an embodiment of the present invention.
    First, the processor unit 30 of the TPU initializes after setting failure related variables. In this case, three variables for each fault, that is, a CURRENT variable set to "1" if the fault is currently detected, a STATUS variable set to "1" if the occurrence of an alarm related to the fault is confirmed, Each COUNT variable is stored in which time elapsed values necessary for confirming occurrence or release of an alarm related to the corresponding failure are set (S1).
    After the step S1, the processor unit 30 periodically wakes up every 0.2 seconds (200 ms) (S2) and selects one of the eight subordinate matchers managed by itself to determine the type thereof. To this end, the processor unit 30 reads and reads data related to the type of the slave matcher stored in the register of the ASIC of the slave matcher through the slave matcher interface unit 50 (S3).
    After step S3, the processor unit 30 determines whether the slave matching board selected in step S3 is operated, mounted, and whether a power failure occurs. In this case, the processor unit 30 reads and reads data related to operation, mounting, and power failure in the ASIC of the slave unit through the slave unit interface unit 50 (S4). .
    As a result of the determination in step S4, if the subordinate matcher board is operating, mounted, and the power supply is normal, the processor unit 30 is associated with various faults stored in the register of the ASIC of the subordinate matcher through the subordinate matcher interface unit 50. Read the data and set the relevant variables (CURRENT variable and STATUS variable related to each disorder) (S5).
    After the step S5, the processor unit 30 reads the values stored in the CURRENT variable and the STATUS variable related to the clock failure, detects the clock failure of the slave matching unit selected in the step S3, and determines the occurrence or release of the alarm for the clock failure. Report the occurrence or release to the MPU.
    More specifically, the processor unit 30 compares the CURRENT variable value and the STATUS variable value related to the clock failure after step S5 (S6) and determines whether the STATUS variable value is "1" when the two variable values are different (S7).
    If the STATUS variable value related to the clock failure is not "1" as a result of the determination in step S7 (CURRENT = 1, STATUS = 0), the processor unit 30 does not generate an alarm for the clock failure of the slave matcher selected in step S3. However, it is recognized that a clock failure is currently detected and determines whether the value stored in the COUNT variable related to the clock failure is 10. That is, it is determined whether the clock failure is continuously detected for 2 seconds (S8).
    As a result of the determination in step S8, if the value stored in the COUNT variable related to the clock failure is 10, that is, if the clock failure is continuously detected for 2 seconds, the processor unit 30 initializes the lower alarm, turns on the corresponding LED, and the IPC interface unit ( Through 40), the alarm occurrence related to the clock failure is reported to the MPU (S9).
    Initializing the lower alarm means that when an alarm occurs, the lower alarm having a lower priority than the alarm is not monitored. In other words, the alarm processes only the parent alarm and not the subalarms derived from it.
    However, if it is determined in step S8 that the value stored in the COUNT variable related to the clock failure is less than 10, the value stored in the COUNT variable is increased by one (S10) and then branches to step S3. That is, monitoring of the other dependent matcher starts.
    On the other hand, when the determination result of step S7 is that the value of the STATUS variable related to the clock failure is "1" (CURRENT = 0, STATUS = 1), the processor unit 30 generates an alarm for the clock failure of the slave matching unit selected in step S3. Recognizing that no current or current clock failure is detected, it determines whether the value stored in the COUNT variable related to the clock failure is 50. That is, it is determined whether the clock failure is not continuously detected for 10 seconds (S11).
    If the value stored in the COUNT variable related to the clock failure is 50, that is, if the clock failure is not continuously detected for 10 seconds, the processor unit 30 turns off the corresponding LED to inform the release of the alarm against the clock failure. After the alarm release related to the clock failure is reported to the MPU through the IPC interface unit 40 (S12), the process branches to the process of monitoring the failure of the next priority.
    However, if it is determined in step S11 that the value stored in the COUNT variable related to the clock failure is less than 50, the processor unit 30 increases the value stored in the COUNT variable by one (S13) and branches to step S3. That is, monitoring of the other dependent matcher starts.
    Repeating steps S3, S4, S5, S6, S7, S8, and S10 every 0.2 seconds to increase the COUNT variable value related to clock failure by 1, the clock count is detected or the clock failure is not detected. The time elapsed value up to the time of judging the variable value can be easily seen by looking at the value stored in the COUNT variable. For example, if the value of the COUNT variable is 5, it means 5 × 0.2 seconds = 1 second.
    On the other hand, if the two variable values are the same as the comparison result of step S6, the processor unit 30 determines whether the STATUS variable value is "1" (S14).
    If the STATUS variable value related to the clock failure is "1" as a result of the determination in step S14 (CURRENT = 1, STATUS = 1), the processor unit 30 generates an alarm for the clock failure of the subordinate matcher selected in step S3 and the clock is generated. Recognizing that a fault is still being detected, the process branches to S3. That is, monitoring of the other dependent matcher starts.
    However, when the determination result of step S14 indicates that the value of the STATUS variable related to the clock failure is "0" (CURRENT = 0, STATUS = 0), the processor unit 30 cancels the alarm on the clock failure of the slave matching unit selected in step S3. Recognizing that it is a status and no clock failure is detected, it branches to the next priority failure monitoring.
    After the above step S12 or after the step S14 is determined, the processor unit 30 prioritizes the failure detection suitable for each type according to the type of the subordinate matcher determined in step S3, that is, whether the subordinate matcher is one of TIU, TI1U, and TI4U. Apply rankings to monitor for various failures.
    That is, TIU has a failure detection priority of AU-AIS> DS3-LOS> DS3-AIS>. And TI1U and TI4U have fault detection priority LOS> LOF> AIS> EXBER>. Therefore, as shown in FIG. 4, the processor unit 30 monitors various failures in order according to the priority corresponding to the type of the subordinate matcher. At this time, when the occurrence of any alarm is confirmed as described above, the lower alarm is initialized.
    In the above, LOS (Loss Of Signal) indicates signal loss, LOF (Loss Of Frame) indicates frame loss, Alarm Indication Signal (AIS) indicates higher alarm occurrence, and EXBER (Excessive Bit Error Ratio) indicates transient error. Indicates.
    In addition, various failure detection is performed according to the type of the subordinate matcher, and the types of failures according to the types of the subordinate matcher are shown in Table 1 below.
    Dependent matcher typeType of Disability TIUHernia, power failure, hardware failure, DS3-LOS, DS3-AIS, DS3-OOF, AU3-AIS TI1U or TI4UHernia, power failure, hardware failure, LOS, LOF, MS-AIS, EXBER, SD, MS-RDI, AU3-AIS, AU4-AIS, AU3-LOP, AU4-LOP
    (MS-AIS: Multiplex Section Alarm Indication Signal, SD: Signal Degrade, MS-RDI: Multiplex Section Remote Defect Indication, AU3-LOP: AU-3 Loss Of Pointer, OOF: Out Of Frame)
    In addition, as illustrated in FIG. 4, the monitoring process of each failure having a lower priority than the clock failure monitoring process is similar to the clock failure monitoring process described above. That is, in the monitoring of other failures, the CURRENT, STATUS, and COUNT variables related to each failure are used instead of the CURRENT, STATUS and COUNT variables related to the clock failure. Therefore, the description of the monitoring process of the remaining failure is omitted.
    On the other hand, when the MPU reports an alarm occurrence and release of the subordinate matcher from the TPU, the MPU reports to the operator so that the operator instructs the switchover of the subordinate matcher board on which the alarm has been triggered or cleared, or takes other measures to facilitate rapid failover and maintenance. Make it happen.
    In addition, as described above, instead of reporting a related alarm occurrence to the MPU immediately after the TPU detects a failure, reporting the occurrence of an alarm when the failure is continuously detected for 2 seconds results in the detection and no detection of a failure for a short time. Frequently occurring problems can be prevented due to frequent switching of the subordinate matcher board, and instead of reporting the relevant alarm release to the MPU as soon as the failure is not detected, clearing the alarm when the failure is not detected continuously for 10 seconds. By reporting, the alarm can be prevented from being cleared when no fault is detected for a short time, thereby increasing the reliability of the alarm clearing.
    As such, the present invention periodically monitors a plurality of subordinate matchers, determines the occurrence and release of alarms related to various faults generated in the subordinate matcher, and reports the facts to the operator so that rapid disaster recovery and maintenance can be performed. Therefore, there is an effect that can improve the quality of the communication service.
    权利要求:
    Claims (7)
    [1" claim-type="Currently amended] In the multiple devices of the 2.5Gbps synchronous optical transmission device, a method of managing a plurality of subordinate matching devices having a redundant structure of the operation board and the spare board to enable protection switching in the event of a failure,
    A first step of determining the type of the dependent matcher;
    A second step of determining whether the slave matcher is operated, mounted, and whether a power failure occurs;
    A third step of reading fault related data from the slave matcher if the slave matcher is operating, mounted, and the power source is normal as a result of the determination of the second step;
    A fourth step of reading out the fault-related data read in the third step and detecting the fault according to the priority corresponding to the type of the subordinate matcher board determined in the first step, and then determining the occurrence and release of the related alarm. To
    In the 2.5Gbps synchronous optical transmitter, the repeater repeats all the subordinate matching devices periodically every t1 time (t1> 0) and reports the fact to the operator when an alarm is generated or released. How to handle alarm.
    [2" claim-type="Currently amended] The method of claim 1,
    The fourth step is
    A first process of detecting a failure by reading the failure-related data;
    A second step of determining whether the obstacle detected in the first step is continuously detected for a time t2 (where t2> t1);
    A third process of determining occurrence of an alarm related to the failure if a failure is continuously detected for t2 hours as a result of the determination of the second process;
    A fourth process of continuously monitoring a failure in which an alarm is determined in the third process and determining whether the failure is not continuously detected for a time t3 (where t3> t2) if the failure is not detected;
    And a fifth process for determining release of an alarm related to the failure if a failure is not continuously detected for t3 time as a result of the determination of the fourth process. Way.
    [3" claim-type="Currently amended] The method of claim 2,
    The alarm processing method of the subordinate matcher in the 2.5Gbps synchronous optical transmission device, characterized in that the failure for the alarm having a lower priority than the alarm is confirmed in the third process.
    [4" claim-type="Currently amended] The method of claim 2,
    In the third process, when the occurrence of the alarm is determined to turn on the corresponding LED (Light Emitting Diode), and when the release of the alarm is determined in the fifth process the 2.5Gbps synchronous optical transmission device, characterized in that off How to handle the alarm in the slave matcher.
    [5" claim-type="Currently amended] The method according to claim 1 or 2,
    And the t1 is set to 0.2 seconds. The alarm processing method of the slave matcher in the 2.5Gbps synchronous optical transmitter.
    [6" claim-type="Currently amended] The method of claim 2,
    And t2 is set to 2 seconds.
    [7" claim-type="Currently amended] The method of claim 2,
    And the t3 is set to 10 seconds. The alarm processing method of the slave matcher in the 2.5Gbps synchronous optical transmitter.
    类似技术:
    公开号 | 公开日 | 专利标题
    CA2094541C|1999-11-02|Dual hubbing in a bidirectional line-switched ring transmission system
    US7630297B2|2009-12-08|Trail/path protection for SDH/SONET networks
    US5812289A|1998-09-22|Optical repeater and optical transmitter
    DE60129881T2|2007-12-20|Optical transponder and automatic method for identifying an optical signal type
    US5333130A|1994-07-26|Self-healing drop and insert communication network
    DE69727040T2|2005-01-27|Method and device for detecting errors in a network
    US6587235B1|2003-07-01|Method and apparatus for capacity-efficient restoration in an optical communication system
    RU2331157C2|2008-08-10|Method, device and system for optical communication
    AU624168B2|1992-06-04|Tdm demultiplexer with dedicated maintenance channels to indicate high-speed line faults to low speed circuits
    US7068931B2|2006-06-27|Alarm control system and method
    US4633246A|1986-12-30|Time divison multiplex ring
    US6816818B2|2004-11-09|Method, clock generator module and receiver module for synchronizing a receiver module
    US5557437A|1996-09-17|Optical terminal system having self-monitoring function
    US5974027A|1999-10-26|Telecommunications network including a channel switching protection arrangement
    US6366556B1|2002-04-02|Self-healing networks using virtual rings
    US5831970A|1998-11-03|Transmission apparatus
    US5159595A|1992-10-27|Ring transmission system
    ES2214470T3|2004-09-16|Signal protection device type ring 1 / n.
    US6728489B2|2004-04-27|Optical transmission system constructing method and system
    JP4867728B2|2012-02-01|Optical signal multiplexing transmission device
    JP4287382B2|2009-07-01|TECHNICAL FIELD The present invention relates to a terminal relay device of a network.
    DE4410972C2|1999-03-11|Method and network element for transmitting data in a working ring and a protective ring
    DE69434789T2|2007-07-05|Communication system consisting of interconnected, weggeschaltenen ring transmission systems
    US6005694A|1999-12-21|Method and system for detecting optical faults within the optical domain of a fiber communication network
    US5586112A|1996-12-17|Digital crossconnect system for selecting alternate communication routes in case of a transmission fault
    同族专利:
    公开号 | 公开日
    KR100237476B1|2000-01-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-11-17|Application filed by 유기범, 대우통신 주식회사
    1997-11-17|Priority to KR1019970060397A
    1999-06-05|Publication of KR19990040084A
    2000-01-15|Application granted
    2000-01-15|Publication of KR100237476B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970060397A|KR100237476B1|1997-11-17|1997-11-17|Method of processing alarms of tributary interface unit in 2.5gbps synchronous multiplexing and optical transmission system|
    [返回顶部]