• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A CMOS inverter is disclosed that can reduce an electric field applied to an individual device. This includes a first PMOS transistor whose gate is connected to an inverter input terminal, whose source is connected to a power supply voltage, the first NMOS transistor whose first source is connected to its gate, and whose source is grounded. A second PMOS transistor and a second NMOS transistor connected in series between the PMOS transistor and the first NMOS transistor are provided. A first voltage and a second voltage are applied to gates of the second PMOS transistor and the second NMOS transistor, respectively, drains thereof are connected to an output terminal, and a source of the second PMOS transistor is connected to a drain of the first PMOS transistor; The source of the second NMOS transistor is connected to the drain of the first NMOS transistor.
    公开号:KR19990034765A
    申请号:KR1019970056461
    申请日:1997-10-30
    公开日:1999-05-15
    发明作者:김경기；강상석
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    CMOS inverter
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a CMOS inverter capable of reducing the electric field applied to the individual elements constituting the inverter.
    In order to ensure the reliability of individual devices in a semiconductor circuit, an aging process is usually performed for a sufficient time under conditions worse than a normal environment. This aging ensures that the device will operate without defects for a long time after shipping. In order to guarantee the reliability of the device, the device should be less affected by external stress as much as possible, and it is required that stress is not concentrated on a part of the device.
    One of the stresses commonly applied to semiconductor devices is an electric field. In particular, in an MOS (Metal-Oxide-Semiconductor) transistor, when the electric field is excessively applied, the transistor may be damaged and fail to function. This is because the gate oxide film of the transistor having a thin film MOS structure is damaged by an excessive electric field and no longer serves as a gate.
    Inverters, which are the basic units in all circuit configurations of semiconductor integrated circuits, and constituted by CMOS, can also be damaged by the excessive electric fields mentioned. This will be described with reference to the basic circuit diagram of the CMOS inverter shown in FIG.
    As shown in FIG. 1, a general CMOS inverter includes one PMOS transistor Qp and an NMOS Qn.
    For example, when the input signal Vin is input at the high level of the power supply voltage level Vcc, an electric field such as Vgs = 0V, Vgd = Vcc, Vds = Vcc is generated in the PMOS transistor Qp, and the NMOS transistor An electric field such as Vgs = Vcc, Vgd = Vcc, and Vds = 0V is generated in Qn.
    In addition, when the input signal Vin is input at a low level, the output Vout becomes high. Thus, an electric field such as Vgs = Vcc, Vgd = Vcc, and Vds = 0V is generated in the PMOS transistor Qp, and the NMOS transistor is generated. An electric field such as Vgs = 0V, Vgd = Vcc, and Vds = 0V is generated in Qn.
    In this way, an electric field of the power supply voltage level Vcc is applied between the gate and the source or the gate and the drain of the PMOS transistor or the NMOS transistor constituting the CMOS inverter, which puts considerable stress on the transistor constituting the inverter. The effect of this stress is not so great, but prolonged exposure can shorten the life of the device.
    SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a CMOS inverter capable of reducing an electric field applied to an individual element.
    1 is a basic circuit diagram of a conventional CMOS inverter.
    2 is a circuit diagram of a CMOS inverter according to an embodiment of the present invention.
    In the CMOS inverter according to the present invention for achieving the above technical problem, a first PMOS transistor whose gate is connected to the inverter input terminal, the source is connected to the power supply voltage, the first PMOS transistor and its gate are connected, A first NMOS transistor having a source grounded and a second PMOS transistor and a second NMOS transistor connected in series between the first PMOS transistor and the first NMOS transistor, and having a gate at the gate of the second PMOS transistor and the second NMOS transistor A first voltage and a second voltage are respectively applied, and drains thereof are connected to an output terminal, a source of the second PMOS transistor is a drain of the first PMOS transistor, and a source of the second NMOS transistor is connected to the first NMOS transistor. Connected to the drain.
    Here, the first voltage and the second voltage is preferably applied in the range of 0V ≤ first voltage ≤ V DD -Vtp, Vtn ≤ 2 ≤ voltage V DD, respectively.
    Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    2 is a circuit diagram of a CMOS inverter according to an embodiment of the present invention.
    As shown in FIG. 2, the CMOS inverter according to the present invention further includes a second PMOS between the first PMOS transistor Qp1 and the first NMOS transistor Qn1 connected in series with the same input signal Vin. The transistor Qp2 and the second NMOS transistor Qn2 are connected in series. The added second PMOS transistor Qp2 and the second NMOS transistor Qn2 serve to disperse the electric field applied to the first PMOS transistor Qp1 and the first NMOS transistor Qn1.
    1, the electric field applied to each device will be described.
    For example, when the input signal Vin is input at the high level of the power supply voltage level Vcc, the first PMOS transistor Qp1 is turned off, and thus, the first PMOS transistor Q2 is a contact point of the first PMOS transistor and the second PMOS transistor. The voltage obtained by adding the input voltage V A of the second PMOS transistor and the threshold voltage Vt of the first PMOS transistor is applied to one node N1. In addition, since the first NMOS transistor Qn1 is turned on by the input high level signal, 0V is applied to the second node N2 which is a contact point of the first NMOS transistor Qn1 and the second NMOS transistor Qn2.
    Therefore, an electric field such as Vgs = 0V, Vgd = Vcc- (V A + Vt), Vds = Vcc- (V A + Vt) is generated in the first PMOS transistor Qp1, and the second PMOS transistor Qp2 is generated. Electric fields such as Vgs = Vt, Vgd = V A , and Vds = V A + Vt are generated. In addition, an electric field such as Vgs = Vcc, Vgd = Vcc, Vds = 0V is generated in the first NMOS transistor Qn1, and Vgs = V B , Vgd = V B , Vds = in the second NMOS transistor Qn2. An electric field equal to 0V is generated.
    As described above, when the input signal Vin is high, Vgd and Vgs decrease from Vcc to Vcc- (V A -Vt) for the PMOS transistor.
    On the contrary, when the input signal Vin is input at the low level, the first PMOS transistor Qp1 is turned on and the first NMOS transistor Qn1 is turned off. Accordingly, a voltage obtained by subtracting the threshold voltage Vt of the first NMOS transistor from the input voltage V B of the second NMOS transistor is applied to the second node N2, which is a contact point between the first NMOS transistor and the second NMOS transistor. .
    Accordingly, an electric field such as Vgs = Vcc, Vgd = Vcc, Vds = 0V is generated in the first PMOS transistor Qp1, and Vgs = Vcc-V A , Vgd = Vcc-V A in the second PMOS transistor Qp2. , An electric field such as Vds = 0V is generated. In addition, an electric field such as Vgs = Vt, Vgd = Vcc-V B , Vds = Vcc- (V B -Vt) is generated in the first NMOS transistor Qn1, and Vgs = in the second NMOS transistor Qn2. Electric fields such as 0 V, Vgd = Vcc- (V B -Vt), and Vds = V B -Vt are generated.
    As described above, when the input signal Vin is low, Vgd and Vds decrease from Vcc to Vcc- (V B -Vt) for the NMOS transistor.
    Here, the second input voltage of the PMOS transistor (Qp2) and the second NMOS transistor (Qn1) (V A and V B) levels are given the speed side, V by A = 0V, V B = to keep Vcc level It is advantageous. However, in order to reduce the electric field applied to the transistor, it is desirable to adjust the V A level higher than 0 V and adjust the V B level lower than Vcc. That is, the level of the input voltages V A and V B of the second PMOS transistor Qp2 and the second NMOS transistor Qn1 is in the range of 0 V ≤ V A ≤ V DD- Vtp and Vtn ≤ V B ≤ V DD . It is desirable to determine the operating speed and the electric field.
    The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
    As described above, according to the present invention, when the input signal of the CMOS inverter is high, the electric field applied to the PMOS transistor is reduced, and when the input signal is low, the electric field applied to the NMOS transistor is reduced.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] A first PMOS transistor whose gate is connected to an inverter input terminal and whose source is connected to a power supply voltage;
    A first NMOS transistor connected to the first PMOS transistor and a gate thereof and whose source is grounded; And
    A second PMOS transistor and a second NMOS transistor connected in series between the first PMOS transistor and the first NMOS transistor;
    A first voltage and a second voltage are applied to gates of the second PMOS transistor and the second NMOS transistor, respectively, drains thereof are connected to an output terminal, and a source of the second PMOS transistor is connected to a drain of the first PMOS transistor; The source of the second NMOS transistor is connected to the drain of the first NMOS transistor.
    [2" claim-type="Currently amended] The CMOS inverter of claim 1, wherein the first voltage and the second voltage are respectively applied in a range of 0 V ≤ first voltage ≤ V DD- Vtp, and Vtn ≤ second voltage ≤ V DD .
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-30|Application filed by 윤종용, 삼성전자 주식회사
    1997-10-30|Priority to KR1019970056461A
    1999-05-15|Publication of KR19990034765A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970056461A|KR19990034765A|1997-10-30|1997-10-30|Cmos inverter|
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